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Some rather crude implementation (note: Naomi 2 is BROKEN by now, but this change is necessary because we are effectively into Naomi 2 league)

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This commit is contained in:
Angelo Salese 2011-07-05 13:11:44 +00:00
parent 89892a23db
commit 4109afd655
3 changed files with 77 additions and 7 deletions
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14
src/mame/drivers/naomi.c
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@ -1575,20 +1575,20 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64 )
/* Area 1 */
AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_BASE( &dc_texture_ram ) // texture memory 64 bit access
AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_BASE( &dc_framebuffer_ram ) // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
// AM_RANGE(0x06000000, 0x06ffffff) AM_RAM // 32 bit access 2nd PVR RAM
// AM_RANGE(0x07000000, 0x07ffffff) AM_RAM // 64 bit access 2nd PVR RAM
AM_RANGE(0x06000000, 0x06ffffff) AM_RAM AM_BASE( &pvr2_texture_ram ) // 32 bit access 2nd PVR RAM
AM_RANGE(0x07000000, 0x07ffffff) AM_RAM AM_BASE( &pvr2_framebuffer_ram )// 64 bit access 2nd PVR RAM
/* Area 2*/
// AM_RANGE(0x085f8000, 0x085f9fff) AM_READWRITE( pvr_ta_r, pvr_ta_w ) // 2nd PVR registers
// AM_RANGE(0x08800000, 0x0???????) // T&L chip registers
// AM_RANGE(0x0a000000, 0x0???????) // T&L chip RAM
AM_RANGE(0x085f8000, 0x085f9fff) AM_READWRITE( pvr2_ta_r, pvr2_ta_w ) // 2nd PVR registers
AM_RANGE(0x08800000, 0x088000ff) AM_READWRITE32( elan_regs_r, elan_regs_w, U64(0xffffffffffffffff) ) // T&L chip registers
AM_RANGE(0x0a000000, 0x0bffffff) AM_RAM AM_BASE( &elan_ram ) // T&L chip RAM
/* Area 3 */
AM_RANGE(0x0c000000, 0x0dffffff) AM_MIRROR(0xa2000000) AM_RAM AM_BASE(&naomi_ram64)
/* Area 4 */
AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_WRITE( ta_fifo_poly_w )
AM_RANGE(0x10800000, 0x10ffffff) AM_MIRROR(0x02000000) AM_WRITE( ta_fifo_yuv_w )
AM_RANGE(0x10000000, 0x107fffff) AM_WRITE( ta_fifo_poly_w )
AM_RANGE(0x10800000, 0x10ffffff) AM_WRITE( ta_fifo_yuv_w )
AM_RANGE(0x11000000, 0x11ffffff) AM_WRITE( ta_texture_directpath0_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
/* 0x12000000 -0x13ffffff Mirror area of 0x10000000 -0x11ffffff */
AM_RANGE(0x13000000, 0x13ffffff) AM_WRITE( ta_texture_directpath1_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)

8
src/mame/includes/dc.h
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@ -204,8 +204,16 @@ extern UINT32 pvrctrl_regs[0x100/4];
extern UINT64 *dc_texture_ram;
extern UINT64 *dc_framebuffer_ram;
extern UINT64 *pvr2_texture_ram;
extern UINT64 *pvr2_framebuffer_ram;
extern UINT64 *elan_ram;
READ64_HANDLER( pvr_ta_r );
WRITE64_HANDLER( pvr_ta_w );
READ64_HANDLER( pvr2_ta_r );
WRITE64_HANDLER( pvr2_ta_w );
READ32_HANDLER( elan_regs_r );
WRITE32_HANDLER( elan_regs_w );
WRITE64_HANDLER( ta_fifo_poly_w );
WRITE64_HANDLER( ta_fifo_yuv_w );
VIDEO_START(dc);

62
src/mame/video/dc.c
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@ -134,6 +134,11 @@ static void pvr_accumulationbuffer_to_framebuffer(address_space *space, int x,in
UINT64 *dc_framebuffer_ram; // '32-bit access area'
UINT64 *dc_texture_ram; // '64-bit access area'
UINT64 *pvr2_texture_ram;
UINT64 *pvr2_framebuffer_ram;
UINT64 *elan_ram;
static UINT32 tafifo_buff[32];
static emu_timer *vbout_timer;
@ -2621,3 +2626,60 @@ SCREEN_UPDATE(dc)
return 0;
}
/* Naomi 2 attempts (TBD) */
READ64_HANDLER( pvr2_ta_r )
{
int reg;
UINT64 shift;
reg = decode_reg_64(offset, mem_mask, &shift);
switch (reg)
{
}
printf("PVR2 %08x R\n",reg);
return 0;
}
WRITE64_HANDLER( pvr2_ta_w )
{
int reg;
UINT64 shift;
UINT32 dat;
reg = decode_reg_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
//printf("PVR2 %08x %08x\n",reg,dat);
}
READ32_HANDLER( elan_regs_r )
{
switch(offset)
{
case 0: // ID chip (TODO: BIOS crashes / gives a black screen with this as per now!)
return 0xe1ad0000;
case 0x04/4:
return 0x12;
case 0x14/4:
return 0x2029;
case 0x74/4:
return space->machine().rand() & 0x3f;
default:
printf("%08x %08x\n",cpu_get_pc(&space->device()),offset*4);
break;
}
return 0;
}
WRITE32_HANDLER( elan_regs_w )
{
// ...
}