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Fixed incorrect MUL number of cycles
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@ -1908,7 +1908,7 @@ static void HC11OP(mul)(hc11_state *cpustate)
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REG_D = (UINT8)REG_A * (UINT8)REG_B;
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REG_D = (UINT8)REG_A * (UINT8)REG_B;
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CLEAR_C(cpustate);
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CLEAR_C(cpustate);
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cpustate->ccr |= (REG_B & 0x80) ? CC_C : 0;
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cpustate->ccr |= (REG_B & 0x80) ? CC_C : 0;
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CYCLES(cpustate, 3);
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CYCLES(cpustate, 10);
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}
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}
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/* PSHA 0x36 */
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/* PSHA 0x36 */
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