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mcs51: New version of old hack to break out of JB INT0/INT1 loops when interrupt is triggered

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This commit is contained in:
AJR 2019-03-22 12:01:59 -04:00
parent 0b27ba31c4
commit 41f23bcc2b
2 changed files with 16 additions and 0 deletions
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12
src/devices/cpu/mcs51/mcs51.cpp
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@ -874,6 +874,8 @@ uint8_t mcs51_cpu_device::bit_address_r(uint8_t offset)
int distance; /* distance between bit addressable words */
/* 1 for normal bits, 8 for sfr bit addresses */
m_last_bit = offset;
//User defined bit addresses 0x20-0x2f (values are 0x0-0x7f)
if (offset < 0x80) {
distance = 1;
@ -1358,6 +1360,8 @@ void mcs51_cpu_device::execute_op(uint8_t op)
m_recalc_parity = 0;
}
m_last_op = op;
switch( op )
{
case 0x00: nop(op); break; //NOP
@ -1777,6 +1781,10 @@ void mcs51_cpu_device::check_irqs()
return;
}
// Hack to work around polling latency issue with JB INT0/INT1
if (m_last_op == 0x20 && ((int_vec == V_IE0 && m_last_bit == 0xb2) || (int_vec == V_IE1 && m_last_bit == 0xb3)))
PC = PPC + 3;
//Save current pc to stack, set pc to new interrupt vector
push_pc();
PC = int_vec;
@ -2126,6 +2134,8 @@ void mcs51_cpu_device::device_start()
save_item(NAME(m_ppc));
save_item(NAME(m_pc));
save_item(NAME(m_last_op));
save_item(NAME(m_last_bit));
save_item(NAME(m_rwm) );
save_item(NAME(m_cur_irq_prio) );
save_item(NAME(m_last_line_state) );
@ -2213,6 +2223,8 @@ void mcs51_cpu_device::device_reset()
/* Flag as NO IRQ in Progress */
m_irq_active = 0;
m_cur_irq_prio = -1;
m_last_op = 0;
m_last_bit = 0;
/* these are all defined reset states */
PC = 0;

4
src/devices/cpu/mcs51/mcs51.h
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@ -122,6 +122,10 @@ protected:
uint8_t m_forced_inputs[4]; /* allow read even if configured as output */
// JB-related hacks
uint8_t m_last_op;
uint8_t m_last_bit;
int m_icount;
struct mcs51_uart