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Fixed GRCG usage in PC-9801UX, fixed a bunch of new XML dupes

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This commit is contained in:
Angelo Salese 2013-08-02 21:05:30 +00:00
parent cb0fd51fad
commit 4275f55921
2 changed files with 39 additions and 3 deletions
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15
hash/pc98.xml
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@ -333,7 +333,7 @@ TODO:
<!-- in d88 format, perhaps same thing as the one above --> <!-- in d88 format, perhaps same thing as the one above -->
<software name="4drivinga" cloneof="4driving"> <software name="4drivinga" cloneof="4driving">
<description>4D Driving</description> <description>4D Driving (Alt)</description>
<year>19??</year> <year>19??</year>
<publisher>&lt;unknown&gt;</publisher> <publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25"> <part name="flop1" interface="floppy_5_25">
@ -11163,6 +11163,17 @@ other two disks
</part> </part>
</software> </software>
<software name="quarth">
<description>Quarth</description>
<year>19??</year>
<publisher>Konami</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="0x138fb0">
<rom name="quarth.d88" size="0x138fb0" crc="38fbd971" sha1="76b1e8146a45622e20a17efa1ae5d4ebd43595f5" offset="0" />
</dataarea>
</part>
</software>
<software name="queensl"> <software name="queensl">
<description>Queens Library</description> <description>Queens Library</description>
<year>19??</year> <year>19??</year>
@ -11771,7 +11782,7 @@ other two disks
<publisher>Nihon Falcom</publisher> <publisher>Nihon Falcom</publisher>
<part name="flop1" interface="floppy_5_25"> <part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664"> <dataarea name="flop" size="1265664">
<rom name="xanadu_a.fdi" size="1265664" crc="4ae868e6" sha1="cb685bf97623c1839e10fe1c9d7ec01f095bb482" offset="0" /> <rom name="xanadue_a.fdi" size="1265664" crc="4ae868e6" sha1="cb685bf97623c1839e10fe1c9d7ec01f095bb482" offset="0" />
</dataarea> </dataarea>
</part> </part>
<part name="flop2" interface="floppy_5_25"> <part name="flop2" interface="floppy_5_25">

27
src/mess/drivers/pc9801.c
View File

@ -496,6 +496,10 @@ public:
inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank); inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank);
inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data); inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data);
DECLARE_CUSTOM_INPUT_MEMBER(system_type_r); DECLARE_CUSTOM_INPUT_MEMBER(system_type_r);
DECLARE_READ8_MEMBER(pc9801ux_gvram_r);
DECLARE_WRITE8_MEMBER(pc9801ux_gvram_w);
DECLARE_READ8_MEMBER(pc9801ux_gvram0_r);
DECLARE_WRITE8_MEMBER(pc9801ux_gvram0_w);
UINT32 pc9801_286_a20(bool state); UINT32 pc9801_286_a20(bool state);
DECLARE_WRITE8_MEMBER(sasi_data_w); DECLARE_WRITE8_MEMBER(sasi_data_w);
@ -2276,11 +2280,32 @@ WRITE8_MEMBER(pc9801_state::pic_w)
((offset >= 4) ? m_pic2 : m_pic1)->write(space, offset & 3, data); ((offset >= 4) ? m_pic2 : m_pic1)->write(space, offset & 3, data);
} }
READ8_MEMBER(pc9801_state::pc9801ux_gvram_r)
{
return m_pc9801rs_grcg_r(offset & 0x7fff,(offset>>15)+1);
}
WRITE8_MEMBER(pc9801_state::pc9801ux_gvram_w)
{
m_pc9801rs_grcg_w(offset & 0x7fff,(offset>>15)+1,data);
}
READ8_MEMBER(pc9801_state::pc9801ux_gvram0_r)
{
return m_pc9801rs_grcg_r(offset & 0x7fff,0);
}
WRITE8_MEMBER(pc9801_state::pc9801ux_gvram0_w)
{
m_pc9801rs_grcg_w(offset & 0x7fff,0,data);
}
static ADDRESS_MAP_START( pc9801ux_map, AS_PROGRAM, 16, pc9801_state ) static ADDRESS_MAP_START( pc9801ux_map, AS_PROGRAM, 16, pc9801_state )
AM_RANGE(0x000000, 0x09ffff) AM_RAMBANK("wram") AM_RANGE(0x000000, 0x09ffff) AM_RAMBANK("wram")
AM_RANGE(0x0a0000, 0x0a3fff) AM_READWRITE8(pc9801_tvram_r, pc9801_tvram_w, 0xffff) AM_RANGE(0x0a0000, 0x0a3fff) AM_READWRITE8(pc9801_tvram_r, pc9801_tvram_w, 0xffff)
AM_RANGE(0x0a4000, 0x0a4fff) AM_READWRITE8(pc9801rs_knjram_r, pc9801rs_knjram_w, 0xffff) AM_RANGE(0x0a4000, 0x0a4fff) AM_READWRITE8(pc9801rs_knjram_r, pc9801rs_knjram_w, 0xffff)
AM_RANGE(0x0a8000, 0x0b0fff) AM_READWRITE8(pc9801_gvram_r, pc9801_gvram_w, 0xffff) AM_RANGE(0x0a8000, 0x0bffff) AM_READWRITE8(pc9801ux_gvram_r, pc9801ux_gvram_w, 0xffff)
AM_RANGE(0x0e0000, 0x0e7fff) AM_READWRITE8(pc9801ux_gvram0_r,pc9801ux_gvram0_w, 0xffff)
AM_RANGE(0x0e0000, 0x0fffff) AM_READ8(pc9801rs_ipl_r, 0xffff) AM_RANGE(0x0e0000, 0x0fffff) AM_READ8(pc9801rs_ipl_r, 0xffff)
ADDRESS_MAP_END ADDRESS_MAP_END