diff --git a/src/mame/drivers/namcos21.cpp b/src/mame/drivers/namcos21.cpp index 88dd54f7697..b4ef97fafa3 100644 --- a/src/mame/drivers/namcos21.cpp +++ b/src/mame/drivers/namcos21.cpp @@ -1497,19 +1497,19 @@ static ADDRESS_MAP_START( winrun_slave_map, AS_PROGRAM, 16, namcos21_state ) AM_RANGE(0xb80000, 0xb8000f) AM_READWRITE(NAMCO_C139_SCI_register_r,NAMCO_C139_SCI_register_w) ADDRESS_MAP_END + static ADDRESS_MAP_START( winrun_gpu_map, AS_PROGRAM, 16, namcos21_state ) AM_RANGE(0x000000, 0x07ffff) AM_ROM AM_RANGE(0x100000, 0x100001) AM_READWRITE(winrun_gpu_color_r,winrun_gpu_color_w) /* ? */ AM_RANGE(0x180000, 0x19ffff) AM_RAM /* work RAM */ AM_RANGE(0x1c0000, 0x1fffff) AM_DEVICE("gpu_intc", namco_c148_device, map) - AM_RANGE(0x1c0000, 0x1fffff) AM_DEVICE("gpu_intc", namco_c148_device, map) AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_SHARE("gpu_comram") AM_RANGE(0x400000, 0x40ffff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette") AM_RANGE(0x410000, 0x41ffff) AM_RAM_DEVWRITE("palette", palette_device, write_ext) AM_SHARE("palette_ext") AM_RANGE(0x600000, 0x6fffff) AM_ROM AM_REGION("gdata", 0) AM_RANGE(0xc00000, 0xcfffff) AM_READWRITE(winrun_gpu_videoram_r,winrun_gpu_videoram_w) AM_RANGE(0xd00000, 0xd0000f) AM_READWRITE(winrun_gpu_register_r,winrun_gpu_register_w) -// AM_RANGE(0xe0000c, 0xe0000d) POSIRQ + AM_RANGE(0xe0000c, 0xe0000d) AM_DEVREADWRITE8("gpu_intc", namco_c148_device, ext_posirq_line_r,ext_posirq_line_w,0x00ff) ADDRESS_MAP_END @@ -1979,10 +1979,14 @@ MACHINE_CONFIG_END TIMER_DEVICE_CALLBACK_MEMBER(namcos21_state::winrun_gpu_scanline) { int scanline = param; - - if(scanline == 240*2) + + if(scanline == 240*2) m_gpu_intc->vblank_irq_trigger(); + if(scanline == m_gpu_intc->get_posirq_line()*2) + { + m_gpu_intc->pos_irq_trigger(); + } } static MACHINE_CONFIG_START( winrun, namcos21_state ) diff --git a/src/mame/includes/namcos21.h b/src/mame/includes/namcos21.h index aff6bd6902a..f9d73989f9f 100644 --- a/src/mame/includes/namcos21.h +++ b/src/mame/includes/namcos21.h @@ -162,8 +162,9 @@ public: DECLARE_WRITE16_MEMBER(winrun_gpu_register_w); DECLARE_WRITE16_MEMBER(winrun_gpu_videoram_w); DECLARE_READ16_MEMBER(winrun_gpu_videoram_r); + TIMER_DEVICE_CALLBACK_MEMBER(winrun_gpu_scanline); - + uint8_t m_gearbox_state; DECLARE_CUSTOM_INPUT_MEMBER(driveyes_gearbox_r); DECLARE_DRIVER_INIT(driveyes); diff --git a/src/mame/machine/namco_c148.cpp b/src/mame/machine/namco_c148.cpp index 3910bca83da..c3aedab61cc 100644 --- a/src/mame/machine/namco_c148.cpp +++ b/src/mame/machine/namco_c148.cpp @@ -64,15 +64,15 @@ namco_c148_device::namco_c148_device(const machine_config &mconfig, const char * DEVICE_ADDRESS_MAP_START( map, 16, namco_c148_device ) // AM_RANGE(0x06000, 0x07fff) // CPUIRQ lv // AM_RANGE(0x08000, 0x09fff) // EXIRQ lv -// AM_RANGE(0x0a000, 0x0bfff) // POSIRQ lv + AM_RANGE(0x0a000, 0x0bfff) AM_READWRITE8(pos_irq_level_r,pos_irq_level_w,0x00ff) // POSIRQ lv // AM_RANGE(0x0c000, 0x0dfff) // SCIRQ lv AM_RANGE(0x0e000, 0x0ffff) AM_READWRITE8(vblank_irq_level_r,vblank_irq_level_w,0x00ff) // VBlank IRQ lv // AM_RANGE(0x16000, 0x17fff) // CPUIRQ ack // AM_RANGE(0x18000, 0x19fff) // EXIRQ ack -// AM_RANGE(0x1a000, 0x1bfff) // POSIRQ ack + AM_RANGE(0x1a000, 0x1bfff) AM_READWRITE(pos_irq_ack_r, pos_irq_ack_w) // POSIRQ ack // AM_RANGE(0x1c000, 0x1dfff) // SCIRQ ack - AM_RANGE(0x1e000, 0x1ffff) AM_READWRITE8(vblank_irq_ack_r, vblank_irq_ack_w, 0x00ff) // VBlank IRQ ack + AM_RANGE(0x1e000, 0x1ffff) AM_READWRITE(vblank_irq_ack_r, vblank_irq_ack_w) // VBlank IRQ ack // AM_RANGE(0x20000, 0x21fff) // EEPROM ready status (*) AM_RANGE(0x22000, 0x23fff) AM_WRITE8(ext2_w,0x00ff) // sound CPU reset (*) // AM_RANGE(0x24000, 0x25fff) // slave & i/o reset (*) @@ -98,12 +98,24 @@ void namco_c148_device::device_start() void namco_c148_device::device_reset() { m_irqlevel.vblank = 0; + m_irqlevel.pos = 0; } //************************************************************************** // READ/WRITE HANDLERS //************************************************************************** +READ8_MEMBER( namco_c148_device::pos_irq_level_r ) +{ + return m_irqlevel.pos & 0x7; +} + +WRITE8_MEMBER( namco_c148_device::pos_irq_level_w ) +{ + m_irqlevel.pos = data & 7; + flush_irq_acks(); +} + READ8_MEMBER( namco_c148_device::vblank_irq_level_r ) { return m_irqlevel.vblank & 0x7; @@ -112,28 +124,71 @@ READ8_MEMBER( namco_c148_device::vblank_irq_level_r ) WRITE8_MEMBER( namco_c148_device::vblank_irq_level_w ) { m_irqlevel.vblank = data & 7; + flush_irq_acks(); } -READ8_MEMBER( namco_c148_device::vblank_irq_ack_r ) +READ16_MEMBER( namco_c148_device::vblank_irq_ack_r ) { m_hostcpu->set_input_line(m_irqlevel.vblank, CLEAR_LINE); return 0; } -WRITE8_MEMBER( namco_c148_device::vblank_irq_ack_w ) +WRITE16_MEMBER( namco_c148_device::vblank_irq_ack_w ) { m_hostcpu->set_input_line(m_irqlevel.vblank, CLEAR_LINE); } +WRITE16_MEMBER( namco_c148_device::pos_irq_ack_w ) +{ + m_hostcpu->set_input_line(m_irqlevel.pos, CLEAR_LINE); +} + +READ16_MEMBER( namco_c148_device::pos_irq_ack_r ) +{ + m_hostcpu->set_input_line(m_irqlevel.pos, CLEAR_LINE); + return 0; +} + + + WRITE8_MEMBER( namco_c148_device::ext2_w ) { - // TODO: sync flag for GPU in winrun? - if(data & 2) - m_hostcpu->set_input_line(m_irqlevel.vblank, CLEAR_LINE); + // TODO: bit 1 might be irq enable? } +READ8_MEMBER( namco_c148_device::ext_posirq_line_r ) +{ + return m_posirq_line; +} + +WRITE8_MEMBER( namco_c148_device::ext_posirq_line_w ) +{ + m_posirq_line = data; +} + +//************************************************************************** +// GETTERS/SETTERS +//************************************************************************** + void namco_c148_device::vblank_irq_trigger() { m_hostcpu->set_input_line(m_irqlevel.vblank, ASSERT_LINE); } +void namco_c148_device::pos_irq_trigger() +{ + m_hostcpu->set_input_line(m_irqlevel.pos, ASSERT_LINE); +} + +void namco_c148_device::flush_irq_acks() +{ + // If writing an IRQ priority register, clear any pending IRQs. + + for(int i=0;i<8;i++) + m_hostcpu->set_input_line(i, CLEAR_LINE); +} + +uint8_t namco_c148_device::get_posirq_line() +{ + return m_posirq_line; +} diff --git a/src/mame/machine/namco_c148.h b/src/mame/machine/namco_c148.h index 1671a90aff5..8c3fbccaaa2 100644 --- a/src/mame/machine/namco_c148.h +++ b/src/mame/machine/namco_c148.h @@ -44,12 +44,22 @@ public: DECLARE_READ8_MEMBER( vblank_irq_level_r ); DECLARE_WRITE8_MEMBER( vblank_irq_level_w ); - DECLARE_READ8_MEMBER( vblank_irq_ack_r ); - DECLARE_WRITE8_MEMBER( vblank_irq_ack_w ); + DECLARE_READ16_MEMBER( vblank_irq_ack_r ); + DECLARE_WRITE16_MEMBER( vblank_irq_ack_w ); + + DECLARE_READ8_MEMBER( pos_irq_level_r ); + DECLARE_WRITE8_MEMBER( pos_irq_level_w ); + DECLARE_READ16_MEMBER( pos_irq_ack_r ); + DECLARE_WRITE16_MEMBER( pos_irq_ack_w ); + + DECLARE_READ8_MEMBER( ext_posirq_line_r ); + DECLARE_WRITE8_MEMBER( ext_posirq_line_w ); + DECLARE_WRITE8_MEMBER( ext2_w ); void vblank_irq_trigger(); - //uint8_t posirq_line(); - + void pos_irq_trigger(); + uint8_t get_posirq_line(); + protected: // device-level overrides // virtual void device_validity_check(validity_checker &valid) const; @@ -60,12 +70,14 @@ private: const char *m_hostcpu_tag; /**< host cpu tag name */ bool m_hostcpu_master; /**< define if host cpu is master */ struct{ - uint8_t cpuirq; - uint8_t exirq; - uint8_t sciirq; - uint8_t posirq; + uint8_t cpu; + uint8_t ex; + uint8_t sci; + uint8_t pos; uint8_t vblank; }m_irqlevel; + uint8_t m_posirq_line; + void flush_irq_acks(); };