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r65c19: Add banking for C39 subfamily (nw)
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AJR
parent
ce060a337e
commit
42a69e5c6a
@ -14,11 +14,14 @@
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#include "r65c19d.h"
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DEFINE_DEVICE_TYPE(R65C19, r65c19_device, "r65c19", "Rockwell R65C19 MCU")
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DEFINE_DEVICE_TYPE(L2800, l2800_device, "l2800", "Rockwell L2800 MCU")
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r65c19_device::r65c19_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor internal_map)
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: r65c02_device(mconfig, type, tag, owner, clock)
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, m_w(0)
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, m_i(0)
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, m_page1_ram(*this, "page1")
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, m_cir(0)
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{
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program_config.m_internal_map = std::move(internal_map);
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}
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@ -28,6 +31,18 @@ r65c19_device::r65c19_device(const machine_config &mconfig, const char *tag, dev
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{
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}
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c39_device::c39_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor internal_map)
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: r65c19_device(mconfig, type, tag, owner, clock, internal_map)
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, m_exp_config("expansion", ENDIANNESS_LITTLE, 8, 21, 0)
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, m_es4_config("ES4", ENDIANNESS_LITTLE, 8, 9, 0)
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{
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}
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l2800_device::l2800_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: c39_device(mconfig, L2800, tag, owner, clock, address_map_constructor(FUNC(l2800_device::internal_map), this))
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{
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}
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std::unique_ptr<util::disasm_interface> r65c19_device::create_disassembler()
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{
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return std::make_unique<r65c19_disassembler>();
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@ -81,6 +96,29 @@ void r65c19_device::device_start()
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c19_init();
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}
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device_memory_interface::space_config_vector c39_device::memory_space_config() const
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{
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return space_config_vector {
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std::make_pair(AS_PROGRAM, &program_config),
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std::make_pair(AS_DATA, &m_exp_config),
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std::make_pair(AS_IO, &m_es4_config)
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};
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}
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void c39_device::device_start()
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{
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std::unique_ptr<mi_banked> intf = std::make_unique<mi_banked>();
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intf->exp = &space(AS_DATA);
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intf->escache = space(AS_DATA).cache<0, 0, ENDIANNESS_LITTLE>();
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intf->es4 = &space(AS_IO);
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save_item(NAME(intf->bsr));
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save_item(NAME(intf->pbs));
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mintf = std::move(intf);
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c19_init();
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}
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void r65c19_device::c19_init()
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{
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init();
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@ -96,11 +134,157 @@ void r65c19_device::c19_init()
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save_item(NAME(m_w));
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save_item(NAME(m_i));
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save_item(NAME(m_cir));
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}
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void r65c19_device::device_reset()
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{
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r65c02_device::device_reset();
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m_cir = 0x00;
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}
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void c39_device::device_reset()
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{
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r65c02_device::device_reset();
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mi_banked &intf = downcast<mi_banked &>(*mintf);
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intf.bsr[0] = 0xe0;
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intf.bsr[1] = 0xd1;
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intf.bsr[2] = 0xb2;
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intf.bsr[3] = 0xb3;
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intf.bsr[4] = 0x74;
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intf.bsr[5] = 0x75;
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intf.bsr[6] = 0x76;
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intf.bsr[7] = 0x77;
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intf.pbs = 0xff;
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}
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u8 r65c19_device::page1_seg_r(offs_t offset)
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{
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return m_page1_ram[(m_cir & 0x03) << 6 | offset];
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}
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void r65c19_device::page1_seg_w(offs_t offset, u8 data)
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{
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m_page1_ram[(m_cir & 0x03) << 6 | offset] = data;
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}
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u8 r65c19_device::cir_r()
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{
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return m_cir;
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}
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void r65c19_device::cir_w(u8 data)
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{
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// TODO: clear interrupts
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m_cir = data & 0x07;
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}
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u8 c39_device::mi_banked::exp_read(u16 adr)
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{
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return exp->read_byte(u32(bsr[(adr & 0xe000) >> 13]) << 13 | (adr & 0x1fff));
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}
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u8 c39_device::mi_banked::exp_read_cached(u16 adr)
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{
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return escache->read_byte(u32(bsr[(adr & 0xe000) >> 13]) << 13 | (adr & 0x1fff));
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}
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void c39_device::mi_banked::exp_write(u16 adr, u8 val)
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{
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exp->write_byte(u32(bsr[(adr & 0xe000) >> 13]) << 13 | (adr & 0x1fff), val);
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}
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u8 c39_device::mi_banked::es4_read(u16 adr)
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{
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return es4->read_byte(adr & 0x1ff);
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}
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void c39_device::mi_banked::es4_write(u16 adr, u8 val)
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{
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es4->write_byte(adr & 0x1ff, val);
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}
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u8 c39_device::mi_banked::read(u16 adr)
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{
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return program->read_byte(adr);
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}
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u8 c39_device::mi_banked::read_sync(u16 adr)
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{
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if (adr < 0x0600)
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return cache->read_byte(adr);
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else if (adr >= 0x0800 || BIT(pbs, 1))
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return exp_read_cached(adr);
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else
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return es4_read(adr);
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}
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u8 c39_device::mi_banked::read_arg(u16 adr)
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{
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if (adr < 0x0600)
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return cache->read_byte(adr);
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else if (adr >= 0x0800 || BIT(pbs, 1))
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return exp_read_cached(adr);
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else
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return es4_read(adr);
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}
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void c39_device::mi_banked::write(u16 adr, u8 val)
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{
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program->write_byte(adr, val);
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}
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u8 c39_device::pbs_r()
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{
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return downcast<mi_banked &>(*mintf).pbs;
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}
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void c39_device::pbs_w(u8 data)
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{
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downcast<mi_banked &>(*mintf).pbs = data;
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}
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u8 c39_device::bsr_r(offs_t offset)
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{
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return downcast<mi_banked &>(*mintf).bsr[offset];
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}
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void c39_device::bsr_w(offs_t offset, u8 data)
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{
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downcast<mi_banked &>(*mintf).bsr[offset] = data;
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}
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u8 c39_device::expansion_r(offs_t offset)
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{
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mi_banked &intf = downcast<mi_banked &>(*mintf);
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if (offset >= 0x0200 || BIT(intf.pbs, 1))
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return intf.exp_read(offset + 0x0600);
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else
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return intf.es4_read(offset + 0x0600);
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}
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void c39_device::expansion_w(offs_t offset, u8 data)
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{
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mi_banked &intf = downcast<mi_banked &>(*mintf);
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if (offset >= 0x0200 || BIT(intf.pbs, 1))
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intf.exp_write(offset + 0x0600, data);
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else
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intf.es4_write(offset + 0x0600, data);
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}
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void c39_device::internal_map(address_map &map)
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{
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// TODO: most registers still unimplemented
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map(0x0005, 0x0005).rw(FUNC(c39_device::pbs_r), FUNC(c39_device::pbs_w));
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map(0x000b, 0x000b).rw(FUNC(c39_device::cir_r), FUNC(c39_device::cir_w));
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map(0x0018, 0x001f).rw(FUNC(c39_device::bsr_r), FUNC(c39_device::bsr_w));
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map(0x0040, 0x007f).rw(FUNC(c39_device::page1_seg_r), FUNC(c39_device::page1_seg_w));
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map(0x0080, 0x00ff).ram();
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map(0x0100, 0x01ff).ram().share("page1");
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map(0x0200, 0x047f).ram();
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map(0x0600, 0xffff).rw(FUNC(c39_device::expansion_r), FUNC(c39_device::expansion_w));
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}
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#include "cpu/m6502/r65c19.hxx"
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@ -34,6 +34,11 @@ protected:
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void c19_init();
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u8 cir_r();
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void cir_w(u8 data);
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u8 page1_seg_r(offs_t offset);
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void page1_seg_w(offs_t offset, u8 data);
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private:
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void do_add(u8 v);
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u16 do_accumulate(u16 v, u16 w);
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@ -83,8 +88,63 @@ private:
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u16 m_w;
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u16 m_i;
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optional_shared_ptr<u8> m_page1_ram;
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u8 m_cir;
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};
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class c39_device : public r65c19_device
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{
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protected:
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c39_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor internal_map);
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virtual space_config_vector memory_space_config() const override;
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virtual void device_start() override;
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virtual void device_reset() override;
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u8 pbs_r();
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void pbs_w(u8 data);
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u8 bsr_r(offs_t offset);
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void bsr_w(offs_t offset, u8 data);
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u8 expansion_r(offs_t offset);
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void expansion_w(offs_t offset, u8 data);
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void internal_map(address_map &map);
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private:
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class mi_banked : public memory_interface {
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public:
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virtual u8 read(u16 adr) override;
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virtual u8 read_sync(u16 adr) override;
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virtual u8 read_arg(u16 adr) override;
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virtual void write(u16 adr, u8 val) override;
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u8 exp_read(u16 adr);
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u8 exp_read_cached(u16 adr);
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void exp_write(u16 adr, u8 val);
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u8 es4_read(u16 adr);
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void es4_write(u16 adr, u8 val);
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address_space *exp;
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memory_access_cache<0, 0, ENDIANNESS_LITTLE> *escache;
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address_space *es4;
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u8 bsr[8];
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u8 pbs;
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};
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address_space_config m_exp_config;
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address_space_config m_es4_config;
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};
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class l2800_device : public c39_device
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{
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public:
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l2800_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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DECLARE_DEVICE_TYPE(R65C19, r65c19_device)
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DECLARE_DEVICE_TYPE(L2800, l2800_device)
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#endif // MAME_CPU_M6502_R65C19_H
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@ -22,17 +22,16 @@ public:
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void vd56sp(machine_config &mconfig);
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private:
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void mem_map(address_map &map);
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void exp_map(address_map &map);
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required_device<r65c19_device> m_maincpu;
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};
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void vd56sp_state::mem_map(address_map &map)
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void vd56sp_state::exp_map(address_map &map)
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{
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map(0x0040, 0x03ff).ram();
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map(0x0800, 0x1fff).rom().region("firmware", 0x20800);
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map(0x8000, 0xffff).rom().region("firmware", 0x28000);
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map(0x0e0000, 0x0fffff).rom().region("firmware", 0x20000);
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map(0x1f8000, 0x1fffff).ram();
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}
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@ -41,8 +40,8 @@ INPUT_PORTS_END
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void vd56sp_state::vd56sp(machine_config &config)
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{
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R65C19(config, m_maincpu, 8'000'000); // FIXME: actually L2800-38 (XTAL not readable)
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m_maincpu->set_addrmap(AS_PROGRAM, &vd56sp_state::mem_map);
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L2800(config, m_maincpu, 8'000'000); // L28L2800-38 (XTAL not readable)
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m_maincpu->set_addrmap(AS_DATA, &vd56sp_state::exp_map);
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// Modem IC: Conexant R6764-61
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}
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