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m37710: Fix UART control register 1 writes and raveracw regression (nw)

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This commit is contained in:
AJR 2019-07-10 19:19:48 -04:00
parent 5eaac5e857
commit 42b3be5935
1 changed files with 3 additions and 3 deletions
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6
src/devices/cpu/m37710/m37710.cpp
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@ -631,7 +631,7 @@ uint8_t m37710_cpu_device::uart1_ctrl_reg0_r()
LOGMASKED(LOG_UART, "uart1_ctrl_reg0_r: UART1 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[1], REG_PB<<16 | REG_PC);
//return m_uart_ctrl_reg0[1];
return 0xff; // not hooked up yet
return 0x08; // not hooked up yet
}
void m37710_cpu_device::uart1_ctrl_reg0_w(uint8_t data)
@ -652,7 +652,7 @@ void m37710_cpu_device::uart0_ctrl_reg1_w(uint8_t data)
{
LOGMASKED(LOG_UART, "uart0_ctrl_reg0_w %x: UART0 transmit/recv ctrl 1 = %x\n", data, m_uart_ctrl_reg1[0]);
m_uart_ctrl_reg1[0] = data;
m_uart_ctrl_reg1[0] = (m_uart_ctrl_reg1[0] & (BIT(data, 2) ? 0xfa : 0x0a)) | (data & 0x05);
}
uint8_t m37710_cpu_device::uart1_ctrl_reg1_r()
@ -666,7 +666,7 @@ void m37710_cpu_device::uart1_ctrl_reg1_w(uint8_t data)
{
LOGMASKED(LOG_UART, "uart1_ctrl_reg1_w %x: UART1 transmit/recv ctrl 1 = %x\n", data, m_uart_ctrl_reg1[1]);
m_uart_ctrl_reg1[1] = data;
m_uart_ctrl_reg1[1] = (m_uart_ctrl_reg1[1] & (BIT(data, 2) ? 0xfa : 0x0a)) | (data & 0x05);
}
uint16_t m37710_cpu_device::uart0_rbuf_r()