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netlist: New devices and some fixes. [Couriersud]

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- add CD4006 and CD4070 devices
- add TL084 opamp model
- Clock now supports proxies, i.e. can be connected to
  analog devices.
- Fixed netlists using CLOCK
- added some comments
- removed a forgotten header file.
This commit is contained in:
couriersud 2020-01-25 15:26:10 +01:00
parent 2e570a9a6e
commit 42d351a4eb
17 changed files with 251 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
scripts/src/netlist.lua
View File

@ -120,6 +120,8 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_2716.h",
MAME_DIR .. "src/lib/netlist/devices/nld_tms4800.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_tms4800.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4006.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4006.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4020.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4020.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.cpp",
@ -218,7 +220,6 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_system.h",
MAME_DIR .. "src/lib/netlist/devices/nlid_truthtable.cpp",
MAME_DIR .. "src/lib/netlist/devices/nlid_truthtable.h",
MAME_DIR .. "src/lib/netlist/devices/nlid_cmos.h",
MAME_DIR .. "src/lib/netlist/devices/nlid_system.h",
MAME_DIR .. "src/lib/netlist/devices/nlid_proxy.cpp",
MAME_DIR .. "src/lib/netlist/devices/nlid_proxy.h",

3
src/lib/netlist/analog/nlid_twoterm.h
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@ -283,6 +283,7 @@ namespace analog
protected:
//NETLIB_UPDATEI();
//FIXME: should be able to change
NETLIB_UPDATE_PARAMI() { }
private:
@ -484,13 +485,13 @@ namespace analog
NETLIB_UPDATE_PARAMI()
{
//FIXME: works only for CS without function
solve_now();
const auto zero(nlconst::zero());
set_mat(zero, zero, -m_I(),
zero, zero, m_I());
}
private:
state_var<nl_fptype> m_t;
param_fp_t m_I;

2
src/lib/netlist/devices/net_lib.cpp
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@ -133,6 +133,8 @@ namespace devices
LIB_ENTRY(9334)
LIB_ENTRY(AM2847)
// FIXME: duplicate?
LIB_ENTRY(CD4006)
LIB_ENTRY(CD4006_dip)
LIB_ENTRY(CD4020_WI)
LIB_ENTRY(CD4020)
LIB_ENTRY(CD4066_GATE)

1
src/lib/netlist/devices/net_lib.h
View File

@ -50,6 +50,7 @@
#include "nld_2102A.h"
#include "nld_2716.h"
#include "nld_4006.h"
#include "nld_4020.h"
#include "nld_4066.h"
#include "nld_74107.h"

100
src/lib/netlist/devices/nld_4006.cpp Normal file
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@ -0,0 +1,100 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_4006.c
*
*/
#include "nld_4006.h"
#include "nlid_system.h"
namespace netlist
{
namespace devices
{
NETLIB_OBJECT(CD4006)
{
NETLIB_CONSTRUCTOR(CD4006)
NETLIB_FAMILY("CD4XXX")
, m_CLOCK(*this, "CLOCK")
, m_I(*this, {{"D1", "D2", "D3", "D4"}})
, m_Q(*this, {{"D1P4", "D1P4S", "D2P4", "D2P5", "D3P4", "D4P4", "D3P5"}})
, m_d(*this, "m_d", 0)
, m_last_clock(*this, "m_last_clock", 0)
, m_supply(*this, "VDD", "VSS")
{
}
NETLIB_RESETI()
{
}
NETLIB_UPDATEI()
{
if (m_last_clock && !m_CLOCK())
{
m_d[0] >>= 1;
m_d[1] >>= 1;
m_d[2] >>= 1;
m_d[3] >>= 1;
// falling, output all but D1P4S
m_Q[0].push(m_d[0] & 1, netlist_time::from_nsec(200));
m_Q[2].push((m_d[1] >> 1) & 1, netlist_time::from_nsec(200)); // D2 + 4
m_Q[3].push( m_d[1] & 1, netlist_time::from_nsec(200)); // D2 + 5
m_Q[4].push( m_d[2] & 1, netlist_time::from_nsec(200)); // D3 + 4
m_Q[5].push((m_d[3] >> 1) & 1, netlist_time::from_nsec(200)); // D4 + 4
m_Q[6].push( m_d[3] & 1, netlist_time::from_nsec(200)); // D5 + 5
m_last_clock = m_CLOCK();
}
else if (!m_last_clock && m_CLOCK())
{
// rising, output D1P4S
m_Q[1].push(m_d[0] & 1, netlist_time::from_nsec(200));
m_last_clock = m_CLOCK();
}
else
{
m_d[0] = (m_d[0] & 0x0f) | (m_I[0]() << 4);
m_d[1] = (m_d[1] & 0x1f) | (m_I[1]() << 5);
m_d[2] = (m_d[2] & 0x0f) | (m_I[2]() << 4);
m_d[3] = (m_d[3] & 0x1f) | (m_I[3]() << 5);
}
}
protected:
logic_input_t m_CLOCK;
object_array_t<logic_input_t, 4> m_I;
object_array_t<logic_output_t, 7> m_Q;
state_container<std::array<uint8_t, 4>> m_d;
state_var<netlist_sig_t> m_last_clock;
nld_power_pins m_supply;
};
NETLIB_OBJECT_DERIVED(CD4006_dip, CD4006)
{
NETLIB_CONSTRUCTOR_DERIVED(CD4006_dip, CD4006)
{
register_subalias("1", m_I[0]);
register_subalias("2", m_Q[1]);
register_subalias("3", m_CLOCK);
register_subalias("4", m_I[1]);
register_subalias("5", m_I[2]);
register_subalias("6", m_I[3]);
register_subalias("7", "VSS");
register_subalias("8", m_Q[5]);
register_subalias("9", m_Q[6]);
register_subalias("10", m_Q[4]);
register_subalias("11", m_Q[2]);
register_subalias("12", m_Q[3]);
register_subalias("13", m_Q[0]);
register_subalias("14", "VDD");
}
};
NETLIB_DEVICE_IMPL(CD4006, "CD4006", "+CLOCK,+D1,+D2,+D3,+D4,+D1P4,+D1P4S,+D2P4,+D2P5,+D3P4,+D4P4,+D3P5,@VCC,@GND")
NETLIB_DEVICE_IMPL(CD4006_dip, "CD4006_DIP", "")
} //namespace devices
} // namespace netlist

50
src/lib/netlist/devices/nld_4006.h Normal file
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@ -0,0 +1,50 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_4006.h
*
* CD4006: CMOS 18-Stage Static Register
*
* Description
*
* CD4006BMS types are composed of 4 separate shift register sections: two
* sections of four stages and two sections of five stages with an output tap
* at the fourth stage. Each section has an independent single-rail data path.
*
* A common clock signal is used for all stages. Data are shifted to the next
* stages on negative-going transitions of the clock. Through appropriate
* connections of inputs and outputs, multiple register sections of 4, 5, 8,
* and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18
* stages can be implemented using one CD4006BMS package. Longer shift register
* sections can be assembled by using more than one CD4006BMS.
*
* To facilitate cascading stages when clock rise and fall times are slow,
* an optional output (D1 + 4’) that is delayed one-half clockcycle, is
* provided.
*
* +--------------+
* D1 |1 ++ 14| VDD
* D1+4' |2 13| D1+4
* CLOCK |3 12| D2+5
* D2 |4 4006 11| D2+4
* D3 |5 10| D3+4
* D4 |6 9| D4+5
* VSS |7 8| D4+4
* +--------------+
*
*
* Naming conventions follow SYC datasheet
*
* FIXME: Timing depends on VDD-VSS
*
*/
#ifndef NLD_4006_H_
#define NLD_4006_H_
#include "netlist/nl_setup.h"
#define CD4006(name) \
NET_REGISTER_DEV(CD4006, name)
#endif /* NLD_4006_H_ */

1
src/lib/netlist/devices/nld_4020.cpp
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@ -5,7 +5,6 @@
*
*/
//#include "nlid_cmos.h"
#include "nld_4020.h"
#include "nlid_system.h"

1
src/lib/netlist/devices/nld_4066.cpp
View File

@ -62,6 +62,7 @@ namespace netlist
{
R = rON;
}
//printf("%s %f %f %g\n", name().c_str(), sup, in, R);
if (R > nlconst::zero())
{
m_R.update();

41
src/lib/netlist/devices/nlid_cmos.h
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@ -1,41 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_cmos.h
*
*/
#ifndef NLID_CMOS_H_
#define NLID_CMOS_H_
#include "netlist/nl_base.h"
#include "netlist/nl_setup.h"
namespace netlist
{
namespace devices
{
// FIXME: this needs to be removed
NETLIB_OBJECT(vdd_vss)
{
NETLIB_CONSTRUCTOR(vdd_vss)
, m_vdd(*this, "VDD")
, m_vss(*this, "VSS")
{
}
NETLIB_UPDATEI() {}
NETLIB_RESETI() {}
public:
nl_fptype vdd() { return m_vdd(); }
nl_fptype vss() { return m_vss(); }
analog_input_t m_vdd;
analog_input_t m_vss;
};
} //namespace devices
} // namespace netlist
#endif /* NLID_CMOS_H_ */

13
src/lib/netlist/devices/nlid_system.h
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@ -84,6 +84,8 @@ namespace devices
, m_feedback(*this, "FB")
, m_Q(*this, "Q")
, m_freq(*this, "FREQ", nlconst::magic(7159000.0 * 5.0))
, m_FAMILY(*this, "FAMILY", "FAMILY(TYPE=TTL)")
, m_supply(*this)
{
m_inc = netlist_time::from_fp(plib::reciprocal(m_freq()*nlconst::two()));
@ -107,7 +109,10 @@ namespace devices
param_fp_t m_freq;
netlist_time m_inc;
};
param_model_t m_FAMILY;
NETLIB_NAME(power_pins) m_supply;
};
// -----------------------------------------------------------------------------
// varclock
@ -230,7 +235,11 @@ namespace devices
NETLIB_UPDATEI() { }
NETLIB_RESETI() { m_Q.initial(0); }
NETLIB_UPDATE_PARAMI() { m_Q.push(m_IN() & 1, netlist_time::from_nsec(1)); }
NETLIB_UPDATE_PARAMI()
{
//printf("%s %d\n", name().c_str(), m_IN());
m_Q.push(m_IN() & 1, netlist_time::from_nsec(1));
}
private:
logic_output_t m_Q;

49
src/lib/netlist/macro/nlm_cd4xxx.cpp
View File

@ -152,6 +152,45 @@ static NETLIST_START(CD4016_DIP)
)
NETLIST_END()
/*
* DM7486: Quad 2-Input Exclusive-OR Gates
*
* Y = A+B
* +---+---++---+
* | A | B || Y |
* +===+===++===+
* | 0 | 0 || 0 |
* | 0 | 1 || 1 |
* | 1 | 0 || 1 |
* | 1 | 1 || 0 |
* +---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
static NETLIST_START(CD4070_DIP)
CD4070_GATE(A)
CD4070_GATE(B)
CD4070_GATE(C)
CD4070_GATE(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
A.B, /* B1 |2 13| B4 */ D.B,
A.Q, /* Y1 |3 12| A4 */ D.A,
B.Q, /* Y2 |4 7486 11| Y4 */ D.Q,
B.A, /* A2 |5 10| Y3 */ C.Q,
B.B, /* B2 |6 9| B3 */ C.B,
A.GND,/* GND |7 8| A3 */ C.A
/* +--------------+ */
)
NETLIST_END()
static NETLIST_START(CD4316_DIP)
CD4316_GATE(A)
CD4316_GATE(B)
@ -191,7 +230,17 @@ NETLIST_START(CD4XXX_lib)
TT_FAMILY("CD4XXX")
TRUTHTABLE_END()
TRUTHTABLE_START(CD4070_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|0|15")
TT_LINE("0,1|1|22")
TT_LINE("1,0|1|22")
TT_LINE("1,1|0|15")
TT_FAMILY("CD4XXX")
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(CD4001_DIP)
LOCAL_LIB_ENTRY(CD4070_DIP)
/* DIP ONLY */
LOCAL_LIB_ENTRY(CD4020_DIP)

6
src/lib/netlist/macro/nlm_cd4xxx.h
View File

@ -33,6 +33,12 @@
#define CD4001_DIP(name) \
NET_REGISTER_DEV(CD4001_DIP, name)
#define CD4070_GATE(name) \
NET_REGISTER_DEV(CD4070_GATE, name)
#define CD4070_DIP(name) \
NET_REGISTER_DEV(CD4070_DIP, name)
/* ----------------------------------------------------------------------------
* DIP only macros
* ---------------------------------------------------------------------------*/

16
src/lib/netlist/macro/nlm_opamp.cpp
View File

@ -134,6 +134,16 @@ static NETLIST_START(MB3614_DIP)
NETLIST_END()
static NETLIST_START(TL084_DIP)
OPAMP(A, "TL084")
OPAMP(B, "TL084")
OPAMP(C, "TL084")
OPAMP(D, "TL084")
INCLUDE(opamp_layout_4_4_11)
NETLIST_END()
static NETLIST_START(LM324_DIP)
OPAMP(A, "LM324")
OPAMP(B, "LM324")
@ -343,6 +353,11 @@ NETLIST_START(OPAMP_lib)
LOCAL_LIB_ENTRY(opamp_layout_1_8_5)
LOCAL_LIB_ENTRY(opamp_layout_1_11_6)
// FIXME: JFET Opamp may need better model
// VLL and VHH for +-6V RI=10^12 (for numerical stability 10^9 is used below
// RO from data sheet
NET_MODEL("TL084 OPAMP(TYPE=3 VLH=0.75 VLL=0.75 FPF=10 UGF=3000k SLEW=13M RI=1000M RO=192 DAB=0.0014)")
NET_MODEL("LM324 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.00075)")
NET_MODEL("LM358 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.001)")
NET_MODEL("MB3614 OPAMP(TYPE=3 VLH=1.4 VLL=0.02 FPF=10 UGF=1000k SLEW=0.6M RI=1000k RO=50 DAB=0.002)")
@ -357,6 +372,7 @@ NETLIST_START(OPAMP_lib)
NET_MODEL("LM3900_PNP1 PNP(IS=1E-14 BF=40 TF=1E-7 CJC=1E-12 CJE=1E-12 VAF=150 RB=100 RE=5)")
#endif
LOCAL_LIB_ENTRY(MB3614_DIP)
LOCAL_LIB_ENTRY(TL084_DIP)
LOCAL_LIB_ENTRY(LM324_DIP)
LOCAL_LIB_ENTRY(LM358_DIP)
LOCAL_LIB_ENTRY(LM2902_DIP)

3
src/lib/netlist/macro/nlm_opamp.h
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@ -24,6 +24,9 @@
#define LM324_DIP(name) \
NET_REGISTER_DEV(LM324_DIP, name)
#define TL084_DIP(name) \
NET_REGISTER_DEV(TL084_DIP, name)
#define LM2902_DIP(name) \
NET_REGISTER_DEV(LM2902_DIP, name)

3
src/lib/netlist/nl_config.h
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@ -17,8 +17,7 @@
///
/// \brief Version - Minor.
///
#define NL_VERSION_MINOR 8
///
#define NL_VERSION_MINOR 9
/// \brief Version - Patch level.
///
#define NL_VERSION_PATCHLEVEL 0

5
src/mame/machine/nl_palestra.cpp
View File

@ -709,5 +709,10 @@ NETLIST_START(palestra)
HINT(clk, NO_DEACTIVATE)
#endif
// Connect power terminals
NET_C(VCC, N1X1.VCC, N1X2.VCC, N1X3.VCC, N1X4.VCC, N1X5.VCC, N1X6a.VCC, N1X7a.VCC, N1X8.VCC)
NET_C(GND, N1X1.GND, N1X2.GND, N1X3.GND, N1X4.GND, N1X5.GND, N1X7a.GND, N1X6a.GND, N1X8.GND)
NETLIST_END()

4
src/mame/machine/nl_stuntcyc.cpp
View File

@ -665,8 +665,8 @@ NETLIST_START(stuntcyc)
// Power terminals
NET_C(VCC, high.VCC, low.VCC, ANTENNA.VCC, FREESCORE_SW_B0.VCC, FREESCORE_SW_B1.VCC, FREESCORE_SW_B2.VCC, FREESCORE_SW_B3.VCC,
MISS_SW_B0.VCC, MISS_SW_B1.VCC, MISS_SW_B2.VCC, R38_2.VCC, R39_2.VCC)
MISS_SW_B0.VCC, MISS_SW_B1.VCC, MISS_SW_B2.VCC, R38_2.VCC, R39_2.VCC, SPEED_PULSES.VCC, PROBECLK.VCC)
NET_C(GND, high.GND, low.GND, ANTENNA.GND, FREESCORE_SW_B0.GND, FREESCORE_SW_B1.GND, FREESCORE_SW_B2.GND, FREESCORE_SW_B3.GND,
MISS_SW_B0.GND, MISS_SW_B1.GND, MISS_SW_B2.GND, R38_2.GND, R39_2.GND)
MISS_SW_B0.GND, MISS_SW_B1.GND, MISS_SW_B2.GND, R38_2.GND, R39_2.GND, SPEED_PULSES.GND, PROBECLK.GND)
#endif
NETLIST_END()