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Merge pull request #4487 from shattered/_1c5572b0c3

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netlist wip: 7474, 7497, test driver
This commit is contained in:
R. Belmont 2019-01-07 16:12:35 -05:00 committed by GitHub
commit 43110c956e
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GPG Key ID: 4AEE18F83AFDEB23
15 changed files with 776 additions and 2 deletions
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2
scripts/src/netlist.lua
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@ -140,6 +140,8 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_7490.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7493.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7493.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7497.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7497.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74107.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74107.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74123.cpp",

3
scripts/target/mame/arcade.lua
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@ -4885,5 +4885,8 @@ files {
MAME_DIR .. "src/mame/includes/xyonix.h",
MAME_DIR .. "src/mame/video/xyonix.cpp",
MAME_DIR .. "src/mame/drivers/yuvomz80.cpp",
MAME_DIR .. "src/mame/drivers/testpat.cpp",
MAME_DIR .. "src/mame/machine/nl_tp1983.cpp",
MAME_DIR .. "src/mame/machine/nl_tp1985.cpp",
}
end

1
src/lib/netlist/build/makefile
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@ -92,6 +92,7 @@ NLOBJS := \
$(NLOBJ)/devices/nld_7485.o \
$(NLOBJ)/devices/nld_7490.o \
$(NLOBJ)/devices/nld_7493.o \
$(NLOBJ)/devices/nld_7497.o \
$(NLOBJ)/devices/nld_74107.o \
$(NLOBJ)/devices/nld_74123.o \
$(NLOBJ)/devices/nld_74153.o \

2
src/lib/netlist/devices/net_lib.cpp
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@ -74,6 +74,7 @@ namespace netlist
ENTRYX(7485, TTL_7485, "+A0,+A1,+A2,+A3,+B0,+B1,+B2,+B3,+LTIN,+EQIN,+GTIN")
ENTRYX(7490, TTL_7490, "+A,+B,+R1,+R2,+R91,+R92")
ENTRYX(7493, TTL_7493, "+CLKA,+CLKB,+R1,+R2")
ENTRYX(7497, TTL_7497, "+CLK,+STRB,+EN,+UNITY,+CLR,+B0,+B1,+B2,+B3,+B4,+B5")
ENTRYX(74107, TTL_74107, "+CLK,+J,+K,+CLRQ")
ENTRYX(74107A, TTL_74107A, "+CLK,+J,+K,+CLRQ")
ENTRYX(74123, TTL_74123, "")
@ -126,6 +127,7 @@ namespace netlist
ENTRYX(7485_dip, TTL_7485_DIP, "")
ENTRYX(7490_dip, TTL_7490_DIP, "")
ENTRYX(7493_dip, TTL_7493_DIP, "")
// ENTRYX(7497_dip, TTL_7497_DIP, "")
ENTRYX(74107_dip, TTL_74107_DIP, "")
ENTRYX(74123_dip, TTL_74123_DIP, "")
ENTRYX(74153_dip, TTL_74153_DIP, "")

1
src/lib/netlist/devices/net_lib.h
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@ -47,6 +47,7 @@
#include "nld_7485.h"
#include "nld_7490.h"
#include "nld_7493.h"
#include "nld_7497.h"
#include "nld_74107.h"
#include "nld_74123.h"
#include "nld_74153.h"

4
src/lib/netlist/devices/nld_7474.cpp
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@ -117,13 +117,13 @@ namespace netlist
sub.m_nextD = m_D();
sub.m_CLK.activate_lh();
}
else if (!m_PREQ())
else if (!m_PREQ() && m_CLRQ())
{
sub.newstate(1, 0);
sub.m_CLK.inactivate();
m_D.inactivate();
}
else if (!m_CLRQ())
else if (!m_CLRQ() && m_PREQ())
{
sub.newstate(0, 1);
sub.m_CLK.inactivate();

186
src/lib/netlist/devices/nld_7497.cpp Normal file
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@ -0,0 +1,186 @@
// license:GPL-2.0+
// copyright-holders:Sergey Svishchev
/*
* nld_7497.cpp
*
* To do:
*
* - STRB and EN
* - Timing
*/
#include "nld_7497.h"
#include "../nl_base.h"
namespace netlist
{
namespace devices
{
static constexpr netlist_time out_delay_CLK_Y[2] = { NLTIME_FROM_NS(20), NLTIME_FROM_NS(26) }; // tPHL, tPLH
static constexpr netlist_time out_delay_CLK_Z[2] = { NLTIME_FROM_NS(17), NLTIME_FROM_NS(12) };
NETLIB_OBJECT(7497)
{
NETLIB_CONSTRUCTOR(7497)
, m_B(*this, {{"B0", "B1", "B2", "B3", "B4", "B5"}})
, m_CLK(*this, "CLK", NETLIB_DELEGATE(7497, clk))
, m_STRB(*this, "STRB")
, m_EN(*this, "EN")
, m_UNITY(*this, "UNITY", NETLIB_DELEGATE(7497, unity))
, m_CLR(*this, "CLR", NETLIB_DELEGATE(7497, clr))
, m_Y(*this, "Y")
, m_Z(*this, "Z")
, m_ENOUT(*this, "ENOUT")
, m_reset(*this, "_m_reset", 0)
, m_a(*this, "_m_a", 0)
, m_rate(*this, "_m_rate", 0)
, m_state(*this, "_m_state", 0)
{
}
private:
NETLIB_RESETI();
NETLIB_UPDATEI();
NETLIB_HANDLERI(noop) { }
NETLIB_HANDLERI(unity);
NETLIB_HANDLERI(clr);
NETLIB_HANDLERI(clk);
object_array_t<logic_input_t, 6> m_B;
logic_input_t m_CLK;
logic_input_t m_STRB;
logic_input_t m_EN;
logic_input_t m_UNITY;
logic_input_t m_CLR;
logic_output_t m_Y;
logic_output_t m_Z;
logic_output_t m_ENOUT;
state_var_sig m_reset;
state_var_sig m_a;
state_var_sig m_rate;
state_var_sig m_state;
void newstate(const netlist_sig_t state)
{
m_state = state;
m_Z.push(state ^ 1, out_delay_CLK_Z[state ^ 1]);
if (m_UNITY())
m_Y.push(state, out_delay_CLK_Y[state]);
else
m_Y.push(1, out_delay_CLK_Y[1]);
if (m_CLK())
m_CLK.set_state(logic_t::STATE_INP_HL);
else
m_CLK.set_state(logic_t::STATE_INP_LH);
}
int rate()
{
int a = 0;
for (std::size_t i = 0; i < 6; i++)
a |= (m_B[i]() << i);
return a;
}
};
NETLIB_RESET(7497)
{
m_reset = 1;
m_a = 0;
m_rate = 0;
m_CLK.set_state(logic_t::STATE_INP_HL);
m_B[0].set_state(logic_t::STATE_INP_LH);
m_B[1].set_state(logic_t::STATE_INP_LH);
m_B[2].set_state(logic_t::STATE_INP_LH);
m_B[3].set_state(logic_t::STATE_INP_LH);
m_B[4].set_state(logic_t::STATE_INP_LH);
m_B[5].set_state(logic_t::STATE_INP_LH);
m_STRB.set_state(logic_t::STATE_INP_HL);
#if 0
m_EN.set_state(logic_t::STATE_INP_HL);
#endif
m_UNITY.set_state(logic_t::STATE_INP_LH);
m_CLR.set_state(logic_t::STATE_INP_LH);
newstate(0);
m_ENOUT.push(1, out_delay_CLK_Y[1]);
}
NETLIB_UPDATE(7497)
{
// m_reset = m_CLR() ^ 1;
// m_reset = 1 -- normal operation
if (!m_reset)
{
m_CLK.inactivate();
m_Y.push_force(0, NLTIME_FROM_NS(24));
m_Z.push_force(1, NLTIME_FROM_NS(15));
m_ENOUT.push_force(1, NLTIME_FROM_NS(15)); // XXX
}
}
NETLIB_HANDLER(7497, unity)
{
newstate (m_state);
}
NETLIB_HANDLER(7497, clr)
{
m_a = 0;
newstate (0);
}
NETLIB_HANDLER(7497, clk)
{
netlist_sig_t clk = m_CLK();
if (m_reset)
{
// lock rate on falling edge of CLK
if (!clk) m_rate = rate();
if (m_rate && !m_STRB())
{
if (
((m_a & 1) == 0 && (m_rate & 32)) ||
((m_a & 3) == 1 && (m_rate & 16)) ||
((m_a & 7) == 3 && (m_rate & 8)) ||
((m_a & 15) == 7 && (m_rate & 4)) ||
((m_a & 31) == 15 && (m_rate & 2)) ||
((m_a & 63) == 31 && (m_rate & 1)))
newstate(clk);
}
else
{
newstate(0);
}
if (m_a == 62)
m_ENOUT.push(0, out_delay_CLK_Y[0]); // XXX timing
else
m_ENOUT.push(1, out_delay_CLK_Y[1]);
if (clk)
{
m_CLK.set_state(logic_t::STATE_INP_HL);
m_a++;
m_a &= 63;
}
else
{
m_CLK.set_state(logic_t::STATE_INP_LH);
}
}
}
NETLIB_DEVICE_IMPL(7497)
} //namespace devices
} // namespace netlist

57
src/lib/netlist/devices/nld_7497.h Normal file
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@ -0,0 +1,57 @@
// license:GPL-2.0+
// copyright-holders:Sergey Svishchev
/*
* nld_7497.h
*
* SN7497: Synchronous 6-Bit Binary Rate Multiplier
*
* +--------------+
* B1 |1 16| VCC
* B4 |2 15| B3
* B5 |3 14| B2
* B0 |4 7497 13| CLR
* Z |5 12| UNITY/CAS
* Y |6 11| ENin (EN)
* ENout |7 10| STRB
* GND |8 9| CLK
* +--------------+
*
* Naming conventions follow TI datasheet
*
* The counter is enabled when the clear, strobe, and enable inputs are low.
*
* When the rate input is binary 0 (all rate inputs low), Z remains high [and Y low].
*
* The unity/cascade input, when connected to the clock input, passes
* clock frequency (inverted) to the Y output when the rate input/decoding
* gates are inhibited by the strobe.
*
* When CLR is H, states of CLK and STRB can affect Y and Z. Default are
* Y L, Z H, ENout H.
*
* Unity/cascade is used to inhibit output Y (UNITY L -> Y H)
*/
#ifndef NLD_7497_H_
#define NLD_7497_H_
#include "../nl_setup.h"
#define TTL_7497(name, cCLK, cSTRB, cEN, cUNITY, cCLR, cB0, cB1, cB2, cB3, cB4, cB5) \
NET_REGISTER_DEV(TTL_7497, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, STRB, cSTRB) \
NET_CONNECT(name, EN, cEN) \
NET_CONNECT(name, UNITY, cUNITY) \
NET_CONNECT(name, CLR, cCLR) \
NET_CONNECT(name, B0, cB0) \
NET_CONNECT(name, B1, cB1) \
NET_CONNECT(name, B2, cB2) \
NET_CONNECT(name, B3, cB3) \
NET_CONNECT(name, B4, cB4) \
NET_CONNECT(name, B5, cB5)
#define TTL_7497_DIP(name) \
NET_REGISTER_DEV(TTL_7497_DIP, name)
#endif /* NLD_7497_H_ */

3
src/lib/netlist/macro/nlm_base.cpp
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@ -15,6 +15,9 @@ static NETLIST_START(diode_models)
NET_MODEL("1N4001 D(Is=14.11n N=1.984 Rs=33.89m Ikf=94.81 Xti=3 Eg=1.11 Cjo=25.89p M=.44 Vj=.3245 Fc=.5 Bv=75 Ibv=10u Tt=5.7u Iave=1 Vpk=50 mfg=GI type=silicon)")
NET_MODEL("1N4148 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
NET_MODEL("1S1588 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75)")
NET_MODEL("1N34A D( Bv=75 Cjo=0.5e-12 Eg=0.67 Ibv=18e-3 Is=2e-7 Rs=7 N=1.3 Vj=0.1 M=0.27 type=germanium)")
NET_MODEL("LedRed D(IS=93.2p RS=42M N=3.73 BV=4 IBV=10U CJO=2.97P VJ=.75 M=.333 TT=4.32U Iave=40m Vpk=4 type=LED)")
NET_MODEL("LedGreen D(IS=93.2p RS=42M N=4.61 BV=4 IBV=10U CJO=2.97P VJ=.75 M=.333 TT=4.32U Iave=40m Vpk=4 type=LED)")
NET_MODEL("LedBlue D(IS=93.2p RS=42M N=7.47 BV=5 IBV=10U CJO=2.97P VJ=.75 M=.333 TT=4.32U Iave=40m Vpk=5 type=LED)")

143
src/mame/drivers/testpat.cpp Normal file
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@ -0,0 +1,143 @@
// license:BSD-3-Clause
// copyright-holders:Sergey Svishchev
/***************************************************************************
TV test pattern generators
Radio, 1983, N5
http://radioway.ru/1983/05/generator_telesignalov.html
http://radioway.ru/1984/04/generator_telesignalov.html
Radio, 1985, N6
http://radioway.ru/1985/06/generator_ispytatelnyh_signalov.html
***************************************************************************/
#include "emu.h"
#include "machine/netlist.h"
#include "video/fixfreq.h"
#include "netlist/devices/net_lib.h"
#include "machine/nl_tp1983.h"
#include "machine/nl_tp1985.h"
#include "screen.h"
#include <cmath>
#define MASTER_CLOCK (4000000)
#define V_TOTAL_PONG 315
#define H_TOTAL_PONG 256 // tbc
class tp1983_state : public driver_device
{
public:
tp1983_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_video(*this, "fixfreq")
{
}
// devices
required_device<netlist_mame_device> m_maincpu;
required_device<fixedfreq_device> m_video;
void tp1983(machine_config &config);
protected:
// driver_device overrides
virtual void machine_start() override { };
virtual void machine_reset() override { };
virtual void video_start() override { };
private:
};
class tp1985_state : public driver_device
{
public:
tp1985_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_video(*this, "fixfreq")
{
}
// devices
required_device<netlist_mame_device> m_maincpu;
required_device<fixedfreq_device> m_video;
void tp1985(machine_config &config);
protected:
// driver_device overrides
virtual void machine_start() override { };
virtual void machine_reset() override { };
virtual void video_start() override { };
private:
NETDEV_ANALOG_CALLBACK_MEMBER(video_out_cb);
};
NETDEV_ANALOG_CALLBACK_MEMBER(tp1985_state::video_out_cb)
{
m_video->update_composite_monochrome(4.0 - data, time);
}
static INPUT_PORTS_START(tp1983)
INPUT_PORTS_END
static INPUT_PORTS_START(tp1985)
INPUT_PORTS_END
MACHINE_CONFIG_START(tp1983_state::tp1983)
MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
MCFG_NETLIST_SETUP(tp1983)
MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "vid0", "videomix", fixedfreq_device, update_composite_monochrome, "fixfreq")
MCFG_FIXFREQ_ADD("fixfreq", "screen")
MCFG_FIXFREQ_MONITOR_CLOCK(MASTER_CLOCK)
MCFG_FIXFREQ_HORZ_PARAMS(H_TOTAL_PONG-64,H_TOTAL_PONG-40,H_TOTAL_PONG-8,H_TOTAL_PONG)
MCFG_FIXFREQ_VERT_PARAMS(V_TOTAL_PONG-19,V_TOTAL_PONG-16,V_TOTAL_PONG-12,V_TOTAL_PONG)
MCFG_FIXFREQ_FIELDCOUNT(1)
MCFG_FIXFREQ_SYNC_THRESHOLD(1)
MCFG_FIXFREQ_GAIN(0.36)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(tp1985_state::tp1985)
MCFG_DEVICE_ADD("maincpu", NETLIST_CPU, NETLIST_CLOCK)
MCFG_NETLIST_SETUP(tp1985)
MCFG_NETLIST_ANALOG_OUTPUT("maincpu", "vid0", "videomix", tp1985_state, video_out_cb, "")
MCFG_FIXFREQ_ADD("fixfreq", "screen")
MCFG_FIXFREQ_MONITOR_CLOCK(MASTER_CLOCK)
MCFG_FIXFREQ_HORZ_PARAMS(H_TOTAL_PONG-64,H_TOTAL_PONG-40,H_TOTAL_PONG-8,H_TOTAL_PONG)
MCFG_FIXFREQ_VERT_PARAMS(V_TOTAL_PONG-19,V_TOTAL_PONG-16,V_TOTAL_PONG-12,V_TOTAL_PONG)
MCFG_FIXFREQ_FIELDCOUNT(1)
MCFG_FIXFREQ_SYNC_THRESHOLD(1)
MCFG_FIXFREQ_GAIN(0.36)
MACHINE_CONFIG_END
ROM_START( tp1983 ) /* dummy to satisfy game entry*/
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
ROM_END
ROM_START( tp1985 ) /* dummy to satisfy game entry*/
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
ROM_END
GAME( 1983, tp1983, 0, tp1983, tp1983, tp1983_state, empty_init, ROT0, "Radio", "TV Test Pattern Generator 1983", MACHINE_NO_SOUND_HW)
GAME( 1985, tp1985, 0, tp1985, tp1985, tp1985_state, empty_init, ROT0, "Radio", "TV Test Pattern Generator 1985", MACHINE_NO_SOUND_HW)

119
src/mame/machine/nl_tp1983.cpp Normal file
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@ -0,0 +1,119 @@
// license:BSD-3-Clause
// copyright-holders:Sergey Svishchev
/***************************************************************************
Netlist (tp1983) included from testpat.cpp
***************************************************************************/
#ifndef __PLIB_PREPROCESSOR__
#define NL_PROHIBIT_BASEH_INCLUDE 1
#include "netlist/devices/net_lib.h"
#endif
// gray scale
#define SB3 0
// vertical stripes
#define SB4 1
// vertical lines
#define SB5 0
// horizontal stripes
#define SB6 0
// horizontal lines
#define SB7 0
// "M"
#define SB8 1
// inverse
//efine SB9 0
NETLIST_START(tp1983)
SOLVER(Solver, 48000)
// PARAM(Solver.PARALLEL, 0) // Don't do parallel solvers
PARAM(Solver.ACCURACY, 1e-5) // ???
// PARAM(Solver.LTE, 1e-4) // Default is not enough for paddle control if using LTE
PARAM(NETLIST.USE_DEACTIVATE, 1)
ANALOG_INPUT(V5, 5)
TTL_INPUT(high, 1)
TTL_INPUT(low, 0)
// skipping D7.1 D7.2 D8.2 clock generator circuit
MAINCLOCK(clk, 250000.0)
// vsync generator
#define _C6 0
CAP(C6, CAP_P(11))
RES(R19, RES_K(30))
#if _C6
NET_C(V5, C6.1)
#else
NET_C(DD6_2.Q, C6.1)
#endif
NET_C(C6.2, R19.1)
NET_C(R19.2, GND)
// CLK, STROBE, ENABLE, UNITY, CLR, Bx [9, 10, 11, 12, 13, ...]
TTL_7497(DD4, clk, low, low, low, DD5.Y, high, vsync, low, vsync, vsync, low)
#if 1
TTL_7497(DD5, DD4.Z, DD6_2.QQ, low, DD5.ENOUT, DD5.Y, high, DD6_1.QQ, low, low, low, low)
#else
TTL_7497(DD5, DD4.Z, low, low, DD5.ENOUT, DD5.Y, high, DD6_1.QQ, low, low, low, low)
#endif
// CLK, D, CLRQ, PREQ [3, 2, 1, 4]
#if 1
TTL_7474(DD6_1, DD5.Y, DD6_2.Q, C6.2, high)
TTL_7474(DD6_2, DD5.Y, DD6_1.QQ, C6.2, high)
#else
TTL_7474(DD6_1, DD5.Y, DD6_2.Q, low, high)
TTL_7474(DD6_2, DD5.Y, DD6_1.QQ, low, high)
#endif
ALIAS(vsync, DD6_1.Q)
// hsync generator
#if 0
CAP(C1, CAP_P(330))
CAP(C2, CAP_P(3300)) // XXX tunable 3300
RES(R2, RES_K(30))
RES(R3, 1200)
// A, B, C, D, CLEAR, LOADQ, CU, CD [15, 1, 10, 9, 14, 11, 5, 4]
TTL_74193(DD1, low, low, low, low, low, high, clk, high)
NET_C(DD1.CARRYQ, C1.1)
NET_C(R2.2, GND)
TTL_7400_NAND(DD2_1, hsync, C1.2)
NET_C(C1.2, R2.1)
NET_C(DD2_1.Q, C2.1)
NET_C(vsync, R3.1)
NET_C(R3.2, C2.2)
TTL_7400_NAND(DD2_2, C2.2, C2.2)
TTL_7400_NAND(DD2_3, hsync, hsync)
ALIAS(hsync, DD2_2.Q)
// video mixer
RES(R10, 820)
NET_C(hsync, R10.1)
ALIAS(videomix, R10.2)
#else
ALIAS(videomix, vsync)
#endif
#if 1
HINT(clk, NO_DEACTIVATE)
#endif
NETLIST_END()

4
src/mame/machine/nl_tp1983.h Normal file
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@ -0,0 +1,4 @@
// license:BSD-3-Clause
// copyright-holders:Sergey Svishchev
NETLIST_EXTERNAL(tp1983)

245
src/mame/machine/nl_tp1985.cpp Normal file
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@ -0,0 +1,245 @@
// license:BSD-3-Clause
// copyright-holders:Sergey Svishchev
/***************************************************************************
Netlist (tp1985) included from testpat.cpp
***************************************************************************/
#ifndef __PLIB_PREPROCESSOR__
#define NL_PROHIBIT_BASEH_INCLUDE 1
#include "netlist/devices/net_lib.h"
#endif
// gray scale
#define SB3 0
// vertical stripes
#define SB4 1
// vertical lines
#define SB5 0
// horizontal stripes
#define SB6 0
// horizontal lines
#define SB7 0
// "M"
#define SB8 1
// inverse
//efine SB9 0
//
#define _R19 0
//
#define _VD4 0
//
#define _DD4 1
NETLIST_START(tp1985)
SOLVER(Solver, 48000)
// PARAM(Solver.PARALLEL, 0) // Don't do parallel solvers
PARAM(Solver.ACCURACY, 1e-5) // ???
// PARAM(Solver.LTE, 1e-4) // Default is not enough for paddle control if using LTE
PARAM(NETLIST.USE_DEACTIVATE, 1)
ANALOG_INPUT(V5, 5)
TTL_INPUT(high, 1)
TTL_INPUT(low, 0)
MAINCLOCK(clk, 4000000.0)
// raster generator: DD1-DD4, DD5.3, DD5.4, DD6-DD7
RES(R1, 1000)
NET_C(R1.1, V5)
// A, B, C, D, CLEAR, LOADQ, CU, CD [15, 1, 10, 9, 14, 11, 5, 4]
TTL_74193(DD1, low, low, low, low, GND, R1.2, DD2.CARRYQ, R1.2)
TTL_74193(DD2, low, low, low, low, GND, R1.2, clk, R1.2)
ALIAS(F250K, DD2.CARRYQ)
ALIAS(F15625, DD1.CARRYQ)
RES(R2, 2000)
RES(R3, 1000)
RES(R4, 510)
RES(R5, 240)
RES(R6, 510)
RES(R7, 510)
RES(R8, 240)
DIODE(VD1, "1N34A") // XXX actually D9B
DIODE(VD2, "1N34A") // XXX actually D9B
#if SB3
DIODE(VD6, "1N34A") // XXX actually D9B
#endif
NET_C(DD1.QA, R2.1, R6.1)
NET_C(DD1.QB, R3.1, VD1.A)
NET_C(DD1.QC, R4.1)
NET_C(DD1.QD, R5.1)
NET_C(DD2.QC, R7.1)
NET_C(DD2.QD, R8.1)
NET_C(R6.2, DD3_2.D)
// and to SB1.1, SB4.2, SB3...
#if SB3
#if SB4
NET_C(R2.2, R3.2, R4.2, R5.2)
NET_C(GND, VD6.A)
#else
NET_C(R2.2, R3.2, R4.2, R5.2, VD6.A)
#endif
#else
NET_C(R2.2, R3.2, R4.2, R5.2)
#endif
// and to SB6.2
NET_C(R7.2, R8.2, VD2.A)
// CLK, D, CLRQ, PREQ [3, 2, 1, 4]
TTL_7474(DD3_1, DD1.QA, DD1.QB, DD1.CARRYQ, DD3_1.QQ)
// TTL_7474(DD3_2, VD1.K, DD2.QD, high, DD3_1.QQ) // per book, produces one pulse, shifted too far.
#if _DD4
TTL_7474(DD3_2, DD2.QD, VD1.K, DD4.Y, DD3_1.QQ) // per journal, produces two pulse, shifted correctly.
#else
TTL_7474(DD3_2, DD2.QD, VD1.K, high, DD3_1.QQ) // per journal, produces two pulse, shifted correctly.
#endif
/*
* verified:
*
* DD3.1 = hblank generator, 12 us @ 75%
* DD3.2 = hsync generator, 4 us @ 100%, shifted 2 us after hblank
* hsync period = 64us (15625 Hz)
*/
#if _DD4
RES(R12, 2000)
RES(R13, 2000)
CAP(C2, CAP_P(1000))
NET_C(V5, R13.1)
NET_C(GND, R12.1)
NET_C(C2.2, R13.2)
NET_C(R13.2, R12.2)
NET_C(DD6.QD, C2.1)
// CLK, STROBE, ENABLE, UNITY, CLR, Bx
//
// STRB, ENin are tied to GND
TTL_7497(DD4, DD3_1.QQ, low, low, DD5_3.Q, DD5_4.Q, low, DD4.Y, low, DD5_3.Q, low, low)
// TTL_7497(DD4, DD3_1.QQ, low, low, low, DD5_4.Q, low, DD4.Y, low, DD5_3.Q, low, low)
// TTL_7497(DD4, DD3_1.QQ, low, low, low, DD5_4.Q, low, DD4.Y, low, low, low, low)
TTL_7400_NAND(DD5_3, R13.2, DD4.Y)
// TTL_7400_NAND(DD5_3, high, DD4.Y)
TTL_7400_NAND(DD5_4, DD4.ENOUT, DD4.ENOUT)
TTL_7493(DD6, DD4.Z, DD4.ENOUT, DD6.QD, DD6.QB) // CLK1, CLK2, R1, R2 [14, 1, 2, 3]
#else
TTL_7497(DD4, DD3_1.QQ, low, low, low, low, low, high, low, low, low, low)
// TTL_7493(DDx, DD3_1.QQ, DD3_1.QQ, low, low)
TTL_7493(DDx, DD3_1.QQ, DD3_1.QQ, DDx.QD, DDx.QB)
#endif
// pattern selector
RES(R10, 1000)
RES(R11, 240)
RES(R14, 510)
RES(R15, 1000)
RES(R16, 510)
DIODE(VD3, "1N34A") // XXX actually D9B
#if _VD4
DIODE(VD4, "1N34A") // XXX actually D9B
#endif
DIODE(VD5, "1N34A") // XXX actually D9B
#if SB4
ALIAS(hpatsource, DD1.QA)
#endif
#if SB5
ALIAS(hpatsource, DD2.CARRYQ)
#endif
#if !(SB4+SB5)
ALIAS(hpatsource, R11.2)
#endif
#if SB6
ALIAS(vpatsource, DD6.QA)
#endif
#if SB7
ALIAS(vpatsource, DD4.Z)
#endif
#if !(SB6+SB7)
ALIAS(vpatsource, R11.2)
#endif
NET_C(V5, R10.1)
NET_C(V5, R11.1)
NET_C(V5, R15.1)
NET_C(R11.2, VD3.A)
NET_C(hpatsource, R14.1)
NET_C(R14.2, DD7_2.A)
TTL_7400_NAND(DD7_1, hpatsource, vpatsource)
#if !SB8
TTL_7400_NAND(DD7_2, VD3.K, R15.2)
NET_C(VD2.K, DD7_2.B)
#else
TTL_7400_NAND(DD7_2, VD3.K, DD7_1.Q)
NET_C(R15.2, GND)
NET_C(VD2.K, GND)
#endif
#if _VD4
NET_C(DD7_2.Q, VD4.K)
NET_C(VD4.A, R16.2)
#else
NET_C(DD7_2.Q, R16.2)
#endif
NET_C(DD3_1.Q, R16.1)
TTL_7400_NAND(DD7_3, DD7_2.Q, R10.2)
TTL_7400_NAND(DD7_4, R16.1, DD7_3.Q)
NET_C(DD7_4.Q, VD5.A)
NET_C(VD5.K, R17.1)
#if SB3
NET_C(VD6.K, R17.1)
#endif
// video mixer
#ifdef VD7
DIODE(VD7, "1N34A") // XXX actually D9B
#endif
RES(R17, 10) // XXX actually 470 ohm POT
RES(R18, 430)
#if _R19
RES(R19, 430)
CAP(C3, CAP_U(50))
#endif
#ifdef VD7
NET_C(DD3_2.QQ, VD7.A)
NET_C(VD7.K, R18.1)
#else
NET_C(DD3_2.QQ, R18.1)
#endif
NET_C(R17.2, R18.2) // XXX
#if _R19
NET_C(GND, R19.1)
NET_C(R18.2, C3.2)
NET_C(R19.2, C3.2)
ALIAS(videomix, C3.1)
#else
ALIAS(videomix, R18.2)
#endif
#if 1
HINT(clk, NO_DEACTIVATE)
#endif
NETLIST_END()

4
src/mame/machine/nl_tp1985.h Normal file
View File

@ -0,0 +1,4 @@
// license:BSD-3-Clause
// copyright-holders:Sergey Svishchev
NETLIST_EXTERNAL(tp1985)

4
src/mame/mame.lst
View File

@ -40117,6 +40117,10 @@ zx80 // 1980 Sinclair ZX-80
zx81 // 1981 Sinclair ZX-81
zx97 //
@source:testpat.cpp
tp1983
tp1985
@source:vgmplay.cpp
vgmplay