mirror of
https://github.com/holub/mame
synced 2025-04-19 07:00:31 +03:00
fm7.cpp: First cleanup pass
- Separate state classes - Scope down macros and structs - Shorten many handler names - Eliminate a little of the RAM region abuse
This commit is contained in:
AJR
parent
402b885847
commit
43af60c1cd
File diff suppressed because it is too large
Load Diff
@ -22,107 +22,17 @@
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#include "emupal.h"
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// Interrupt flags
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#define IRQ_FLAG_KEY 0x01
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#define IRQ_FLAG_PRINTER 0x02
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#define IRQ_FLAG_TIMER 0x04
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#define IRQ_FLAG_OTHER 0x08
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// the following are not read in port 0xfd03
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#define IRQ_FLAG_MFD 0x10
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#define IRQ_FLAG_TXRDY 0x20
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#define IRQ_FLAG_RXRDY 0x40
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#define IRQ_FLAG_SYNDET 0x80
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// system types
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#define SYS_FM7 1
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#define SYS_FM77AV 2
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#define SYS_FM77AV40EX 3
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#define SYS_FM11 4
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#define SYS_FM16 5
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// keyboard scancode formats
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#define KEY_MODE_FM7 0 // FM-7 ASCII type code
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#define KEY_MODE_FM16B 1 // FM-16B (FM-77AV and later only)
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#define KEY_MODE_SCAN 2 // Scancode Make/Break (PC-like)
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struct fm7_encoder_t
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{
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uint8_t buffer[12];
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uint8_t tx_count;
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uint8_t rx_count;
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uint8_t command_length;
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uint8_t answer_length;
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uint8_t latch; // 0=ready to receive
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uint8_t ack;
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uint8_t position;
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};
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struct fm7_mmr_t
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{
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uint8_t bank_addr[8][16];
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uint8_t segment;
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uint8_t window_offset;
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uint8_t enabled;
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uint8_t mode;
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};
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struct fm7_video_t
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{
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uint8_t sub_busy;
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uint8_t sub_halt;
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uint8_t sub_reset; // high if reset caused by subrom change
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uint8_t attn_irq;
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uint8_t vram_access; // VRAM access flag
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uint8_t crt_enable;
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uint16_t vram_offset;
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uint16_t vram_offset2;
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uint8_t fm7_pal[8];
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uint16_t fm77av_pal_selected;
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uint8_t subrom; // currently active sub CPU ROM (AV only)
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uint8_t cgrom; // currently active CGROM (AV only)
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uint8_t modestatus;
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uint8_t multi_page;
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uint8_t fine_offset;
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uint8_t nmi_mask;
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uint8_t active_video_page;
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uint8_t display_video_page;
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uint8_t vsync_flag;
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};
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struct fm7_alu_t
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{
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uint8_t command;
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uint8_t lcolour;
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uint8_t mask;
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uint8_t compare_data;
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uint8_t compare[8];
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uint8_t bank_disable;
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uint8_t tilepaint_b;
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uint8_t tilepaint_r;
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uint8_t tilepaint_g;
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uint16_t addr_offset;
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uint16_t line_style;
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uint16_t x0;
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uint16_t x1;
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uint16_t y0;
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uint16_t y1;
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uint8_t busy;
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};
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class fm7_state : public driver_device
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{
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public:
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fm7_state(const machine_config &mconfig, device_type type, const char *tag) :
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driver_device(mconfig, type, tag),
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m_shared_ram(*this, "shared_ram"),
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m_boot_ram(*this, "boot_ram"),
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m_vectors(*this, "vectors"),
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m_maincpu(*this, "maincpu"),
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m_sub(*this, "sub"),
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m_x86(*this, "x86"),
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m_cassette(*this, "cassette"),
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m_beeper(*this, "beeper"),
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m_ym(*this, "ym"),
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m_psg(*this, "psg"),
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m_screen(*this, "screen"),
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m_centronics(*this, "centronics"),
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@ -140,20 +50,17 @@ public:
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m_joy1(*this, "joy1"),
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m_dsw(*this, "DSW"),
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m_palette(*this, "palette"),
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m_av_palette(*this, "av_palette"),
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m_avbank(*this, "av_bank%u", 1)
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m_av_palette(*this, "av_palette")
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{
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}
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void fm16beta(machine_config &config);
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void fm8(machine_config &config);
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void fm7(machine_config &config);
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void fm77av(machine_config &config);
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void fm11(machine_config &config);
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void init_fm7();
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private:
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protected:
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enum
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{
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TIMER_FM7_BEEPER_OFF,
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@ -165,107 +72,134 @@ private:
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TIMER_FM77AV_VSYNC
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};
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// Interrupt flags
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enum : uint8_t
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{
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IRQ_FLAG_KEY = 0x01,
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IRQ_FLAG_PRINTER = 0x02,
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IRQ_FLAG_TIMER = 0x04,
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IRQ_FLAG_OTHER = 0x08,
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// the following are not read in port 0xfd03
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IRQ_FLAG_MFD = 0x10,
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IRQ_FLAG_TXRDY = 0x20,
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IRQ_FLAG_RXRDY = 0x40,
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IRQ_FLAG_SYNDET = 0x80
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};
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// system types
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enum
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{
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SYS_FM7 = 1,
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SYS_FM77AV = 2,
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SYS_FM77AV40EX = 3,
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SYS_FM11 = 4,
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SYS_FM16 = 5
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};
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// keyboard scancode formats
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enum
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{
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KEY_MODE_FM7 = 0, // FM-7 ASCII type code
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KEY_MODE_FM16B = 1, // FM-16B (FM-77AV and later only)
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KEY_MODE_SCAN = 2 // Scancode Make/Break (PC-like)
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};
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struct fm7_video_t
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{
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uint8_t sub_busy;
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uint8_t sub_halt;
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uint8_t sub_reset; // high if reset caused by subrom change
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uint8_t attn_irq;
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uint8_t vram_access; // VRAM access flag
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uint8_t crt_enable;
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uint16_t vram_offset;
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uint16_t vram_offset2;
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uint8_t fm7_pal[8];
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uint16_t fm77av_pal_selected;
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uint8_t subrom; // currently active sub CPU ROM (AV only)
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uint8_t cgrom; // currently active CGROM (AV only)
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uint8_t modestatus;
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uint8_t multi_page;
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uint8_t fine_offset;
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uint8_t nmi_mask;
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uint8_t active_video_page;
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uint8_t display_video_page;
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uint8_t vsync_flag;
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};
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struct fm7_alu_t
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{
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uint8_t command;
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uint8_t lcolour;
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uint8_t mask;
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uint8_t compare_data;
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uint8_t compare[8];
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uint8_t bank_disable;
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uint8_t tilepaint_b;
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uint8_t tilepaint_r;
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uint8_t tilepaint_g;
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uint16_t addr_offset;
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uint16_t line_style;
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uint16_t x0;
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uint16_t x1;
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uint16_t y0;
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uint16_t y1;
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uint8_t busy;
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};
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virtual void machine_reset() override;
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virtual void video_start() override;
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virtual void fm7_alu_function(uint32_t offset) { }
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virtual void fm7_mmr_refresh(address_space &space) { }
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DECLARE_MACHINE_START(fm7);
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DECLARE_MACHINE_START(fm77av);
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DECLARE_MACHINE_START(fm11);
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DECLARE_MACHINE_START(fm16);
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DECLARE_WRITE_LINE_MEMBER(fm7_fdc_intrq_w);
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DECLARE_WRITE_LINE_MEMBER(fm7_fdc_drq_w);
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DECLARE_WRITE_LINE_MEMBER(fm77av_fmirq);
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DECLARE_WRITE_LINE_MEMBER(fdc_intrq_w);
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DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
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uint8_t fm7_subintf_r();
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void fm7_subintf_w(uint8_t data);
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uint8_t fm7_sub_busyflag_r();
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void fm7_sub_busyflag_w(uint8_t data);
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uint8_t fm7_cancel_ack();
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uint8_t fm7_attn_irq_r();
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uint8_t fm7_vram_access_r();
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void fm7_vram_access_w(uint8_t data);
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uint8_t fm7_vram_r(offs_t offset);
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void fm7_vram_w(offs_t offset, uint8_t data);
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void fm7_vram_banked_w(offs_t offset, uint8_t data);
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uint8_t fm7_vram0_r(offs_t offset);
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uint8_t fm7_vram1_r(offs_t offset);
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uint8_t fm7_vram2_r(offs_t offset);
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uint8_t fm7_vram3_r(offs_t offset);
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uint8_t fm7_vram4_r(offs_t offset);
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uint8_t fm7_vram5_r(offs_t offset);
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uint8_t fm7_vram6_r(offs_t offset);
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uint8_t fm7_vram7_r(offs_t offset);
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uint8_t fm7_vram8_r(offs_t offset);
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uint8_t fm7_vram9_r(offs_t offset);
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uint8_t fm7_vramA_r(offs_t offset);
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uint8_t fm7_vramB_r(offs_t offset);
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void fm7_vram0_w(offs_t offset, uint8_t data);
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void fm7_vram1_w(offs_t offset, uint8_t data);
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void fm7_vram2_w(offs_t offset, uint8_t data);
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void fm7_vram3_w(offs_t offset, uint8_t data);
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void fm7_vram4_w(offs_t offset, uint8_t data);
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void fm7_vram5_w(offs_t offset, uint8_t data);
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void fm7_vram6_w(offs_t offset, uint8_t data);
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void fm7_vram7_w(offs_t offset, uint8_t data);
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void fm7_vram8_w(offs_t offset, uint8_t data);
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void fm7_vram9_w(offs_t offset, uint8_t data);
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void fm7_vramA_w(offs_t offset, uint8_t data);
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void fm7_vramB_w(offs_t offset, uint8_t data);
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uint8_t fm7_crt_r();
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void fm7_crt_w(uint8_t data);
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void fm7_vram_offset_w(offs_t offset, uint8_t data);
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void fm7_multipage_w(uint8_t data);
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uint8_t fm7_palette_r(offs_t offset);
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void fm7_palette_w(offs_t offset, uint8_t data);
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void fm77av_analog_palette_w(offs_t offset, uint8_t data);
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uint8_t fm77av_video_flags_r();
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void fm77av_video_flags_w(uint8_t data);
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uint8_t fm77av_sub_modestatus_r();
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void fm77av_sub_modestatus_w(uint8_t data);
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void fm77av_sub_bank_w(uint8_t data);
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uint8_t fm77av_alu_r(offs_t offset);
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void fm77av_alu_w(offs_t offset, uint8_t data);
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uint8_t fm7_sub_ram_ports_banked_r(offs_t offset);
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void fm7_sub_ram_ports_banked_w(offs_t offset, uint8_t data);
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uint8_t fm7_console_ram_banked_r(offs_t offset);
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void fm7_console_ram_banked_w(offs_t offset, uint8_t data);
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void fm7_irq_mask_w(uint8_t data);
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uint8_t fm7_irq_cause_r();
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void fm7_beeper_w(uint8_t data);
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uint8_t fm7_sub_beeper_r();
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uint8_t vector_r(offs_t offset);
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void vector_w(offs_t offset, uint8_t data);
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uint8_t fm7_fd04_r();
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uint8_t fm7_rom_en_r(address_space &space);
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void fm7_rom_en_w(address_space &space, uint8_t data);
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void fm7_init_en_w(address_space &space, uint8_t data);
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uint8_t fm7_fdc_r(offs_t offset);
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void fm7_fdc_w(offs_t offset, uint8_t data);
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uint8_t fm7_keyboard_r(offs_t offset);
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uint8_t fm7_sub_keyboard_r(offs_t offset);
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uint8_t fm77av_key_encoder_r(offs_t offset);
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void fm77av_key_encoder_w(offs_t offset, uint8_t data);
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uint8_t fm7_cassette_printer_r();
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void fm7_cassette_printer_w(offs_t offset, uint8_t data);
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uint8_t fm77av_boot_mode_r();
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uint8_t fm7_psg_select_r();
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void fm7_psg_select_w(uint8_t data);
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void fm77av_ym_select_w(uint8_t data);
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uint8_t fm7_psg_data_r();
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void fm7_psg_data_w(uint8_t data);
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void fm77av_bootram_w(offs_t offset, uint8_t data);
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uint8_t fm7_main_shared_r(offs_t offset);
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void fm7_main_shared_w(offs_t offset, uint8_t data);
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uint8_t fm7_fmirq_r();
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uint8_t fm7_unknown_r();
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uint8_t fm7_mmr_r(offs_t offset);
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void fm7_mmr_w(address_space &space, offs_t offset, uint8_t data);
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uint8_t fm7_kanji_r(offs_t offset);
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void fm7_kanji_w(offs_t offset, uint8_t data);
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uint8_t subintf_r();
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void subintf_w(uint8_t data);
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uint8_t sub_busyflag_r();
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void sub_busyflag_w(uint8_t data);
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uint8_t cancel_ack();
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uint8_t attn_irq_r();
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uint8_t vram_access_r();
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void vram_access_w(uint8_t data);
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uint8_t vram_r(offs_t offset);
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void vram_w(offs_t offset, uint8_t data);
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uint8_t crt_r();
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void crt_w(uint8_t data);
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void vram_offset_w(offs_t offset, uint8_t data);
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void multipage_w(uint8_t data);
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uint8_t palette_r(offs_t offset);
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void palette_w(offs_t offset, uint8_t data);
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void irq_mask_w(uint8_t data);
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uint8_t irq_cause_r();
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void beeper_w(uint8_t data);
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uint8_t sub_beeper_r();
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uint8_t fd04_r();
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uint8_t rom_en_r(address_space &space);
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void rom_en_w(address_space &space, uint8_t data);
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uint8_t fdc_r(offs_t offset);
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void fdc_w(offs_t offset, uint8_t data);
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uint8_t keyboard_r(offs_t offset);
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uint8_t sub_keyboard_r(offs_t offset);
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uint8_t cassette_printer_r();
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void cassette_printer_w(offs_t offset, uint8_t data);
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uint8_t psg_select_r();
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void psg_select_w(uint8_t data);
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uint8_t psg_data_r();
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void psg_data_w(uint8_t data);
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uint8_t main_shared_r(offs_t offset);
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void main_shared_w(offs_t offset, uint8_t data);
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uint8_t unknown_r();
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uint8_t kanji_r(offs_t offset);
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void kanji_w(offs_t offset, uint8_t data);
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IRQ_CALLBACK_MEMBER(fm7_irq_ack);
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IRQ_CALLBACK_MEMBER(fm7_sub_irq_ack);
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IRQ_CALLBACK_MEMBER(irq_ack);
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IRQ_CALLBACK_MEMBER(sub_irq_ack);
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DECLARE_WRITE_LINE_MEMBER(write_centronics_busy);
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DECLARE_WRITE_LINE_MEMBER(write_centronics_fault);
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@ -274,30 +208,23 @@ private:
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uint32_t screen_update_fm7(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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void fm11_mem(address_map &map);
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void fm11_sub_mem(address_map &map);
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void fm11_x86_io(address_map &map);
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void fm11_x86_mem(address_map &map);
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void fm16_io(address_map &map);
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void fm16_mem(address_map &map);
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void fm16_sub_mem(address_map &map);
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void fm77av_mem(address_map &map);
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void fm77av_sub_mem(address_map &map);
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void fm7_banked_mem(address_map &map);
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void fm7_mem(address_map &map);
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void fm7_sub_mem(address_map &map);
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void fm8_mem(address_map &map);
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optional_shared_ptr<uint8_t> m_shared_ram;
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optional_shared_ptr<uint8_t> m_boot_ram;
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required_shared_ptr<uint8_t> m_vectors;
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uint8_t m_irq_flags;
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uint8_t m_irq_mask;
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emu_timer* m_timer;
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emu_timer* m_subtimer;
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emu_timer* m_keyboard_timer;
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uint8_t m_basic_rom_en;
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uint8_t m_init_rom_en;
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bool m_basic_rom_en;
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bool m_init_rom_en;
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unsigned int m_key_delay;
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unsigned int m_key_repeat;
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@ -315,37 +242,26 @@ private:
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uint8_t m_fdc_irq_flag;
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uint8_t m_fdc_drq_flag;
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uint8_t m_fm77av_ym_irq;
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uint8_t m_speaker_active;
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uint16_t m_kanji_address;
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fm7_encoder_t m_encoder;
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fm7_mmr_t m_mmr;
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uint8_t m_cp_prev;
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||||
|
||||
std::unique_ptr<uint8_t[]> m_video_ram;
|
||||
emu_timer* m_fm77av_vsync_timer;
|
||||
uint8_t m_type;
|
||||
fm7_video_t m_video;
|
||||
fm7_alu_t m_alu;
|
||||
int m_sb_prev;
|
||||
|
||||
void fm77av_encoder_setup_command();
|
||||
void fm77av_encoder_handle_command();
|
||||
TIMER_CALLBACK_MEMBER(fm7_beeper_off);
|
||||
TIMER_CALLBACK_MEMBER(fm77av_encoder_ack);
|
||||
TIMER_CALLBACK_MEMBER(fm7_timer_irq);
|
||||
TIMER_CALLBACK_MEMBER(fm7_subtimer_irq);
|
||||
TIMER_CALLBACK_MEMBER(fm7_keyboard_poll);
|
||||
TIMER_CALLBACK_MEMBER(fm77av_alu_task_end);
|
||||
TIMER_CALLBACK_MEMBER(fm77av_vsync);
|
||||
TIMER_CALLBACK_MEMBER(beeper_off);
|
||||
TIMER_CALLBACK_MEMBER(timer_irq);
|
||||
TIMER_CALLBACK_MEMBER(subtimer_irq);
|
||||
TIMER_CALLBACK_MEMBER(keyboard_poll);
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<cpu_device> m_sub;
|
||||
optional_device<cpu_device> m_x86;
|
||||
required_device<cassette_image_device> m_cassette;
|
||||
required_device<beep_device> m_beeper;
|
||||
optional_device<ym2203_device> m_ym;
|
||||
optional_device<ay8910_device> m_psg;
|
||||
required_device<screen_device> m_screen;
|
||||
|
||||
@ -361,25 +277,11 @@ private:
|
||||
optional_region_ptr<uint8_t> m_rom_ptr;
|
||||
optional_region_ptr<uint8_t> m_basic_ptr;
|
||||
|
||||
void fm7_alu_mask_write(uint32_t offset, int bank, uint8_t dat);
|
||||
void fm7_alu_function_compare(uint32_t offset);
|
||||
void fm7_alu_function_pset(uint32_t offset);
|
||||
void fm7_alu_function_or(uint32_t offset);
|
||||
void fm7_alu_function_and(uint32_t offset);
|
||||
void fm7_alu_function_xor(uint32_t offset);
|
||||
void fm7_alu_function_not(uint32_t offset);
|
||||
void fm7_alu_function_invalid(uint32_t offset);
|
||||
void fm7_alu_function_tilepaint(uint32_t offset);
|
||||
void fm7_alu_function(uint32_t offset);
|
||||
uint32_t fm7_line_set_pixel(int x, int y);
|
||||
void fm77av_line_draw();
|
||||
void main_irq_set_flag(uint8_t flag);
|
||||
void main_irq_clear_flag(uint8_t flag);
|
||||
void fm7_update_psg();
|
||||
void fm7_update_bank(address_space & space, int bank, uint8_t physical);
|
||||
void fm7_mmr_refresh(address_space& space);
|
||||
virtual void fm7_update_psg();
|
||||
void key_press(uint16_t scancode);
|
||||
void fm7_keyboard_poll_scan();
|
||||
void keyboard_poll_scan();
|
||||
|
||||
int m_centronics_busy;
|
||||
int m_centronics_fault;
|
||||
@ -394,9 +296,161 @@ private:
|
||||
required_device<palette_device> m_palette;
|
||||
optional_device<palette_device> m_av_palette;
|
||||
|
||||
optional_device_array<address_map_bank_device, 16> m_avbank;
|
||||
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||
};
|
||||
|
||||
class fm77_state : public fm7_state
|
||||
{
|
||||
public:
|
||||
fm77_state(const machine_config &mconfig, device_type type, const char *tag) :
|
||||
fm7_state(mconfig, type, tag),
|
||||
m_avbank(*this, "av_bank%u", 1),
|
||||
m_ym(*this, "ym"),
|
||||
m_boot_ram(*this, "boot_ram")
|
||||
{
|
||||
}
|
||||
|
||||
void fm77av(machine_config &config);
|
||||
|
||||
protected:
|
||||
struct fm7_encoder_t
|
||||
{
|
||||
uint8_t buffer[12];
|
||||
uint8_t tx_count;
|
||||
uint8_t rx_count;
|
||||
uint8_t command_length;
|
||||
uint8_t answer_length;
|
||||
uint8_t latch; // 0=ready to receive
|
||||
uint8_t ack;
|
||||
uint8_t position;
|
||||
};
|
||||
|
||||
struct fm7_mmr_t
|
||||
{
|
||||
uint8_t bank_addr[8][16];
|
||||
uint8_t segment;
|
||||
uint8_t window_offset;
|
||||
uint8_t enabled;
|
||||
uint8_t mode;
|
||||
};
|
||||
|
||||
virtual void machine_reset() override;
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||
|
||||
DECLARE_MACHINE_START(fm77av);
|
||||
|
||||
void av_encoder_setup_command();
|
||||
void av_encoder_handle_command();
|
||||
TIMER_CALLBACK_MEMBER(av_encoder_ack);
|
||||
TIMER_CALLBACK_MEMBER(av_alu_task_end);
|
||||
TIMER_CALLBACK_MEMBER(av_vsync);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(av_fmirq);
|
||||
|
||||
void vram_banked_w(offs_t offset, uint8_t data);
|
||||
uint8_t vram0_r(offs_t offset);
|
||||
uint8_t vram1_r(offs_t offset);
|
||||
uint8_t vram2_r(offs_t offset);
|
||||
uint8_t vram3_r(offs_t offset);
|
||||
uint8_t vram4_r(offs_t offset);
|
||||
uint8_t vram5_r(offs_t offset);
|
||||
uint8_t vram6_r(offs_t offset);
|
||||
uint8_t vram7_r(offs_t offset);
|
||||
uint8_t vram8_r(offs_t offset);
|
||||
uint8_t vram9_r(offs_t offset);
|
||||
uint8_t vramA_r(offs_t offset);
|
||||
uint8_t vramB_r(offs_t offset);
|
||||
void vram0_w(offs_t offset, uint8_t data);
|
||||
void vram1_w(offs_t offset, uint8_t data);
|
||||
void vram2_w(offs_t offset, uint8_t data);
|
||||
void vram3_w(offs_t offset, uint8_t data);
|
||||
void vram4_w(offs_t offset, uint8_t data);
|
||||
void vram5_w(offs_t offset, uint8_t data);
|
||||
void vram6_w(offs_t offset, uint8_t data);
|
||||
void vram7_w(offs_t offset, uint8_t data);
|
||||
void vram8_w(offs_t offset, uint8_t data);
|
||||
void vram9_w(offs_t offset, uint8_t data);
|
||||
void vramA_w(offs_t offset, uint8_t data);
|
||||
void vramB_w(offs_t offset, uint8_t data);
|
||||
uint8_t console_ram_banked_r(offs_t offset);
|
||||
void console_ram_banked_w(offs_t offset, uint8_t data);
|
||||
uint8_t sub_ram_ports_banked_r(offs_t offset);
|
||||
void sub_ram_ports_banked_w(offs_t offset, uint8_t data);
|
||||
void av_analog_palette_w(offs_t offset, uint8_t data);
|
||||
uint8_t av_video_flags_r();
|
||||
void av_video_flags_w(uint8_t data);
|
||||
uint8_t av_sub_modestatus_r();
|
||||
void av_sub_modestatus_w(uint8_t data);
|
||||
void av_sub_bank_w(uint8_t data);
|
||||
uint8_t av_alu_r(offs_t offset);
|
||||
void av_alu_w(offs_t offset, uint8_t data);
|
||||
void av_bootram_w(offs_t offset, uint8_t data);
|
||||
uint8_t av_key_encoder_r(offs_t offset);
|
||||
void av_key_encoder_w(offs_t offset, uint8_t data);
|
||||
uint8_t av_boot_mode_r();
|
||||
void av_ym_select_w(uint8_t data);
|
||||
uint8_t vector_r(offs_t offset);
|
||||
void init_en_w(address_space &space, uint8_t data);
|
||||
uint8_t fmirq_r();
|
||||
virtual void fm7_update_psg() override;
|
||||
|
||||
uint8_t mmr_r(offs_t offset);
|
||||
void mmr_w(address_space &space, offs_t offset, uint8_t data);
|
||||
void fm7_update_bank(address_space &space, int bank, uint8_t physical);
|
||||
virtual void fm7_mmr_refresh(address_space &space) override;
|
||||
|
||||
void alu_mask_write(uint32_t offset, int bank, uint8_t dat);
|
||||
void alu_function_compare(uint32_t offset);
|
||||
void alu_function_pset(uint32_t offset);
|
||||
void alu_function_or(uint32_t offset);
|
||||
void alu_function_and(uint32_t offset);
|
||||
void alu_function_xor(uint32_t offset);
|
||||
void alu_function_not(uint32_t offset);
|
||||
void alu_function_invalid(uint32_t offset);
|
||||
void alu_function_tilepaint(uint32_t offset);
|
||||
virtual void fm7_alu_function(uint32_t offset) override;
|
||||
uint32_t av_line_set_pixel(int x, int y);
|
||||
void av_line_draw();
|
||||
|
||||
void fm77av_mem(address_map &map);
|
||||
void fm77av_sub_mem(address_map &map);
|
||||
void fm7_banked_mem(address_map &map);
|
||||
|
||||
required_device_array<address_map_bank_device, 16> m_avbank;
|
||||
optional_device<ym2203_device> m_ym;
|
||||
required_shared_ptr<uint8_t> m_boot_ram;
|
||||
|
||||
fm7_encoder_t m_encoder;
|
||||
fm7_mmr_t m_mmr;
|
||||
|
||||
emu_timer* m_vsync_timer;
|
||||
|
||||
uint8_t m_fm77av_ym_irq;
|
||||
};
|
||||
|
||||
class fm11_state : public fm77_state
|
||||
{
|
||||
public:
|
||||
fm11_state(const machine_config &mconfig, device_type type, const char *tag) :
|
||||
fm77_state(mconfig, type, tag),
|
||||
m_x86(*this, "x86")
|
||||
{
|
||||
}
|
||||
|
||||
void fm11(machine_config &config);
|
||||
|
||||
protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
DECLARE_MACHINE_START(fm11);
|
||||
|
||||
void fm11_mem(address_map &map);
|
||||
void fm11_sub_mem(address_map &map);
|
||||
void fm11_x86_io(address_map &map);
|
||||
void fm11_x86_mem(address_map &map);
|
||||
|
||||
required_device<cpu_device> m_x86;
|
||||
};
|
||||
|
||||
#endif // MAME_INCLUDES_FM7_H
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
* bit 6: Sub-CPU cancel IRQ
|
||||
*/
|
||||
|
||||
uint8_t fm7_state::fm7_subintf_r()
|
||||
uint8_t fm7_state::subintf_r()
|
||||
{
|
||||
uint8_t ret = 0x00;
|
||||
|
||||
@ -37,7 +37,7 @@ uint8_t fm7_state::fm7_subintf_r()
|
||||
return ret;
|
||||
}
|
||||
|
||||
void fm7_state::fm7_subintf_w(uint8_t data)
|
||||
void fm7_state::subintf_w(uint8_t data)
|
||||
{
|
||||
m_video.sub_halt = data & 0x80;
|
||||
if(data & 0x80)
|
||||
@ -49,14 +49,14 @@ void fm7_state::fm7_subintf_w(uint8_t data)
|
||||
//popmessage("Sub CPU Interface write: %02x\n",data);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_sub_busyflag_r()
|
||||
uint8_t fm7_state::sub_busyflag_r()
|
||||
{
|
||||
if(m_video.sub_halt == 0)
|
||||
m_video.sub_busy = 0x00;
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
void fm7_state::fm7_sub_busyflag_w(uint8_t data)
|
||||
void fm7_state::sub_busyflag_w(uint8_t data)
|
||||
{
|
||||
m_video.sub_busy = 0x80;
|
||||
}
|
||||
@ -65,7 +65,7 @@ void fm7_state::fm7_sub_busyflag_w(uint8_t data)
|
||||
* Sub-CPU port 0xd402
|
||||
* Read-only: Acknowledge Cancel IRQ
|
||||
*/
|
||||
uint8_t fm7_state::fm7_cancel_ack()
|
||||
uint8_t fm7_state::cancel_ack()
|
||||
{
|
||||
m_sub->set_input_line(M6809_IRQ_LINE,CLEAR_LINE);
|
||||
return 0x00;
|
||||
@ -74,7 +74,7 @@ uint8_t fm7_state::fm7_cancel_ack()
|
||||
/*
|
||||
* Reading from 0xd404 (sub-CPU) causes an "Attention" FIRQ on the main CPU
|
||||
*/
|
||||
uint8_t fm7_state::fm7_attn_irq_r()
|
||||
uint8_t fm7_state::attn_irq_r()
|
||||
{
|
||||
m_video.attn_irq = 1;
|
||||
m_maincpu->set_input_line(M6809_FIRQ_LINE,ASSERT_LINE);
|
||||
@ -87,23 +87,23 @@ uint8_t fm7_state::fm7_attn_irq_r()
|
||||
* On read, enables VRAM access
|
||||
* On write, disables VRAM access
|
||||
*/
|
||||
uint8_t fm7_state::fm7_vram_access_r()
|
||||
uint8_t fm7_state::vram_access_r()
|
||||
{
|
||||
m_video.vram_access = 1;
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram_access_w(uint8_t data)
|
||||
void fm7_state::vram_access_w(uint8_t data)
|
||||
{
|
||||
m_video.vram_access = 0;
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(fm7_state::fm77av_alu_task_end)
|
||||
TIMER_CALLBACK_MEMBER(fm77_state::av_alu_task_end)
|
||||
{
|
||||
m_alu.busy = 0;
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_mask_write(uint32_t offset, int bank, uint8_t dat)
|
||||
void fm77_state::alu_mask_write(uint32_t offset, int bank, uint8_t dat)
|
||||
{
|
||||
uint8_t temp;
|
||||
int page = 0;
|
||||
@ -132,7 +132,7 @@ void fm7_state::fm7_alu_mask_write(uint32_t offset, int bank, uint8_t dat)
|
||||
m_video_ram[(offset & 0x3fff) + (bank * 0x4000) + (page * 0xc000)] = temp | dat;
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function_compare(uint32_t offset)
|
||||
void fm77_state::alu_function_compare(uint32_t offset)
|
||||
{
|
||||
// COMPARE - compares which colors match those in the compare registers
|
||||
// can be used on its own, or when bit 6 of the command register is high.
|
||||
@ -187,7 +187,7 @@ void fm7_state::fm7_alu_function_compare(uint32_t offset)
|
||||
m_alu.compare_data = dat;
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function_pset(uint32_t offset)
|
||||
void fm77_state::alu_function_pset(uint32_t offset)
|
||||
{
|
||||
// PSET - simply sets the pixels to the selected logical colour
|
||||
int x;
|
||||
@ -196,7 +196,7 @@ void fm7_state::fm7_alu_function_pset(uint32_t offset)
|
||||
uint8_t mask;
|
||||
|
||||
if(m_alu.command & 0x40)
|
||||
fm7_alu_function_compare(offset);
|
||||
alu_function_compare(offset);
|
||||
|
||||
if(offset >= 0xc000)
|
||||
{
|
||||
@ -219,12 +219,12 @@ void fm7_state::fm7_alu_function_pset(uint32_t offset)
|
||||
dat &= ~m_alu.mask;
|
||||
dat |= mask;
|
||||
|
||||
fm7_alu_mask_write(offset,x,dat);
|
||||
alu_mask_write(offset,x,dat);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function_or(uint32_t offset)
|
||||
void fm77_state::alu_function_or(uint32_t offset)
|
||||
{
|
||||
int x;
|
||||
uint8_t dat;
|
||||
@ -232,7 +232,7 @@ void fm7_state::fm7_alu_function_or(uint32_t offset)
|
||||
uint8_t mask;
|
||||
|
||||
if(m_alu.command & 0x40)
|
||||
fm7_alu_function_compare(offset);
|
||||
alu_function_compare(offset);
|
||||
|
||||
if(offset >= 0xc000)
|
||||
{
|
||||
@ -258,12 +258,12 @@ void fm7_state::fm7_alu_function_or(uint32_t offset)
|
||||
dat &= ~m_alu.mask;
|
||||
dat |= mask;
|
||||
|
||||
fm7_alu_mask_write(offset,x,dat);
|
||||
alu_mask_write(offset,x,dat);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function_and(uint32_t offset)
|
||||
void fm77_state::alu_function_and(uint32_t offset)
|
||||
{
|
||||
int x;
|
||||
uint8_t dat;
|
||||
@ -271,7 +271,7 @@ void fm7_state::fm7_alu_function_and(uint32_t offset)
|
||||
uint8_t mask;
|
||||
|
||||
if(m_alu.command & 0x40)
|
||||
fm7_alu_function_compare(offset);
|
||||
alu_function_compare(offset);
|
||||
|
||||
if(offset >= 0xc000)
|
||||
{
|
||||
@ -297,12 +297,12 @@ void fm7_state::fm7_alu_function_and(uint32_t offset)
|
||||
dat &= ~m_alu.mask;
|
||||
dat |= mask;
|
||||
|
||||
fm7_alu_mask_write(offset,x,dat);
|
||||
alu_mask_write(offset,x,dat);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function_xor(uint32_t offset)
|
||||
void fm77_state::alu_function_xor(uint32_t offset)
|
||||
{
|
||||
int x;
|
||||
uint8_t dat;
|
||||
@ -310,7 +310,7 @@ void fm7_state::fm7_alu_function_xor(uint32_t offset)
|
||||
uint8_t mask;
|
||||
|
||||
if(m_alu.command & 0x40)
|
||||
fm7_alu_function_compare(offset);
|
||||
alu_function_compare(offset);
|
||||
|
||||
if(offset >= 0xc000)
|
||||
{
|
||||
@ -336,12 +336,12 @@ void fm7_state::fm7_alu_function_xor(uint32_t offset)
|
||||
dat &= ~m_alu.mask;
|
||||
dat |= mask;
|
||||
|
||||
fm7_alu_mask_write(offset,x,dat);
|
||||
alu_mask_write(offset,x,dat);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function_not(uint32_t offset)
|
||||
void fm77_state::alu_function_not(uint32_t offset)
|
||||
{
|
||||
int x;
|
||||
uint8_t dat;
|
||||
@ -349,7 +349,7 @@ void fm7_state::fm7_alu_function_not(uint32_t offset)
|
||||
uint8_t mask;
|
||||
|
||||
if(m_alu.command & 0x40)
|
||||
fm7_alu_function_compare(offset);
|
||||
alu_function_compare(offset);
|
||||
|
||||
if(offset >= 0xc000)
|
||||
{
|
||||
@ -375,12 +375,12 @@ void fm7_state::fm7_alu_function_not(uint32_t offset)
|
||||
dat &= ~m_alu.mask;
|
||||
dat |= mask;
|
||||
|
||||
fm7_alu_mask_write(offset,x,dat);
|
||||
alu_mask_write(offset,x,dat);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function_invalid(uint32_t offset)
|
||||
void fm77_state::alu_function_invalid(uint32_t offset)
|
||||
{
|
||||
// Invalid function, still does something though (used by Laydock)
|
||||
int x;
|
||||
@ -389,7 +389,7 @@ void fm7_state::fm7_alu_function_invalid(uint32_t offset)
|
||||
uint8_t mask;
|
||||
|
||||
if(m_alu.command & 0x40)
|
||||
fm7_alu_function_compare(offset);
|
||||
alu_function_compare(offset);
|
||||
|
||||
if(offset >= 0xc000)
|
||||
{
|
||||
@ -407,12 +407,12 @@ void fm7_state::fm7_alu_function_invalid(uint32_t offset)
|
||||
|
||||
dat = mask & m_alu.mask;
|
||||
|
||||
fm7_alu_mask_write(offset,x,dat);
|
||||
alu_mask_write(offset,x,dat);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function_tilepaint(uint32_t offset)
|
||||
void fm77_state::alu_function_tilepaint(uint32_t offset)
|
||||
{
|
||||
// TILEPAINT - writes to VRAM based on the tilepaint colour registers
|
||||
int x;
|
||||
@ -421,7 +421,7 @@ void fm7_state::fm7_alu_function_tilepaint(uint32_t offset)
|
||||
uint8_t mask;
|
||||
|
||||
if(m_alu.command & 0x40)
|
||||
fm7_alu_function_compare(offset);
|
||||
alu_function_compare(offset);
|
||||
|
||||
if(offset >= 0xc000)
|
||||
{
|
||||
@ -451,43 +451,43 @@ void fm7_state::fm7_alu_function_tilepaint(uint32_t offset)
|
||||
mask = (m_video_ram[(offset & 0x3fff) + (x * 0x4000) + (page * 0xc000)]) & m_alu.mask;
|
||||
dat |= mask;
|
||||
|
||||
fm7_alu_mask_write(offset,x,dat);
|
||||
alu_mask_write(offset,x,dat);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm7_alu_function(uint32_t offset)
|
||||
void fm77_state::fm7_alu_function(uint32_t offset)
|
||||
{
|
||||
switch(m_alu.command & 0x07)
|
||||
{
|
||||
case 0x00: // PSET
|
||||
fm7_alu_function_pset(offset);
|
||||
alu_function_pset(offset);
|
||||
break;
|
||||
case 0x02: // OR
|
||||
fm7_alu_function_or(offset);
|
||||
alu_function_or(offset);
|
||||
break;
|
||||
case 0x03: // AND
|
||||
fm7_alu_function_and(offset);
|
||||
alu_function_and(offset);
|
||||
break;
|
||||
case 0x04: // XOR
|
||||
fm7_alu_function_xor(offset);
|
||||
alu_function_xor(offset);
|
||||
break;
|
||||
case 0x05: // NOT
|
||||
fm7_alu_function_not(offset);
|
||||
alu_function_not(offset);
|
||||
break;
|
||||
case 0x06: // TILEPAINT
|
||||
fm7_alu_function_tilepaint(offset);
|
||||
alu_function_tilepaint(offset);
|
||||
break;
|
||||
case 0x07: // COMPARE
|
||||
fm7_alu_function_compare(offset);
|
||||
alu_function_compare(offset);
|
||||
break;
|
||||
case 0x01:
|
||||
default:
|
||||
fm7_alu_function_invalid(offset);
|
||||
alu_function_invalid(offset);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t fm7_state::fm7_line_set_pixel(int x, int y)
|
||||
uint32_t fm77_state::av_line_set_pixel(int x, int y)
|
||||
{
|
||||
uint32_t addr;
|
||||
static const uint8_t pixel_mask[8] = {0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0xfe };
|
||||
@ -515,7 +515,7 @@ uint32_t fm7_state::fm7_line_set_pixel(int x, int y)
|
||||
return addr;
|
||||
}
|
||||
|
||||
void fm7_state::fm77av_line_draw()
|
||||
void fm77_state::av_line_draw()
|
||||
{
|
||||
int x1 = m_alu.x0;
|
||||
int x2 = m_alu.x1;
|
||||
@ -541,7 +541,7 @@ void fm7_state::fm77av_line_draw()
|
||||
|
||||
for(;;)
|
||||
{
|
||||
fm7_line_set_pixel(x1, y1);
|
||||
av_line_set_pixel(x1, y1);
|
||||
byte_count++;
|
||||
|
||||
if(x1 == x2 && y1 == y2)
|
||||
@ -565,7 +565,7 @@ void fm7_state::fm77av_line_draw()
|
||||
timer_set(attotime::from_usec(byte_count/16), TIMER_FM77AV_ALU_TASK_END);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram_r(offs_t offset)
|
||||
uint8_t fm7_state::vram_r(offs_t offset)
|
||||
{
|
||||
int offs;
|
||||
uint16_t page = 0x0000;
|
||||
@ -602,7 +602,7 @@ uint8_t fm7_state::fm7_vram_r(offs_t offset)
|
||||
return m_video_ram[offs + page];
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram_w(offs_t offset, uint8_t data)
|
||||
void fm7_state::vram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
int offs;
|
||||
uint16_t page = 0x0000;
|
||||
@ -642,7 +642,7 @@ void fm7_state::fm7_vram_w(offs_t offset, uint8_t data)
|
||||
}
|
||||
|
||||
// not pretty, but it should work.
|
||||
void fm7_state::fm7_vram_banked_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram_banked_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
int offs;
|
||||
uint16_t page = 0x0000;
|
||||
@ -683,148 +683,148 @@ void fm7_state::fm7_vram_banked_w(offs_t offset, uint8_t data)
|
||||
m_video_ram[offs+page] = data;
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram0_r(offs_t offset)
|
||||
uint8_t fm77_state::vram0_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset);
|
||||
return vram_r(offset);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram1_r(offs_t offset)
|
||||
uint8_t fm77_state::vram1_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x1000);
|
||||
return vram_r(offset+0x1000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram2_r(offs_t offset)
|
||||
uint8_t fm77_state::vram2_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x2000);
|
||||
return vram_r(offset+0x2000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram3_r(offs_t offset)
|
||||
uint8_t fm77_state::vram3_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x3000);
|
||||
return vram_r(offset+0x3000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram4_r(offs_t offset)
|
||||
uint8_t fm77_state::vram4_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x4000);
|
||||
return vram_r(offset+0x4000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram5_r(offs_t offset)
|
||||
uint8_t fm77_state::vram5_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x5000);
|
||||
return vram_r(offset+0x5000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram6_r(offs_t offset)
|
||||
uint8_t fm77_state::vram6_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x6000);
|
||||
return vram_r(offset+0x6000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram7_r(offs_t offset)
|
||||
uint8_t fm77_state::vram7_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x7000);
|
||||
return vram_r(offset+0x7000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram8_r(offs_t offset)
|
||||
uint8_t fm77_state::vram8_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x8000);
|
||||
return vram_r(offset+0x8000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vram9_r(offs_t offset)
|
||||
uint8_t fm77_state::vram9_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0x9000);
|
||||
return vram_r(offset+0x9000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vramA_r(offs_t offset)
|
||||
uint8_t fm77_state::vramA_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0xa000);
|
||||
return vram_r(offset+0xa000);
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_vramB_r(offs_t offset)
|
||||
uint8_t fm77_state::vramB_r(offs_t offset)
|
||||
{
|
||||
if(!m_video.sub_halt) // no access if sub CPU is not halted.
|
||||
return 0xff;
|
||||
return fm7_vram_r(offset+0xb000);
|
||||
return vram_r(offset+0xb000);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram0_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram0_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset,data);
|
||||
vram_banked_w(offset,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram1_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram1_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x1000,data);
|
||||
vram_banked_w(offset+0x1000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram2_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram2_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x2000,data);
|
||||
vram_banked_w(offset+0x2000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram3_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram3_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x3000,data);
|
||||
vram_banked_w(offset+0x3000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram4_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram4_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x4000,data);
|
||||
vram_banked_w(offset+0x4000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram5_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram5_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x5000,data);
|
||||
vram_banked_w(offset+0x5000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram6_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram6_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x6000,data);
|
||||
vram_banked_w(offset+0x6000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram7_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram7_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x7000,data);
|
||||
vram_banked_w(offset+0x7000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram8_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram8_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x8000,data);
|
||||
vram_banked_w(offset+0x8000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vram9_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vram9_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0x9000,data);
|
||||
vram_banked_w(offset+0x9000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vramA_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vramA_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0xa000,data);
|
||||
vram_banked_w(offset+0xa000,data);
|
||||
}
|
||||
|
||||
void fm7_state::fm7_vramB_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::vramB_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
fm7_vram_banked_w(offset+0xb000,data);
|
||||
vram_banked_w(offset+0xb000,data);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -833,13 +833,13 @@ void fm7_state::fm7_vramB_w(offs_t offset, uint8_t data)
|
||||
* On read, enables the CRT display
|
||||
* On write, disables the CRT display
|
||||
*/
|
||||
uint8_t fm7_state::fm7_crt_r()
|
||||
uint8_t fm7_state::crt_r()
|
||||
{
|
||||
m_video.crt_enable = 1;
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
void fm7_state::fm7_crt_w(uint8_t data)
|
||||
void fm7_state::crt_w(uint8_t data)
|
||||
{
|
||||
m_video.crt_enable = 0;
|
||||
}
|
||||
@ -850,7 +850,7 @@ void fm7_state::fm7_crt_w(uint8_t data)
|
||||
* 0xd40e: bits 0-6 - offset in bytes (high byte) (bit 6 is used for 400 line video only)
|
||||
* 0xd40f: bits 0-7 - offset in bytes (low byte)
|
||||
*/
|
||||
void fm7_state::fm7_vram_offset_w(offs_t offset, uint8_t data)
|
||||
void fm7_state::vram_offset_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
uint16_t new_offset = 0;
|
||||
|
||||
@ -898,7 +898,7 @@ void fm7_state::fm7_vram_offset_w(offs_t offset, uint8_t data)
|
||||
* bits 6-4: VRAM planes to display (G,R,B) (1=disable)
|
||||
* bits 2-0: VRAM CPU access (G,R,B) (1=disable)
|
||||
*/
|
||||
void fm7_state::fm7_multipage_w(uint8_t data)
|
||||
void fm7_state::multipage_w(uint8_t data)
|
||||
{
|
||||
m_video.multi_page = data & 0x77;
|
||||
}
|
||||
@ -911,12 +911,12 @@ void fm7_state::fm7_multipage_w(uint8_t data)
|
||||
* bit 1 = Red
|
||||
* bit 0 = Blue
|
||||
*/
|
||||
uint8_t fm7_state::fm7_palette_r(offs_t offset)
|
||||
uint8_t fm7_state::palette_r(offs_t offset)
|
||||
{
|
||||
return m_video.fm7_pal[offset];
|
||||
}
|
||||
|
||||
void fm7_state::fm7_palette_w(offs_t offset, uint8_t data)
|
||||
void fm7_state::palette_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_palette->set_pen_color(offset, rgb_t(pal1bit(data >> 1), pal1bit(data >> 2), pal1bit(data >> 0)));
|
||||
m_video.fm7_pal[offset] = data & 0x07;
|
||||
@ -933,7 +933,7 @@ void fm7_state::fm7_palette_w(offs_t offset, uint8_t data)
|
||||
* fd33: red level (4 bits)
|
||||
* fd34: green level (4 bits)
|
||||
*/
|
||||
void fm7_state::fm77av_analog_palette_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::av_analog_palette_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
int val;
|
||||
|
||||
@ -974,7 +974,7 @@ void fm7_state::fm77av_analog_palette_w(offs_t offset, uint8_t data)
|
||||
* bit 6 - display VRAM page
|
||||
* bit 7 - NMI mask register (1=mask)
|
||||
*/
|
||||
uint8_t fm7_state::fm77av_video_flags_r()
|
||||
uint8_t fm77_state::av_video_flags_r()
|
||||
{
|
||||
uint8_t ret = 0xff;
|
||||
|
||||
@ -993,7 +993,7 @@ uint8_t fm7_state::fm77av_video_flags_r()
|
||||
return ret;
|
||||
}
|
||||
|
||||
void fm7_state::fm77av_video_flags_w(uint8_t data)
|
||||
void fm77_state::av_video_flags_w(uint8_t data)
|
||||
{
|
||||
uint8_t* RAM = memregion("subsyscg")->base();
|
||||
|
||||
@ -1012,7 +1012,7 @@ void fm7_state::fm77av_video_flags_w(uint8_t data)
|
||||
* bit 1 (R/O) - DISPTMG status (0=blank)
|
||||
* bit 0 (R/O) - VSync status (1=sync?)
|
||||
*/
|
||||
uint8_t fm7_state::fm77av_sub_modestatus_r()
|
||||
uint8_t fm77_state::av_sub_modestatus_r()
|
||||
{
|
||||
uint8_t ret = 0x00;
|
||||
|
||||
@ -1028,7 +1028,7 @@ uint8_t fm7_state::fm77av_sub_modestatus_r()
|
||||
return ret;
|
||||
}
|
||||
|
||||
void fm7_state::fm77av_sub_modestatus_w(uint8_t data)
|
||||
void fm77_state::av_sub_modestatus_w(uint8_t data)
|
||||
{
|
||||
m_video.modestatus = data & 0x40;
|
||||
if(data & 0x40)
|
||||
@ -1050,7 +1050,7 @@ void fm7_state::fm77av_sub_modestatus_w(uint8_t data)
|
||||
* bits 1 and 0 select which subsys ROM to be banked into sub CPU space
|
||||
* on the FM-77AV40 and later, bit 2 can also selected to bank in sub monitor RAM.
|
||||
*/
|
||||
void fm7_state::fm77av_sub_bank_w(uint8_t data)
|
||||
void fm77_state::av_sub_bank_w(uint8_t data)
|
||||
{
|
||||
// uint8_t* RAM = memregion("sub")->base();
|
||||
uint8_t* ROM;
|
||||
@ -1122,7 +1122,7 @@ void fm7_state::fm77av_sub_bank_w(uint8_t data)
|
||||
* 0xd428-29(W): Line X1 (High-Low, X9-X0)
|
||||
* 0xd42a-2b(W): Line Y1 (High-Low, Y8-Y0)
|
||||
*/
|
||||
uint8_t fm7_state::fm77av_alu_r(offs_t offset)
|
||||
uint8_t fm77_state::av_alu_r(offs_t offset)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -1147,7 +1147,7 @@ uint8_t fm7_state::fm77av_alu_r(offs_t offset)
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm77av_alu_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::av_alu_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
uint16_t dat;
|
||||
|
||||
@ -1251,7 +1251,7 @@ void fm7_state::fm77av_alu_w(offs_t offset, uint8_t data)
|
||||
dat = (m_alu.y1 & 0xff00) | data;
|
||||
m_alu.y1 = dat;
|
||||
// draw line
|
||||
fm77av_line_draw();
|
||||
av_line_draw();
|
||||
// logerror("ALU: write to Y1 (low) register - %02x (%04x)\n",data,m_alu.y1);
|
||||
break;
|
||||
default:
|
||||
@ -1259,24 +1259,24 @@ void fm7_state::fm77av_alu_w(offs_t offset, uint8_t data)
|
||||
}
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(fm7_state::fm77av_vsync)
|
||||
TIMER_CALLBACK_MEMBER(fm77_state::av_vsync)
|
||||
{
|
||||
if(param == 0) // start of vsync
|
||||
{
|
||||
m_video.vsync_flag = 1;
|
||||
m_fm77av_vsync_timer->adjust(attotime::from_usec(510),1); // VSync length for 200 line modes = 0.51ms
|
||||
m_vsync_timer->adjust(attotime::from_usec(510),1); // VSync length for 200 line modes = 0.51ms
|
||||
}
|
||||
else
|
||||
{
|
||||
m_video.vsync_flag = 0;
|
||||
m_fm77av_vsync_timer->adjust(m_screen->time_until_vblank_end());
|
||||
m_vsync_timer->adjust(m_screen->time_until_vblank_end());
|
||||
}
|
||||
}
|
||||
|
||||
// called when banked into main CPU space by the MMR, available only if sub CPU is halted
|
||||
uint8_t fm7_state::fm7_sub_ram_ports_banked_r(offs_t offset)
|
||||
uint8_t fm77_state::sub_ram_ports_banked_r(offs_t offset)
|
||||
{
|
||||
uint8_t* RAM = memregion("maincpu")->base();
|
||||
uint8_t* RAM = m_ram_ptr.target();
|
||||
uint8_t* ROM;
|
||||
|
||||
if(!m_video.sub_halt)
|
||||
@ -1295,39 +1295,39 @@ uint8_t fm7_state::fm7_sub_ram_ports_banked_r(offs_t offset)
|
||||
}
|
||||
|
||||
if(offset >= 0x410 && offset <= 0x42b)
|
||||
return fm77av_alu_r(offset-0x410);
|
||||
return av_alu_r(offset-0x410);
|
||||
|
||||
switch(offset)
|
||||
{
|
||||
case 0x400:
|
||||
case 0x401:
|
||||
return fm7_sub_keyboard_r(offset-0x400);
|
||||
return sub_keyboard_r(offset-0x400);
|
||||
case 0x402:
|
||||
return fm7_cancel_ack();
|
||||
return cancel_ack();
|
||||
case 0x403:
|
||||
return fm7_sub_beeper_r();
|
||||
return sub_beeper_r();
|
||||
case 0x404:
|
||||
return fm7_attn_irq_r();
|
||||
return attn_irq_r();
|
||||
case 0x408:
|
||||
return fm7_crt_r();
|
||||
return crt_r();
|
||||
case 0x409:
|
||||
return fm7_vram_access_r();
|
||||
return vram_access_r();
|
||||
case 0x40a:
|
||||
return fm7_sub_busyflag_r();
|
||||
return sub_busyflag_r();
|
||||
case 0x430:
|
||||
return fm77av_video_flags_r();
|
||||
return av_video_flags_r();
|
||||
case 0x431:
|
||||
case 0x432:
|
||||
return fm77av_key_encoder_r(offset-0x431);
|
||||
return av_key_encoder_r(offset-0x431);
|
||||
default:
|
||||
logerror("Unmapped read from sub CPU port 0xd%03x via MMR banking\n",offset);
|
||||
return 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
void fm7_state::fm7_sub_ram_ports_banked_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::sub_ram_ports_banked_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
uint8_t* RAM = memregion("maincpu")->base();
|
||||
uint8_t* RAM = m_ram_ptr.target();
|
||||
|
||||
if(!m_video.sub_halt)
|
||||
return;
|
||||
@ -1350,40 +1350,40 @@ void fm7_state::fm7_sub_ram_ports_banked_w(offs_t offset, uint8_t data)
|
||||
|
||||
if(offset >= 0x410 && offset <= 0x42b)
|
||||
{
|
||||
fm77av_alu_w(offset-0x410,data);
|
||||
av_alu_w(offset-0x410,data);
|
||||
return;
|
||||
}
|
||||
|
||||
switch(offset)
|
||||
{
|
||||
case 0x408:
|
||||
fm7_crt_w(data);
|
||||
crt_w(data);
|
||||
break;
|
||||
case 0x409:
|
||||
fm7_vram_access_w(data);
|
||||
vram_access_w(data);
|
||||
break;
|
||||
case 0x40a:
|
||||
fm7_sub_busyflag_w(data);
|
||||
sub_busyflag_w(data);
|
||||
break;
|
||||
case 0x40e:
|
||||
case 0x40f:
|
||||
fm7_vram_offset_w(offset-0x40e,data);
|
||||
vram_offset_w(offset-0x40e,data);
|
||||
break;
|
||||
case 0x430:
|
||||
fm77av_video_flags_w(data);
|
||||
av_video_flags_w(data);
|
||||
break;
|
||||
case 0x431:
|
||||
case 0x432:
|
||||
fm77av_key_encoder_w(offset-0x431,data);
|
||||
av_key_encoder_w(offset-0x431,data);
|
||||
break;
|
||||
default:
|
||||
logerror("Unmapped write of 0x%02x to sub CPU port 0xd%03x via MMR banking\n",data,offset);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t fm7_state::fm7_console_ram_banked_r(offs_t offset)
|
||||
uint8_t fm77_state::console_ram_banked_r(offs_t offset)
|
||||
{
|
||||
uint8_t* RAM = memregion("maincpu")->base();
|
||||
uint8_t* RAM = m_ram_ptr.target();
|
||||
|
||||
if(!m_video.sub_halt)
|
||||
return 0xff;
|
||||
@ -1391,9 +1391,9 @@ uint8_t fm7_state::fm7_console_ram_banked_r(offs_t offset)
|
||||
return RAM[0x1c000+offset];
|
||||
}
|
||||
|
||||
void fm7_state::fm7_console_ram_banked_w(offs_t offset, uint8_t data)
|
||||
void fm77_state::console_ram_banked_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
uint8_t* RAM = memregion("maincpu")->base();
|
||||
uint8_t* RAM = m_ram_ptr.target();
|
||||
|
||||
if(!m_video.sub_halt)
|
||||
return;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user