mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
am9517a: Updates
- Store actual line state in status register, correcting to logical state when used
- Revert previous change that corrupted DREQ input state when the mask register was written to (3b15113002)
- Add configuration methods to define initial state for DREQ inputs being active low (or high)
- Add a few more internal helper functions
- Disable side effects of reads for debugging
This commit is contained in:
AJR
parent
e1652298a5
commit
43e25e6168
@ -145,29 +145,53 @@ enum
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// dma_request -
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//-------------------------------------------------
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void am9517a_device::dma_request(int channel, int state)
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void am9517a_device::dma_request(int channel, bool state)
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{
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LOG("AM9517A Channel %u DMA Request: %u\n", channel, state);
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if (state ^ COMMAND_DREQ_ACTIVE_LOW)
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{
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if (state)
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m_status |= (1 << (channel + 4));
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}
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else
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{
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m_status &= ~(1 << (channel + 4));
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}
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trigger(1);
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}
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//-------------------------------------------------
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// mask_channel -
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//-------------------------------------------------
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void am9517a_device::mask_channel(int channel, bool state)
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{
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LOG("AM9517A Channel %u Mask: %u\n", channel, state);
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if (state)
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m_mask |= 1 << channel;
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else
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m_mask &= ~(1 << channel);
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}
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//-------------------------------------------------
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// set_mask_register -
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//-------------------------------------------------
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void am9517a_device::set_mask_register(uint8_t mask)
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{
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LOG("AM9517A Mask Register: %01x\n", mask);
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m_mask = mask;
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}
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//-------------------------------------------------
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// is_request_active -
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//-------------------------------------------------
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inline bool am9517a_device::is_request_active(int channel)
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{
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return (BIT(m_status, channel + 4) & ~BIT(m_mask, channel)) ? true : false;
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return (BIT(COMMAND_DREQ_ACTIVE_LOW ? ~m_status : m_status, channel + 4) && !BIT(m_mask, channel)) ? true : false;
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}
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@ -424,6 +448,7 @@ am9517a_device::am9517a_device(const machine_config &mconfig, device_type type,
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m_hack(0),
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m_ready(1),
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m_command(0),
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m_status(0),
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m_out_hreq_cb(*this),
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m_out_eop_cb(*this),
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m_in_memr_cb(*this),
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@ -518,7 +543,7 @@ void am9517a_device::device_reset()
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{
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m_state = STATE_SI;
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m_command = 0;
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m_status = 0;
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m_status &= 0xf0;
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m_request = 0;
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m_mask = 0x0f;
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m_temp = 0;
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@ -765,7 +790,8 @@ uint8_t am9517a_device::read(offs_t offset)
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break;
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}
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m_msb = !m_msb;
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if (!machine().side_effects_disabled())
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m_msb = !m_msb;
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}
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else
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{
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@ -773,9 +799,12 @@ uint8_t am9517a_device::read(offs_t offset)
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{
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case REGISTER_STATUS:
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data = m_status;
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if (COMMAND_DREQ_ACTIVE_LOW)
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data ^= 0xf0;
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// clear TC bits
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m_status &= 0xf0;
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if (!machine().side_effects_disabled())
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m_status &= 0xf0;
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break;
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case REGISTER_TEMPORARY:
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@ -867,17 +896,7 @@ void am9517a_device::write(offs_t offset, uint8_t data)
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case REGISTER_SINGLE_MASK:
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{
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int channel = data & 0x03;
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if (BIT(data, 2))
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{
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m_mask |= (1 << channel);
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}
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else
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{
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m_mask &= ~(1 << channel);
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}
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LOG("AM9517A Mask Register: %01x\n", m_mask);
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mask_channel(channel, BIT(data, 2));
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}
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break;
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@ -907,18 +926,11 @@ void am9517a_device::write(offs_t offset, uint8_t data)
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break;
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case REGISTER_CLEAR_MASK:
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LOG("AM9517A Clear Mask Register\n");
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m_mask = 0;
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set_mask_register(0);
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break;
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case REGISTER_MASK:
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m_mask = data & 0x0f;
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LOG("AM9517A Mask Register: %01x\n", m_mask);
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// tek4132 firmware indicates setting mask bits also sets status
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m_status |= (data & 0x0f) << 4;
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set_mask_register(data & 0x0f);
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break;
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}
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}
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@ -1093,7 +1105,8 @@ uint8_t v5x_dmau_device::read(offs_t offset)
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case 0x0b: // Status
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ret = m_status;
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// clear TC bits
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m_status &= 0xf0;
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if (!machine().side_effects_disabled())
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m_status &= 0xf0;
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break;
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case 0x0c: // Temporary (low)
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ret = m_temp & 0xff;
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@ -1266,7 +1279,7 @@ void pcxport_dmac_device::device_reset()
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{
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m_state = STATE_SI;
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m_command = 0;
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m_status = 0;
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m_status &= 0xf0;
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m_request = 0;
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m_mask = 0;
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m_temp = 0;
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@ -61,6 +61,10 @@ public:
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template <unsigned C> auto out_iow_callback() { return m_out_iow_cb[C].bind(); }
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template <unsigned C> auto out_dack_callback() { return m_out_dack_cb[C].bind(); }
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// define initial (inactive) state of DREQ inputs
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void dreq_active_low() { assert(!configured()); m_status = 0xf0; }
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void dreq_active_high() { assert(!configured()); m_status = 0; }
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virtual uint8_t read(offs_t offset);
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virtual void write(offs_t offset, uint8_t data);
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@ -116,7 +120,9 @@ protected:
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uint8_t m_request;
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private:
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void dma_request(int channel, int state);
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void dma_request(int channel, bool state);
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void mask_channel(int channel, bool state);
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void set_mask_register(uint8_t mask);
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inline bool is_request_active(int channel);
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inline bool is_software_request_active(int channel);
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inline void set_hreq(int state);
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@ -2178,6 +2178,7 @@ void pc9801_state::pc9801_common(machine_config &config)
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m_pit->out_handler<2>().append(m_sio, FUNC(i8251_device::write_rxc));
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AM9517A(config, m_dmac, 5000000); // unknown clock, TODO: check channels 0 - 1
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m_dmac->dreq_active_low();
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m_dmac->out_hreq_callback().set(FUNC(pc9801_state::dma_hrq_changed));
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m_dmac->out_eop_callback().set(FUNC(pc9801_state::tc_w));
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m_dmac->in_memr_callback().set(FUNC(pc9801_state::dma_read_byte));
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@ -908,6 +908,7 @@ void qx10_state::qx10(machine_config &config)
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m_scc->out_int_callback().set(FUNC(qx10_state::keyboard_irq));
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AM9517A(config, m_dma_1, MAIN_CLK/4);
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m_dma_1->dreq_active_low();
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m_dma_1->out_hreq_callback().set(FUNC(qx10_state::dma_hrq_changed));
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m_dma_1->out_eop_callback().set(FUNC(qx10_state::tc_w));
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m_dma_1->in_memr_callback().set(FUNC(qx10_state::memory_read_byte));
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@ -916,7 +917,9 @@ void qx10_state::qx10(machine_config &config)
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m_dma_1->in_ior_callback<1>().set(m_hgdc, FUNC(upd7220_device::dack_r));
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m_dma_1->out_iow_callback<0>().set(m_fdc, FUNC(upd765a_device::dma_w));
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m_dma_1->out_iow_callback<1>().set(m_hgdc, FUNC(upd7220_device::dack_w));
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AM9517A(config, m_dma_2, MAIN_CLK/4);
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m_dma_2->dreq_active_low();
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I8255(config, m_ppi, 0);
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m_ppi->out_pa_callback().set("prndata", FUNC(output_latch_device::write));
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@ -873,6 +873,7 @@ void tek4132_state::tek4132(machine_config &config)
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m_nov[1]->do_callback().set(FUNC(tek4132_state::nov_do));
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AM9517A(config, m_sdma, 4'000'000); // clock?
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m_sdma->dreq_active_low();
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INPUT_MERGER_ALL_HIGH(config, m_sirq);
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//m_sirq->output_handler().set(m_icu, FUNC(ns32202_device::ir_w<4>));
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