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chihiro: few updates to the i386 processor and chihiro driver. [Samuele Zannoli]

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- adds lots of mmx and sse opcodes to the i386 processor
 - adds the fcomip x87 opcode
 - adds a "UINT8 *memory(UINT32 &size)" method to the naomi_gdrom_board device that returns the size and a pointer to the decrypted gdrom data (used by chihiro)
Then for the chihiro driver:
 - adds basic stuff for the Nvidia audio APU
 - adds the "chihiro curthread" debugger command, shows information about the current active thread
 - adds the "chihiro irq,<number>" debugger command, to generate an interrupt with irq number 0-15 by hand
 - adds more patches to let the software run even if usb is not implemented
 - adds the Chihiro Type 1 baseboard/mediaboard features to let the system load the gdrom games
 - adds incomplete save state support
 - adds support to the Nvidia 3d accelerator to draw primitives where the vertex data is not stored in a vertex buffer but contained in the command stream

i386: don't take an smi until current instruction is complete (nw)
This commit is contained in:
cracyc 2013-06-23 22:08:50 +00:00
parent 2cf44e5036
commit 4416165874
7 changed files with 4377 additions and 315 deletions
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29
src/emu/cpu/i386/i386.c
View File

@ -31,6 +31,7 @@ MODRM_TABLE i386_MODRM_table[256];
static void i386_trap_with_error(i386_state* cpustate, int irq, int irq_gate, int trap_level, UINT32 err);
static void i286_task_switch(i386_state* cpustate, UINT16 selector, UINT8 nested);
static void i386_task_switch(i386_state* cpustate, UINT16 selector, UINT8 nested);
static void pentium_smi(i386_state* cpustate);
#define FAULT(fault,error) {cpustate->ext = 1; i386_trap_with_error(cpustate,fault,0,0,error); return;}
#define FAULT_EXP(fault,error) {cpustate->ext = 1; i386_trap_with_error(cpustate,fault,0,trap_level+1,error); return;}
@ -1224,6 +1225,12 @@ static void i386_task_switch(i386_state *cpustate, UINT16 selector, UINT8 nested
static void i386_check_irq_line(i386_state *cpustate)
{
if(!cpustate->smm && cpustate->smi)
{
pentium_smi(cpustate);
return;
}
/* Check if the interrupts are enabled */
if ( (cpustate->irq_state) && cpustate->IF )
{
@ -2987,6 +2994,8 @@ static void i386_common_init(legacy_cpu_device *device, device_irq_acknowledge_c
static const int regs32[8] = {EAX,ECX,EDX,EBX,ESP,EBP,ESI,EDI};
i386_state *cpustate = get_safe_token(device);
assert((sizeof(XMM_REG)/sizeof(double)) == 2);
build_cycle_table(device->machine());
for( i=0; i < 256; i++ ) {
@ -3014,6 +3023,7 @@ static void i386_common_init(legacy_cpu_device *device, device_irq_acknowledge_c
cpustate->direct = &cpustate->program->direct();
cpustate->io = &device->space(AS_IO);
cpustate->vtlb = vtlb_alloc(device, AS_PROGRAM, 0, tlbsize);
cpustate->smi = false;
device->save_item(NAME( cpustate->reg.d));
device->save_item(NAME(cpustate->sreg[ES].selector));
@ -3070,6 +3080,8 @@ static void i386_common_init(legacy_cpu_device *device, device_irq_acknowledge_c
device->save_item(NAME(cpustate->performed_intersegment_jump));
device->save_item(NAME(cpustate->mxcsr));
device->save_item(NAME(cpustate->smm));
device->save_item(NAME(cpustate->smi_latched));
device->save_item(NAME(cpustate->smi));
device->save_item(NAME(cpustate->nmi_masked));
device->save_item(NAME(cpustate->nmi_latched));
device->save_item(NAME(cpustate->smbase));
@ -3171,6 +3183,7 @@ static CPU_RESET( i386 )
cpustate->idtr.base = 0;
cpustate->idtr.limit = 0x3ff;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;
@ -3204,13 +3217,14 @@ static void pentium_smi(i386_state *cpustate)
UINT32 old_flags = get_flags(cpustate);
if(cpustate->smm)
return; // TODO: latch
return;
cpustate->cr[0] &= ~(0x8000000d);
set_flags(cpustate, 2);
if(!cpustate->smiact.isnull())
cpustate->smiact(true);
cpustate->smm = true;
cpustate->smi_latched = false;
// save state
WRITE32(cpustate, cpustate->cr[4], smram_state+SMRAM_IP5_CR4);
@ -3777,6 +3791,7 @@ static CPU_RESET( i486 )
cpustate->eflags_mask = 0x00077fd7;
cpustate->eip = 0xfff0;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;
@ -3892,6 +3907,7 @@ static CPU_RESET( pentium )
cpustate->eip = 0xfff0;
cpustate->mxcsr = 0x1f80;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->smbase = 0x30000;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;
@ -3938,8 +3954,9 @@ static CPU_SET_INFO( pentium )
switch (state)
{
case CPUINFO_INT_INPUT_STATE+INPUT_LINE_SMI:
if(state)
pentium_smi(cpustate);
if(!cpustate->smi && state && cpustate->smm)
cpustate->smi_latched = true;
cpustate->smi = state;
break;
case CPUINFO_INT_REGISTER + X87_CTRL: cpustate->x87_cw = info->i; break;
case CPUINFO_INT_REGISTER + X87_STATUS: cpustate->x87_sw = info->i; break;
@ -4026,6 +4043,7 @@ static CPU_RESET( mediagx )
cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
cpustate->eip = 0xfff0;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;
@ -4149,6 +4167,7 @@ static CPU_RESET( pentium_pro )
cpustate->eip = 0xfff0;
cpustate->mxcsr = 0x1f80;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->smbase = 0x30000;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;
@ -4253,6 +4272,7 @@ static CPU_RESET( pentium_mmx )
cpustate->eip = 0xfff0;
cpustate->mxcsr = 0x1f80;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->smbase = 0x30000;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;
@ -4357,6 +4377,7 @@ static CPU_RESET( pentium2 )
cpustate->eip = 0xfff0;
cpustate->mxcsr = 0x1f80;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->smbase = 0x30000;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;
@ -4461,6 +4482,7 @@ static CPU_RESET( pentium3 )
cpustate->eip = 0xfff0;
cpustate->mxcsr = 0x1f80;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->smbase = 0x30000;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;
@ -4567,6 +4589,7 @@ static CPU_RESET( pentium4 )
cpustate->eip = 0xfff0;
cpustate->mxcsr = 0x1f80;
cpustate->smm = false;
cpustate->smi_latched = false;
cpustate->smbase = 0x30000;
cpustate->nmi_masked = false;
cpustate->nmi_latched = false;

144
src/emu/cpu/i386/i386ops.h
View File

@ -298,6 +298,15 @@ static const X86_OPCODE x86_opcode_table[] =
{ 0x08, OP_2BYTE|OP_I486, I486OP(invd), I486OP(invd), },
{ 0x09, OP_2BYTE|OP_I486, I486OP(wbinvd), I486OP(wbinvd), },
{ 0x0B, OP_2BYTE|OP_PENTIUM, PENTIUMOP(ud2), PENTIUMOP(ud2), },
{ 0x10, OP_2BYTE|OP_SSE, SSEOP(movups_r128_rm128), SSEOP(movups_r128_rm128), },
{ 0x11, OP_2BYTE|OP_SSE, SSEOP(movups_rm128_r128), SSEOP(movups_rm128_r128), },
{ 0x12, OP_2BYTE|OP_SSE, SSEOP(movlps_r128_m64), SSEOP(movlps_r128_m64), },
{ 0x13, OP_2BYTE|OP_SSE, SSEOP(movlps_m64_r128), SSEOP(movlps_m64_r128), },
{ 0x14, OP_2BYTE|OP_SSE, SSEOP(unpcklps_r128_rm128), SSEOP(unpcklps_r128_rm128), },
{ 0x15, OP_2BYTE|OP_SSE, SSEOP(unpckhps_r128_rm128), SSEOP(unpckhps_r128_rm128), },
{ 0x16, OP_2BYTE|OP_SSE, SSEOP(movhps_r128_m64), SSEOP(movhps_r128_m64), },
{ 0x17, OP_2BYTE|OP_SSE, SSEOP(movhps_m64_r128), SSEOP(movhps_m64_r128), },
{ 0x18, OP_2BYTE|OP_PENTIUM, PENTIUMOP(prefetch_m8), PENTIUMOP(prefetch_m8), },
{ 0x20, OP_2BYTE|OP_I386, I386OP(mov_r32_cr), I386OP(mov_r32_cr), },
{ 0x21, OP_2BYTE|OP_I386, I386OP(mov_r32_dr), I386OP(mov_r32_dr), },
{ 0x22, OP_2BYTE|OP_I386, I386OP(mov_cr_r32), I386OP(mov_cr_r32), },
@ -307,13 +316,72 @@ static const X86_OPCODE x86_opcode_table[] =
{ 0x26, OP_2BYTE|OP_I386, I386OP(mov_tr_r32), I386OP(mov_tr_r32), },
{ 0x28, OP_2BYTE|OP_SSE, SSEOP(movaps_r128_rm128), SSEOP(movaps_r128_rm128), },
{ 0x29, OP_2BYTE|OP_SSE, SSEOP(movaps_rm128_r128), SSEOP(movaps_rm128_r128), },
{ 0x2a, OP_2BYTE|OP_SSE, SSEOP(cvtpi2ps_r128_rm64), SSEOP(cvtpi2ps_r128_rm64), },
{ 0x2b, OP_2BYTE|OP_SSE, SSEOP(movntps_m128_r128), SSEOP(movntps_m128_r128), },
{ 0x2c, OP_2BYTE|OP_SSE, SSEOP(cvttps2pi_r64_r128m64), SSEOP(cvttps2pi_r64_r128m64),},
{ 0x2d, OP_2BYTE|OP_SSE, SSEOP(cvtps2pi_r64_r128m64), SSEOP(cvtps2pi_r64_r128m64),},
{ 0x2e, OP_2BYTE|OP_SSE, SSEOP(ucomiss_r128_r128m32), SSEOP(ucomiss_r128_r128m32),},
{ 0x2f, OP_2BYTE|OP_SSE, SSEOP(comiss_r128_r128m32), SSEOP(comiss_r128_r128m32), },
{ 0x30, OP_2BYTE|OP_PENTIUM, PENTIUMOP(wrmsr), PENTIUMOP(wrmsr), },
{ 0x31, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdtsc), PENTIUMOP(rdtsc), },
{ 0x32, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdmsr), PENTIUMOP(rdmsr), },
{ 0x40, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovo_r16_rm16), PENTIUMOP(cmovo_r32_rm32), },
{ 0x41, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovno_r16_rm16), PENTIUMOP(cmovno_r32_rm32), },
{ 0x42, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovb_r16_rm16), PENTIUMOP(cmovb_r32_rm32), },
{ 0x43, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovae_r16_rm16), PENTIUMOP(cmovae_r32_rm32), },
{ 0x44, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmove_r16_rm16), PENTIUMOP(cmove_r32_rm32), },
{ 0x45, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovne_r16_rm16), PENTIUMOP(cmovne_r32_rm32), },
{ 0x46, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovbe_r16_rm16), PENTIUMOP(cmovbe_r32_rm32), },
{ 0x47, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmova_r16_rm16), PENTIUMOP(cmova_r32_rm32), },
{ 0x48, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovs_r16_rm16), PENTIUMOP(cmovs_r32_rm32), },
{ 0x49, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovns_r16_rm16), PENTIUMOP(cmovns_r32_rm32), },
{ 0x4a, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovp_r16_rm16), PENTIUMOP(cmovp_r32_rm32), },
{ 0x4b, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovnp_r16_rm16), PENTIUMOP(cmovnp_r32_rm32), },
{ 0x4c, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovl_r16_rm16), PENTIUMOP(cmovl_r32_rm32), },
{ 0x4d, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovge_r16_rm16), PENTIUMOP(cmovge_r32_rm32), },
{ 0x4e, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovle_r16_rm16), PENTIUMOP(cmovle_r32_rm32), },
{ 0x4f, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovg_r16_rm16), PENTIUMOP(cmovg_r32_rm32), },
{ 0x50, OP_2BYTE|OP_SSE, SSEOP(movmskps_r16_r128), SSEOP(movmskps_r32_r128), },
{ 0x51, OP_2BYTE|OP_SSE, SSEOP(sqrtps_r128_rm128), SSEOP(sqrtps_r128_rm128), },
{ 0x52, OP_2BYTE|OP_SSE, SSEOP(rsqrtps_r128_rm128), SSEOP(rsqrtps_r128_rm128), },
{ 0x53, OP_2BYTE|OP_SSE, SSEOP(rcpps_r128_rm128), SSEOP(rcpps_r128_rm128), },
{ 0x54, OP_2BYTE|OP_SSE, SSEOP(andps_r128_rm128), SSEOP(andps_r128_rm128), },
{ 0x55, OP_2BYTE|OP_SSE, SSEOP(andnps_r128_rm128), SSEOP(andnps_r128_rm128), },
{ 0x56, OP_2BYTE|OP_SSE, SSEOP(orps_r128_rm128), SSEOP(orps_r128_rm128), },
{ 0x57, OP_2BYTE|OP_SSE, SSEOP(xorps), SSEOP(xorps), },
{ 0x58, OP_2BYTE|OP_SSE, SSEOP(addps), SSEOP(addps), },
{ 0x59, OP_2BYTE|OP_SSE, SSEOP(mulps), SSEOP(mulps), },
{ 0x5a, OP_2BYTE|OP_SSE, SSEOP(cvtps2pd_r128_r128m64), SSEOP(cvtps2pd_r128_r128m64),},
{ 0x5b, OP_2BYTE|OP_SSE, SSEOP(cvtdq2ps_r128_rm128), SSEOP(cvtdq2ps_r128_rm128), },
{ 0x5c, OP_2BYTE|OP_SSE, SSEOP(subps), SSEOP(subps), },
{ 0x5d, OP_2BYTE|OP_SSE, SSEOP(minps), SSEOP(minps), },
{ 0x5e, OP_2BYTE|OP_SSE, SSEOP(divps), SSEOP(divps), },
{ 0x5f, OP_2BYTE|OP_SSE, SSEOP(maxps), SSEOP(maxps), },
{ 0x60, OP_2BYTE|OP_MMX, MMXOP(punpcklbw_r64_r64m32), MMXOP(punpcklbw_r64_r64m32),},
{ 0x61, OP_2BYTE|OP_MMX, MMXOP(punpcklwd_r64_r64m32), MMXOP(punpcklwd_r64_r64m32),},
{ 0x62, OP_2BYTE|OP_MMX, MMXOP(punpckldq_r64_r64m32), MMXOP(punpckldq_r64_r64m32),},
{ 0x63, OP_2BYTE|OP_MMX, MMXOP(packsswb_r64_rm64), MMXOP(packsswb_r64_rm64), },
{ 0x64, OP_2BYTE|OP_MMX, MMXOP(pcmpgtb_r64_rm64), MMXOP(pcmpgtb_r64_rm64), },
{ 0x65, OP_2BYTE|OP_MMX, MMXOP(pcmpgtw_r64_rm64), MMXOP(pcmpgtw_r64_rm64), },
{ 0x66, OP_2BYTE|OP_MMX, MMXOP(pcmpgtd_r64_rm64), MMXOP(pcmpgtd_r64_rm64), },
{ 0x67, OP_2BYTE|OP_MMX, MMXOP(packuswb_r64_rm64), MMXOP(packuswb_r64_rm64), },
{ 0x68, OP_2BYTE|OP_MMX, MMXOP(punpckhbw_r64_rm64), MMXOP(punpckhbw_r64_rm64), },
{ 0x69, OP_2BYTE|OP_MMX, MMXOP(punpckhwd_r64_rm64), MMXOP(punpckhwd_r64_rm64), },
{ 0x6a, OP_2BYTE|OP_MMX, MMXOP(punpckhdq_r64_rm64), MMXOP(punpckhdq_r64_rm64), },
{ 0x6b, OP_2BYTE|OP_MMX, MMXOP(packssdw_r64_rm64), MMXOP(packssdw_r64_rm64), },
{ 0x6e, OP_2BYTE|OP_MMX, MMXOP(movd_r64_rm32), MMXOP(movd_r64_rm32), },
{ 0x6f, OP_2BYTE|OP_MMX, MMXOP(movq_r64_rm64), MMXOP(movq_r64_rm64), },
{ 0x70, OP_2BYTE|OP_MMX, MMXOP(pshufw_r64_rm64_i8), MMXOP(pshufw_r64_rm64_i8), },
{ 0x71, OP_2BYTE|OP_MMX, MMXOP(group_0f71), MMXOP(group_0f71), },
{ 0x72, OP_2BYTE|OP_MMX, MMXOP(group_0f72), MMXOP(group_0f72), },
{ 0x73, OP_2BYTE|OP_MMX, MMXOP(group_0f73), MMXOP(group_0f73), },
{ 0x74, OP_2BYTE|OP_CYRIX, I386OP(cyrix_unknown), I386OP(cyrix_unknown), },
{ 0x74, OP_2BYTE|OP_MMX, MMXOP(pcmpeqb_r64_rm64), MMXOP(pcmpeqb_r64_rm64), },
{ 0x75, OP_2BYTE|OP_MMX, MMXOP(pcmpeqw_r64_rm64), MMXOP(pcmpeqw_r64_rm64), },
{ 0x76, OP_2BYTE|OP_MMX, MMXOP(pcmpeqd_r64_rm64), MMXOP(pcmpeqd_r64_rm64), },
{ 0x77, OP_2BYTE|OP_MMX, MMXOP(emms), MMXOP(emms), },
{ 0x7e, OP_2BYTE|OP_MMX, MMXOP(movd_rm32_r64), MMXOP(movd_rm32_r64), },
{ 0x7f, OP_2BYTE|OP_MMX, MMXOP(movq_rm64_r64), MMXOP(movq_rm64_r64), },
{ 0x80, OP_2BYTE|OP_I386, I386OP(jo_rel16), I386OP(jo_rel32), },
{ 0x81, OP_2BYTE|OP_I386, I386OP(jno_rel16), I386OP(jno_rel32), },
{ 0x82, OP_2BYTE|OP_I386, I386OP(jc_rel16), I386OP(jc_rel32), },
@ -376,7 +444,11 @@ static const X86_OPCODE x86_opcode_table[] =
{ 0xBF, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movsx_r32_rm16), },
{ 0xC0, OP_2BYTE|OP_I486, I486OP(xadd_rm8_r8), I486OP(xadd_rm8_r8), },
{ 0xC1, OP_2BYTE|OP_I486, I486OP(xadd_rm16_r16), I486OP(xadd_rm32_r32), },
{ 0xc6, OP_2BYTE|OP_SSE, SSEOP(shufps), SSEOP(shufps), },
{ 0xC2, OP_2BYTE|OP_SSE, SSEOP(cmpps_r128_rm128_i8), SSEOP(cmpps_r128_rm128_i8), },
{ 0xC3, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movnti_m16_r16), PENTIUMOP(movnti_m32_r32), },
{ 0xC4, OP_2BYTE|OP_SSE, SSEOP(pinsrw_r64_r16m16_i8), SSEOP(pinsrw_r64_r32m16_i8),},
{ 0xC5, OP_2BYTE|OP_SSE, SSEOP(pextrw_r16_r64_i8), SSEOP(pextrw_r32_r64_i8), },
{ 0xC6, OP_2BYTE|OP_SSE, SSEOP(shufps), SSEOP(shufps), },
{ 0xC7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmpxchg8b_m64), PENTIUMOP(cmpxchg8b_m64), },
{ 0xC8, OP_2BYTE|OP_I486, I486OP(bswap_eax), I486OP(bswap_eax), },
{ 0xC9, OP_2BYTE|OP_I486, I486OP(bswap_ecx), I486OP(bswap_ecx), },
@ -386,6 +458,74 @@ static const X86_OPCODE x86_opcode_table[] =
{ 0xCD, OP_2BYTE|OP_I486, I486OP(bswap_ebp), I486OP(bswap_ebp), },
{ 0xCE, OP_2BYTE|OP_I486, I486OP(bswap_esi), I486OP(bswap_esi), },
{ 0xCF, OP_2BYTE|OP_I486, I486OP(bswap_edi), I486OP(bswap_edi), },
{ 0xD1, OP_2BYTE|OP_MMX, MMXOP(psrlw_r64_rm64), MMXOP(psrlw_r64_rm64), },
{ 0xD2, OP_2BYTE|OP_MMX, MMXOP(psrld_r64_rm64), MMXOP(psrld_r64_rm64), },
{ 0xD3, OP_2BYTE|OP_MMX, MMXOP(psrlq_r64_rm64), MMXOP(psrlq_r64_rm64), },
{ 0xD4, OP_2BYTE|OP_MMX, MMXOP(paddq_r64_rm64), MMXOP(paddq_r64_rm64), },
{ 0xD5, OP_2BYTE|OP_MMX, MMXOP(pmullw_r64_rm64), MMXOP(pmullw_r64_rm64), },
{ 0xD7, OP_2BYTE|OP_SSE, SSEOP(pmovmskb_r16_r64), SSEOP(pmovmskb_r32_r64), },
{ 0xD8, OP_2BYTE|OP_MMX, MMXOP(psubusb_r64_rm64), MMXOP(psubusb_r64_rm64), },
{ 0xD9, OP_2BYTE|OP_MMX, MMXOP(psubusw_r64_rm64), MMXOP(psubusw_r64_rm64), },
{ 0xDA, OP_2BYTE|OP_SSE, SSEOP(pminub_r64_rm64), SSEOP(pminub_r64_rm64), },
{ 0xDB, OP_2BYTE|OP_MMX, MMXOP(pand_r64_rm64), MMXOP(pand_r64_rm64), },
{ 0xDC, OP_2BYTE|OP_MMX, MMXOP(paddusb_r64_rm64), MMXOP(paddusb_r64_rm64), },
{ 0xDD, OP_2BYTE|OP_MMX, MMXOP(paddusw_r64_rm64), MMXOP(paddusw_r64_rm64), },
{ 0xDE, OP_2BYTE|OP_SSE, SSEOP(pmaxub_r64_rm64), SSEOP(pmaxub_r64_rm64), },
{ 0xDF, OP_2BYTE|OP_MMX, MMXOP(pandn_r64_rm64), MMXOP(pandn_r64_rm64), },
{ 0xE0, OP_2BYTE|OP_SSE, SSEOP(pavgb_r64_rm64), SSEOP(pavgb_r64_rm64), },
{ 0xE1, OP_2BYTE|OP_MMX, MMXOP(psraw_r64_rm64), MMXOP(psraw_r64_rm64), },
{ 0xE2, OP_2BYTE|OP_MMX, MMXOP(psrad_r64_rm64), MMXOP(psrad_r64_rm64), },
{ 0xE3, OP_2BYTE|OP_SSE, SSEOP(pavgw_r64_rm64), SSEOP(pavgw_r64_rm64), },
{ 0xE4, OP_2BYTE|OP_SSE, SSEOP(pmulhuw_r64_rm64), SSEOP(pmulhuw_r64_rm64), },
{ 0xE5, OP_2BYTE|OP_MMX, MMXOP(pmulhw_r64_rm64), MMXOP(pmulhw_r64_rm64), },
{ 0xE7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movntq_m64_r64), PENTIUMOP(movntq_m64_r64), },
{ 0xE8, OP_2BYTE|OP_MMX, MMXOP(psubsb_r64_rm64), MMXOP(psubsb_r64_rm64), },
{ 0xE9, OP_2BYTE|OP_MMX, MMXOP(psubsw_r64_rm64), MMXOP(psubsw_r64_rm64), },
{ 0xEA, OP_2BYTE|OP_SSE, SSEOP(pminsw_r64_rm64), SSEOP(pminsw_r64_rm64), },
{ 0xEB, OP_2BYTE|OP_MMX, MMXOP(por_r64_rm64), MMXOP(por_r64_rm64), },
{ 0xEC, OP_2BYTE|OP_MMX, MMXOP(paddsb_r64_rm64), MMXOP(paddsb_r64_rm64), },
{ 0xED, OP_2BYTE|OP_MMX, MMXOP(paddsw_r64_rm64), MMXOP(paddsw_r64_rm64), },
{ 0xEE, OP_2BYTE|OP_SSE, SSEOP(pmaxsw_r64_rm64), SSEOP(pmaxsw_r64_rm64), },
{ 0xEF, OP_2BYTE|OP_MMX, MMXOP(pxor_r64_rm64), MMXOP(pxor_r64_rm64), },
{ 0xF1, OP_2BYTE|OP_MMX, MMXOP(psllw_r64_rm64), MMXOP(psllw_r64_rm64), },
{ 0xF2, OP_2BYTE|OP_MMX, MMXOP(pslld_r64_rm64), MMXOP(pslld_r64_rm64), },
{ 0xF3, OP_2BYTE|OP_MMX, MMXOP(psllq_r64_rm64), MMXOP(psllq_r64_rm64), },
{ 0xF4, OP_2BYTE|OP_SSE, SSEOP(pmuludq_r64_rm64), SSEOP(pmuludq_r64_rm64), },
{ 0xF5, OP_2BYTE|OP_MMX, MMXOP(pmaddwd_r64_rm64), MMXOP(pmaddwd_r64_rm64), },
{ 0xF6, OP_2BYTE|OP_SSE, SSEOP(psadbw_r64_rm64), SSEOP(psadbw_r64_rm64), },
{ 0xf7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(maskmovq_r64_r64), PENTIUMOP(maskmovq_r64_r64),},
{ 0xF8, OP_2BYTE|OP_MMX, MMXOP(psubb_r64_rm64), MMXOP(psubb_r64_rm64), },
{ 0xF9, OP_2BYTE|OP_MMX, MMXOP(psubw_r64_rm64), MMXOP(psubw_r64_rm64), },
{ 0xFA, OP_2BYTE|OP_MMX, MMXOP(psubd_r64_rm64), MMXOP(psubd_r64_rm64), },
{ 0xFB, OP_2BYTE|OP_SSE, SSEOP(psubq_r64_rm64), SSEOP(psubq_r64_rm64), },
{ 0xFC, OP_2BYTE|OP_MMX, MMXOP(paddb_r64_rm64), MMXOP(paddb_r64_rm64), },
{ 0xFD, OP_2BYTE|OP_MMX, MMXOP(paddw_r64_rm64), MMXOP(paddw_r64_rm64), },
{ 0xFE, OP_2BYTE|OP_MMX, MMXOP(paddd_r64_rm64), MMXOP(paddd_r64_rm64), },
/* F3 0F ?? */
{ 0x2C, OP_3BYTEF3|OP_SSE, SSEOP(cvttss2si), SSEOP(cvttss2si), }
{ 0x10, OP_3BYTEF3|OP_SSE, SSEOP(movss_r128_rm128), SSEOP(movss_r128_rm128), },
{ 0x11, OP_3BYTEF3|OP_SSE, SSEOP(movss_rm128_r128), SSEOP(movss_rm128_r128), },
{ 0x12, OP_3BYTEF3|OP_SSE, SSEOP(movsldup_r128_rm128), SSEOP(movsldup_r128_rm128), },
{ 0x16, OP_3BYTEF3|OP_SSE, SSEOP(movshdup_r128_rm128), SSEOP(movshdup_r128_rm128), },
{ 0x2A, OP_3BYTEF3|OP_SSE, SSEOP(cvtsi2ss_r128_rm32), SSEOP(cvtsi2ss_r128_rm32), },
{ 0x2C, OP_3BYTEF3|OP_SSE, SSEOP(cvttss2si_r32_r128m32), SSEOP(cvttss2si_r32_r128m32),},
{ 0x2D, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2si_r32_r128m32), SSEOP(cvtss2si_r32_r128m32),},
{ 0x51, OP_3BYTEF3|OP_SSE, SSEOP(sqrtss_r128_r128m32), SSEOP(sqrtss_r128_r128m32), },
{ 0x52, OP_3BYTEF3|OP_SSE, SSEOP(rsqrtss_r128_r128m32), SSEOP(rsqrtss_r128_r128m32),},
{ 0x53, OP_3BYTEF3|OP_SSE, SSEOP(rcpss_r128_r128m32), SSEOP(rcpss_r128_r128m32), },
{ 0x58, OP_3BYTEF3|OP_SSE, SSEOP(addss), SSEOP(addss), },
{ 0x59, OP_3BYTEF3|OP_SSE, SSEOP(mulss), SSEOP(mulss), },
{ 0x5A, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2sd_r128_r128m32), SSEOP(cvtss2sd_r128_r128m32),},
{ 0x5B, OP_3BYTEF3|OP_SSE, SSEOP(cvttps2dq_r128_rm128), SSEOP(cvttps2dq_r128_rm128),},
{ 0x5C, OP_3BYTEF3|OP_SSE, SSEOP(subss), SSEOP(subss), },
{ 0x5D, OP_3BYTEF3|OP_SSE, SSEOP(minss_r128_r128m32), SSEOP(minss_r128_r128m32), },
{ 0x5E, OP_3BYTEF3|OP_SSE, SSEOP(divss), SSEOP(divss), },
{ 0x5F, OP_3BYTEF3|OP_SSE, SSEOP(maxss_r128_r128m32), SSEOP(maxss_r128_r128m32), },
{ 0x6F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_r128_rm128), SSEOP(movdqu_r128_rm128), },
{ 0x70, OP_3BYTEF3|OP_SSE, SSEOP(pshufhw_r128_rm128_i8), SSEOP(pshufhw_r128_rm128_i8),},
{ 0x7E, OP_3BYTEF3|OP_SSE, SSEOP(movq_r128_r128m64), SSEOP(movq_r128_r128m64), },
{ 0x7F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_rm128_r128), SSEOP(movdqu_rm128_r128), },
{ 0xB8, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(popcnt_r16_rm16), PENTIUMOP(popcnt_r32_rm32), },
{ 0xC2, OP_3BYTEF3|OP_SSE, SSEOP(cmpss_r128_r128m32_i8), SSEOP(cmpss_r128_r128m32_i8),},
{ 0xD6, OP_3BYTEF3|OP_SSE, SSEOP(movq2dq_r128_r64), SSEOP(movq2dq_r128_r64), },
{ 0xE6, OP_3BYTEF3|OP_SSE, SSEOP(cvtdq2pd_r128_r128m64), SSEOP(cvtdq2pd_r128_r128m64)}
};

31
src/emu/cpu/i386/i386priv.h
View File

@ -306,19 +306,29 @@ union I386_GPR {
UINT8 b[32];
};
union X87_REG {
UINT64 i;
double f;
union MMX_REG {
UINT32 d[2];
INT32 i[2];
UINT16 w[4];
INT16 s[4];
UINT8 b[8];
INT8 c[8];
float f[2];
UINT64 q;
INT64 l;
};
typedef UINT64 MMX_REG;
union XMM_REG {
UINT32 d[4];
UINT8 b[16];
UINT16 w[8];
UINT8 b[16];
UINT32 d[4];
UINT64 q[2];
float f[4];
INT8 c[16];
INT16 s[8];
INT32 i[4];
INT64 l[2];
float f[4];
double f64[2];
};
struct i386_state
@ -434,6 +444,8 @@ struct i386_state
vtlb_state *vtlb;
bool smm;
bool smi;
bool smi_latched;
bool nmi_masked;
bool nmi_latched;
UINT32 smbase;
@ -496,7 +508,7 @@ static int i386_limit_check(i386_state *cpustate, int seg, UINT32 offset);
#define SetSZPF16(x) {cpustate->ZF = ((UINT16)(x)==0); cpustate->SF = ((x)&0x8000) ? 1 : 0; cpustate->PF = i386_parity_table[x & 0xFF]; }
#define SetSZPF32(x) {cpustate->ZF = ((UINT32)(x)==0); cpustate->SF = ((x)&0x80000000) ? 1 : 0; cpustate->PF = i386_parity_table[x & 0xFF]; }
#define MMX(n) cpustate->fpu_reg[(n)].i
#define MMX(n) (*((MMX_REG *)(&cpustate->x87_reg[(n)].low)))
#define XMM(n) cpustate->sse_reg[(n)]
/***********************************************************************************/
@ -866,6 +878,7 @@ INLINE UINT16 READ16PL0(i386_state *cpustate,UINT32 ea)
}
return value;
}
INLINE UINT32 READ32PL0(i386_state *cpustate,UINT32 ea)
{
UINT32 value;

3405
src/emu/cpu/i386/pentops.c
View File

File diff suppressed because it is too large Load Diff

46
src/emu/cpu/i386/x87ops.c
View File

@ -3762,6 +3762,51 @@ void x87_fcomp_sti(i386_state *cpustate, UINT8 modrm)
CYCLES(cpustate, 4);
}
void x87_fcomip_sti(i386_state *cpustate, UINT8 modrm)
{
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
x87_set_stack_underflow(cpustate);
cpustate->ZF = 1;
cpustate->PF = 1;
cpustate->CF = 1;
}
else
{
cpustate->x87_sw &= ~X87_SW_C1;
floatx80 a = ST(0);
floatx80 b = ST(i);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
cpustate->ZF = 1;
cpustate->PF = 1;
cpustate->CF = 1;
cpustate->x87_sw |= X87_SW_IE;
}
else
{
cpustate->ZF = 0;
cpustate->PF = 0;
cpustate->CF = 0;
if (floatx80_eq(a, b))
cpustate->ZF = 1;
if (floatx80_lt(a, b))
cpustate->CF = 1;
}
}
if (x87_check_exceptions(cpustate))
x87_inc_stack(cpustate);
CYCLES(cpustate, 4); // TODO: correct cycle count
}
void x87_fcompp(i386_state *cpustate, UINT8 modrm)
{
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
@ -4651,6 +4696,7 @@ void build_x87_opcode_table_df(i386_state *cpustate)
switch (modrm)
{
case 0xe0: ptr = x87_fstsw_ax; break;
case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = x87_fcomip_sti; break;
}
}

1035
src/mame/drivers/chihiro.c
View File

File diff suppressed because it is too large Load Diff

2
src/mame/machine/naomigd.h
View File

@ -14,6 +14,8 @@ public:
static void static_set_tags(device_t &device, const char *_image_tag, const char *_pic_tag);
UINT8 *memory(UINT32 &size) { size = dimm_data_size; return dimm_data; }
protected:
virtual void device_start();
virtual void device_reset();