mirror of
https://github.com/holub/mame
synced 2025-04-23 17:00:53 +03:00
Modernised the R3000 core: [Phil Bennett]
* The following variants are supported: R3041, R3051, R3052, R3071 and R3081 * Endianness is now specified by MCFG_R3000_ENDIANNESS() (default is big-endian) * Removed configuration struct. Cache sizes and FPU availability are now determined from the CPU type * Added state saving * Added BrCond input callbacks
This commit is contained in:
Phil Bennett
parent
7a27335077
commit
444777967b
File diff suppressed because it is too large
Load Diff
@ -10,10 +10,24 @@
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#define __R3000_H__
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/***************************************************************************
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COMPILE-TIME DEFINITIONS
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INTERFACE CONFIGURATION MACROS
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***************************************************************************/
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#define MCFG_R3000_ENDIANNESS(_endianness) \
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r3000_device::static_set_endianness(*device, _endianness);
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#define MCFG_R3000_BRCOND0_INPUT(_devcb) \
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devcb = &r3000_device::static_set_brcond0_input(*device, DEVCB2_##_devcb);
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#define MCFG_R3000_BRCOND1_INPUT(_devcb) \
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devcb = &r3000_device::static_set_brcond1_input(*device, DEVCB2_##_devcb);
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#define MCFG_R3000_BRCOND2_INPUT(_devcb) \
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devcb = &r3000_device::static_set_brcond2_input(*device, DEVCB2_##_devcb);
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#define MCFG_R3000_BRCOND3_INPUT(_devcb) \
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devcb = &r3000_device::static_set_brcond3_input(*device, DEVCB2_##_devcb);
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/***************************************************************************
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@ -42,26 +56,262 @@ enum
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#define R3000_IRQ5 5 /* IRQ5 */
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/***************************************************************************
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STRUCTURES
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***************************************************************************/
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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struct r3000_cpu_core
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// ======================> r3000_device
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class r3000_device : public cpu_device
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{
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UINT8 hasfpu; /* 1 if we have an FPU, 0 otherwise */
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size_t icache; /* code cache size */
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size_t dcache; /* data cache size */
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protected:
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enum chip_type
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{
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CHIP_TYPE_R3041,
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CHIP_TYPE_R3051,
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CHIP_TYPE_R3052,
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CHIP_TYPE_R3071,
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CHIP_TYPE_R3081,
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};
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// construction/destruction
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r3000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, chip_type chiptype);
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virtual ~r3000_device();
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public:
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// inline configuration helpers
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static void static_set_endianness(device_t &device, endianness_t endianness)
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{
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downcast<r3000_device &>(device).m_endianness = endianness;
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}
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template<class _Object> static devcb2_base &static_set_brcond0_input(device_t &device, _Object object)
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{
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return downcast<r3000_device &>(device).m_in_brcond0.set_callback(object);
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}
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template<class _Object> static devcb2_base &static_set_brcond1_input(device_t &device, _Object object)
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{
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return downcast<r3000_device &>(device).m_in_brcond1.set_callback(object);
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}
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template<class _Object> static devcb2_base &static_set_brcond2_input(device_t &device, _Object object)
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{
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return downcast<r3000_device &>(device).m_in_brcond2.set_callback(object);
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}
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template<class _Object> static devcb2_base &static_set_brcond3_input(device_t &device, _Object object)
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{
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return downcast<r3000_device &>(device).m_in_brcond3.set_callback(object);
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}
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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virtual void device_post_load();
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const;
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virtual UINT32 execute_max_cycles() const;
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virtual UINT32 execute_input_lines() const;
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state);
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
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// device_state_interface overrides
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virtual void state_import(const device_state_entry &entry);
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virtual void state_export(const device_state_entry &entry);
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virtual void state_string_export(const device_state_entry &entry, astring &string);
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const;
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virtual UINT32 disasm_max_opcode_bytes() const;
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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// memory accessors
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struct r3000_data_accessors
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{
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UINT8 (r3000_device::*m_read_byte)(offs_t byteaddress);
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UINT16 (r3000_device::*m_read_word)(offs_t byteaddress);
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UINT32 (r3000_device::*m_read_dword)(offs_t byteaddress);
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void (r3000_device::*m_write_byte)(offs_t byteaddress, UINT8 data);
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void (r3000_device::*m_write_word)(offs_t byteaddress, UINT16 data);
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void (r3000_device::*m_write_dword)(offs_t byteaddress, UINT32 data);
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};
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UINT32 readop(off_t pc);
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UINT8 readmem(offs_t offset);
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UINT16 readmem_word(offs_t offset);
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UINT32 readmem_dword(offs_t offset);
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void writemem(offs_t offset, UINT8 data);
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void writemem_word(offs_t offset, UINT16 data);
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void writemem_dword(offs_t offset, UINT32 data);
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UINT8 readcache_be(offs_t offset);
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UINT16 readcache_be_word(offs_t offset);
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UINT32 readcache_be_dword(offs_t offset);
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void writecache_be(offs_t offset, UINT8 data);
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void writecache_be_word(offs_t offset, UINT16 data);
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void writecache_be_dword(offs_t offset, UINT32 data);
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UINT8 readcache_le(offs_t offset);
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UINT16 readcache_le_word(offs_t offset);
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UINT32 readcache_le_dword(offs_t offset);
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void writecache_le(offs_t offset, UINT8 data);
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void writecache_le_word(offs_t offset, UINT16 data);
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void writecache_le_dword(offs_t offset, UINT32 data);
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// interrupts
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void generate_exception(int exception);
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void check_irqs();
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void set_irq_line(int irqline, int state);
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void invalid_instruction();
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// instructions
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UINT32 get_cop0_reg(int idx);
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void set_cop0_reg(int idx, UINT32 val);
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UINT32 get_cop0_creg(int idx);
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void set_cop0_creg(int idx, UINT32 val);
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void handle_cop0();
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UINT32 get_cop1_reg(int idx);
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void set_cop1_reg(int idx, UINT32 val);
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UINT32 get_cop1_creg(int idx);
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void set_cop1_creg(int idx, UINT32 val);
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void handle_cop1();
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UINT32 get_cop2_reg(int idx);
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void set_cop2_reg(int idx, UINT32 val);
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UINT32 get_cop2_creg(int idx);
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void set_cop2_creg(int idx, UINT32 val);
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void handle_cop2();
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UINT32 get_cop3_reg(int idx);
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void set_cop3_reg(int idx, UINT32 val);
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UINT32 get_cop3_creg(int idx);
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void set_cop3_creg(int idx, UINT32 val);
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void handle_cop3();
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// complex opcodes
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void lwl_be();
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void lwr_be();
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void swl_be();
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void swr_be();
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void lwl_le();
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void lwr_le();
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void swl_le();
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void swr_le();
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// address spaces
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const address_space_config m_program_config_be;
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const address_space_config m_program_config_le;
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address_space *m_program;
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direct_read_data *m_direct;
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// configuration
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chip_type m_chip_type;
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bool m_hasfpu;
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endianness_t m_endianness;
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// core registers
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UINT32 m_pc;
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UINT32 m_nextpc;
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UINT32 m_hi;
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UINT32 m_lo;
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UINT32 m_r[32];
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// COP registers
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UINT32 m_cpr[4][32];
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UINT32 m_ccr[4][32];
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// internal stuff
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UINT32 m_ppc;
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UINT32 m_op;
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int m_icount;
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int m_interrupt_cycles;
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// endian-dependent load/store
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void (r3000_device::*m_lwl)();
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void (r3000_device::*m_lwr)();
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void (r3000_device::*m_swl)();
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void (r3000_device::*m_swr)();
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// memory accesses
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r3000_data_accessors *m_cur;
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r3000_data_accessors m_memory_hand;
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r3000_data_accessors m_cache_hand;
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// cache memory
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UINT32 * m_cache;
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UINT32 * m_icache;
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UINT32 * m_dcache;
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size_t m_cache_size;
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size_t m_icache_size;
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size_t m_dcache_size;
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// I/O
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devcb2_read_line m_in_brcond0;
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devcb2_read_line m_in_brcond1;
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devcb2_read_line m_in_brcond2;
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devcb2_read_line m_in_brcond3;
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};
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/***************************************************************************
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PUBLIC FUNCTIONS
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***************************************************************************/
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// ======================> r3041_device
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DECLARE_LEGACY_CPU_DEVICE(R3000BE, r3000be);
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DECLARE_LEGACY_CPU_DEVICE(R3000LE, r3000le);
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class r3041_device : public r3000_device
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{
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public:
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r3041_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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DECLARE_LEGACY_CPU_DEVICE(R3041BE, r3041be);
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DECLARE_LEGACY_CPU_DEVICE(R3041LE, r3041le);
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// ======================> r3051_device
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class r3051_device : public r3000_device
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{
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public:
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r3051_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// ======================> r3052_device
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class r3052_device : public r3000_device
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{
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public:
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r3052_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// ======================> r3071_device
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class r3071_device : public r3000_device
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{
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public:
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r3071_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// ======================> r3081_device
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class r3081_device : public r3000_device
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{
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public:
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r3081_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// device type definition
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extern const device_type R3041;
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extern const device_type R3051;
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extern const device_type R3052;
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extern const device_type R3071;
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extern const device_type R3081;
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#endif /* __R3000_H__ */
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@ -1545,15 +1545,7 @@ INPUT_PORTS_END
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*
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*************************************/
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static const r3000_cpu_core r3000_config =
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{
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0, /* 1 if we have an FPU, 0 otherwise */
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4096, /* code cache size */
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4096 /* data cache size */
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};
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static const jaguar_cpu_config gpu_config =
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static const jaguar_cpu_config gpu_config =
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{
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&jaguar_state::gpu_cpu_int
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};
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@ -1567,8 +1559,8 @@ static const jaguar_cpu_config dsp_config =
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static MACHINE_CONFIG_START( cojagr3k, jaguar_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", R3041BE, R3000_CLOCK)
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MCFG_CPU_CONFIG(r3000_config)
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MCFG_CPU_ADD("maincpu", R3041, R3000_CLOCK)
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MCFG_R3000_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_CPU_PROGRAM_MAP(r3000_map)
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MCFG_CPU_ADD("gpu", JAGUARGPU, COJAG_CLOCK/2)
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@ -2263,7 +2255,7 @@ void jaguar_state::cojag_common_init(UINT16 gpu_jump_offs, UINT16 spin_pc)
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m_is_cojag = true;
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/* copy over the ROM */
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m_is_r3000 = (m_main_cpu->type() == R3041BE);
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m_is_r3000 = (m_main_cpu->type() == R3041);
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/* install synchronization hooks for GPU */
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if (m_is_r3000)
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@ -402,19 +402,11 @@ INPUT_PORTS_END
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*
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*************************************/
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static const r3000_cpu_core r3000_config =
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{
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0, /* 1 if we have an FPU, 0 otherwise */
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4096, /* code cache size */
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4096 /* data cache size */
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};
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static MACHINE_CONFIG_START( policetr, policetr_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", R3000BE, MASTER_CLOCK/2)
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MCFG_CPU_CONFIG(r3000_config)
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MCFG_CPU_ADD("maincpu", R3041, MASTER_CLOCK/2)
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MCFG_R3000_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_CPU_PROGRAM_MAP(policetr_map)
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MCFG_CPU_VBLANK_INT_DRIVER("screen", policetr_state, irq4_gen)
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@ -326,13 +326,6 @@ static const st0016_interface st0016_config =
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&st0016_charram
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};
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static const r3000_cpu_core r3000_config =
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{
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0,
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4096, /* code cache size */
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2048 /* data cache size */
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};
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MACHINE_RESET_MEMBER(speglsht_state,speglsht)
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{
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memset(m_shared,0,0x1000);
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@ -393,8 +386,8 @@ static MACHINE_CONFIG_START( speglsht, speglsht_state )
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MCFG_CPU_VBLANK_INT_DRIVER("screen", speglsht_state, irq0_line_hold)
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MCFG_CPU_ADD("sub", R3000LE, 25000000)
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MCFG_CPU_CONFIG(r3000_config)
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MCFG_CPU_ADD("sub", R3051, 25000000)
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MCFG_R3000_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_CPU_PROGRAM_MAP(speglsht_mem)
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MCFG_CPU_VBLANK_INT_DRIVER("screen", speglsht_state, irq4_line_assert)
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@ -501,13 +501,6 @@ static const st0016_interface st0016_config =
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&st0016_charram
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};
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static const r3000_cpu_core r3000_config =
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{
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1, /* 1 if we have an FPU, 0 otherwise */
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4096, /* code cache size */
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4096 /* data cache size */
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};
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static const gfx_layout tile_16x8x8_layout =
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{
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16,8,
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@ -545,8 +538,8 @@ static MACHINE_CONFIG_START( srmp5, srmp5_state )
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MCFG_CPU_IO_MAP(st0016_io)
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MCFG_CPU_VBLANK_INT_DRIVER("screen", srmp5_state, irq0_line_hold)
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MCFG_CPU_ADD("sub", R3000LE, 25000000)
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MCFG_CPU_CONFIG(r3000_config)
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MCFG_CPU_ADD("sub", R3051, 25000000)
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MCFG_R3000_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_CPU_PROGRAM_MAP(srmp5_mem)
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MCFG_CPU_VBLANK_INT_DRIVER("screen", srmp5_state, irq4_line_assert)
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@ -115,19 +115,12 @@ static INPUT_PORTS_START( turrett )
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INPUT_PORTS_END
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static const r3000_cpu_core r3000_config =
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{
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0, /* 1 if we have an FPU, 0 otherwise */
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2048, /* code cache size */
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512 /* data cache size */
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};
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static MACHINE_CONFIG_START( turrett, turrett_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", R3041BE, R3041_CLOCK)
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MCFG_CPU_ADD("maincpu", R3041, R3041_CLOCK)
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MCFG_R3000_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_CPU_PROGRAM_MAP(cpu_map)
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MCFG_CPU_CONFIG(r3000_config)
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/* video hardware */
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MCFG_SCREEN_ADD("screen", RASTER)
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