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am9517a_device: converted to devcb2 (nw)

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This commit is contained in:
Ivan Vangelista 2014-04-29 16:56:31 +00:00
parent e9314bc4ec
commit 4460827d21
28 changed files with 555 additions and 587 deletions
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57
src/emu/bus/pci/southbridge.c
View File

@ -10,29 +10,6 @@
#include "bus/pc_kbd/keyboards.h"
I8237_INTERFACE( at_dma8237_1_config )
{
DEVCB_DEVICE_LINE_MEMBER("dma8237_2",am9517a_device,dreq0_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, at_dma8237_out_eop),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma_read_byte),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma_write_byte),
{ DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_0_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_1_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_2_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_3_dack_r) },
{ DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_0_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_1_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_2_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_3_dack_w) },
{ DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dack0_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dack1_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dack2_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dack3_w) }
};
I8237_INTERFACE( at_dma8237_2_config )
{
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma_hrq_changed),
DEVCB_NULL,
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma_read_word),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma_write_word),
{ DEVCB_NULL, DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_5_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_6_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_7_dack_r) },
{ DEVCB_NULL, DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_5_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_6_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dma8237_7_dack_w) },
{ DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dack4_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dack5_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dack6_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, southbridge_device, pc_dack7_w) }
};
static SLOT_INTERFACE_START(pc_isa_onboard)
SLOT_INTERFACE("comat", ISA8_COM_AT)
SLOT_INTERFACE("lpt", ISA8_LPT)
@ -48,8 +25,38 @@ static MACHINE_CONFIG_FRAGMENT( southbridge )
MCFG_PIT8253_CLK2(4772720/4) /* pio port c pin 4, and speaker polling enough */
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(southbridge_device, at_pit8254_out2_changed))
MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, at_dma8237_1_config )
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, at_dma8237_2_config )
MCFG_DEVICE_ADD( "dma8237_1", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq0_w))
MCFG_I8237_OUT_EOP_CB(WRITELINE(southbridge_device, at_dma8237_out_eop))
MCFG_I8237_IN_MEMR_CB(READ8(southbridge_device, pc_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(southbridge_device, pc_dma_write_byte))
MCFG_I8237_IN_IOR_0_CB(READ8(southbridge_device, pc_dma8237_0_dack_r))
MCFG_I8237_IN_IOR_1_CB(READ8(southbridge_device, pc_dma8237_1_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(southbridge_device, pc_dma8237_2_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(southbridge_device, pc_dma8237_3_dack_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(southbridge_device, pc_dma8237_0_dack_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(southbridge_device, pc_dma8237_1_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(southbridge_device, pc_dma8237_2_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(southbridge_device, pc_dma8237_3_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(southbridge_device, pc_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(southbridge_device, pc_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(southbridge_device, pc_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(southbridge_device, pc_dack3_w))
MCFG_DEVICE_ADD( "dma8237_2", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(southbridge_device, pc_dma_hrq_changed))
MCFG_I8237_IN_MEMR_CB(READ8(southbridge_device, pc_dma_read_word))
MCFG_I8237_OUT_MEMW_CB(WRITE8(southbridge_device, pc_dma_write_word))
MCFG_I8237_IN_IOR_1_CB(READ8(southbridge_device, pc_dma8237_5_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(southbridge_device, pc_dma8237_6_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(southbridge_device, pc_dma8237_7_dack_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(southbridge_device, pc_dma8237_5_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(southbridge_device, pc_dma8237_6_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(southbridge_device, pc_dma8237_7_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(southbridge_device, pc_dack4_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(southbridge_device, pc_dack5_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(southbridge_device, pc_dack6_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(southbridge_device, pc_dack7_w))
MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE(":maincpu", 0), VCC, READ8(southbridge_device, get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir2_w), GND, NULL )

27
src/emu/bus/wangpc/rtc.c
View File

@ -101,31 +101,6 @@ static const z80_daisy_config wangpc_rtc_daisy_chain[] =
{ NULL }
};
//-------------------------------------------------
// I8237_INTERFACE( dmac_intf )
//-------------------------------------------------
static I8237_INTERFACE( dmac_intf )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
{ DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL, },
{ DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL, },
{ DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL }
};
//-------------------------------------------------
// MACHINE_CONFIG_FRAGMENT( wangpc_rtc )
//-------------------------------------------------
@ -136,7 +111,7 @@ static MACHINE_CONFIG_FRAGMENT( wangpc_rtc )
MCFG_CPU_PROGRAM_MAP(wangpc_rtc_mem)
MCFG_CPU_IO_MAP(wangpc_rtc_io)
MCFG_I8237_ADD(AM9517A_TAG, 2000000, dmac_intf)
MCFG_DEVICE_ADD(AM9517A_TAG, AM9517A, 2000000)
MCFG_DEVICE_ADD(Z80CTC_0_TAG, Z80CTC, 2000000)
MCFG_Z80CTC_INTR_CB(INPUTLINE(Z80_TAG, INPUT_LINE_IRQ0))

157
src/emu/machine/am9517a.c
View File

@ -152,7 +152,7 @@ inline void am9517a_device::set_hreq(int state)
{
if (m_hreq != state)
{
m_out_hreq_func(state);
m_out_hreq_cb(state);
m_hreq = state;
}
@ -167,13 +167,49 @@ inline void am9517a_device::set_dack()
{
for (int channel = 0; channel < 4; channel++)
{
if ((channel == m_current_channel) && !COMMAND_MEM_TO_MEM)
if (channel == 0)
{
m_channel[channel].m_out_dack_func(COMMAND_DACK_ACTIVE_HIGH);
if ((channel == m_current_channel) && !COMMAND_MEM_TO_MEM)
{
m_out_dack_0_cb(COMMAND_DACK_ACTIVE_HIGH);
}
else
{
m_out_dack_0_cb(!COMMAND_DACK_ACTIVE_HIGH);
}
}
else
else if (channel == 1)
{
m_channel[channel].m_out_dack_func(!COMMAND_DACK_ACTIVE_HIGH);
if ((channel == m_current_channel) && !COMMAND_MEM_TO_MEM)
{
m_out_dack_1_cb(COMMAND_DACK_ACTIVE_HIGH);
}
else
{
m_out_dack_1_cb(!COMMAND_DACK_ACTIVE_HIGH);
}
}
else if (channel == 2)
{
if ((channel == m_current_channel) && !COMMAND_MEM_TO_MEM)
{
m_out_dack_2_cb(COMMAND_DACK_ACTIVE_HIGH);
}
else
{
m_out_dack_2_cb(!COMMAND_DACK_ACTIVE_HIGH);
}
}
else if (channel == 3)
{
if ((channel == m_current_channel) && !COMMAND_MEM_TO_MEM)
{
m_out_dack_3_cb(COMMAND_DACK_ACTIVE_HIGH);
}
else
{
m_out_dack_3_cb(!COMMAND_DACK_ACTIVE_HIGH);
}
}
}
}
@ -187,7 +223,7 @@ inline void am9517a_device::set_eop(int state)
{
if (m_eop != state)
{
m_out_eop_func(state);
m_out_eop_cb(state);
m_eop = state;
}
@ -223,11 +259,25 @@ inline void am9517a_device::dma_read()
{
case MODE_TRANSFER_VERIFY:
case MODE_TRANSFER_WRITE:
m_temp = m_channel[m_current_channel].m_in_ior_func(offset);
switch(m_current_channel)
{
case 0:
m_temp = m_in_ior_0_cb(offset);
break;
case 1:
m_temp = m_in_ior_1_cb(offset);
break;
case 2:
m_temp = m_in_ior_2_cb(offset);
break;
case 3:
m_temp = m_in_ior_3_cb(offset);
break;
}
break;
case MODE_TRANSFER_READ:
m_temp = m_in_memr_func(offset);
m_temp = m_in_memr_cb(offset);
break;
}
}
@ -244,18 +294,32 @@ inline void am9517a_device::dma_write()
switch (MODE_TRANSFER_MASK)
{
case MODE_TRANSFER_VERIFY: {
UINT8 v1 = m_in_memr_func(offset);
UINT8 v1 = m_in_memr_cb(offset);
if(0 && m_temp != v1)
logerror("%s: verify error %02x vs. %02x\n", tag(), m_temp, v1);
break;
}
case MODE_TRANSFER_WRITE:
m_out_memw_func(offset, m_temp);
m_out_memw_cb(offset, m_temp);
break;
case MODE_TRANSFER_READ:
m_channel[m_current_channel].m_out_iow_func(offset, m_temp);
switch(m_current_channel)
{
case 0:
m_out_iow_0_cb(offset, m_temp);
break;
case 1:
m_out_iow_1_cb(offset, m_temp);
break;
case 2:
m_out_iow_2_cb(offset, m_temp);
break;
case 3:
m_out_iow_3_cb(offset, m_temp);
break;
}
break;
}
}
@ -387,44 +451,28 @@ am9517a_device::am9517a_device(const machine_config &mconfig, const char *tag, d
: device_t(mconfig, AM9517A, "AM9517A", tag, owner, clock, "am9517a", __FILE__),
device_execute_interface(mconfig, *this),
m_icount(0),
m_out_hreq_cb(*this),
m_out_eop_cb(*this),
m_in_memr_cb(*this),
m_out_memw_cb(*this),
m_in_ior_0_cb(*this),
m_in_ior_1_cb(*this),
m_in_ior_2_cb(*this),
m_in_ior_3_cb(*this),
m_out_iow_0_cb(*this),
m_out_iow_1_cb(*this),
m_out_iow_2_cb(*this),
m_out_iow_3_cb(*this),
m_out_dack_0_cb(*this),
m_out_dack_1_cb(*this),
m_out_dack_2_cb(*this),
m_out_dack_3_cb(*this),
m_hack(0),
m_ready(1),
m_command(0)
{
}
//-------------------------------------------------
// device_config_complete - perform any
// operations now that the configuration is
// complete
//-------------------------------------------------
void am9517a_device::device_config_complete()
{
// inherit a copy of the static data
const am9517a_interface *intf = reinterpret_cast<const am9517a_interface *>(static_config());
if (intf != NULL)
*static_cast<am9517a_interface *>(this) = *intf;
// or initialize to defaults if none provided
else
{
memset(&m_out_hreq_cb, 0, sizeof(m_out_hreq_cb));
memset(&m_out_eop_cb, 0, sizeof(m_out_eop_cb));
memset(&m_in_memr_cb, 0, sizeof(m_in_memr_cb));
memset(&m_out_memw_cb, 0, sizeof(m_out_memw_cb));
for (int i = 0; i < 4; i++)
{
memset(&m_in_ior_cb[i], 0, sizeof(m_in_ior_cb[i]));
memset(&m_out_iow_cb[i], 0, sizeof(m_out_iow_cb[i]));
memset(&m_out_dack_cb[i], 0, sizeof(m_out_dack_cb[i]));
}
}
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
@ -435,16 +483,25 @@ void am9517a_device::device_start()
m_icountptr = &m_icount;
// resolve callbacks
m_out_hreq_func.resolve(m_out_hreq_cb, *this);
m_out_eop_func.resolve(m_out_eop_cb, *this);
m_in_memr_func.resolve(m_in_memr_cb, *this);
m_out_memw_func.resolve(m_out_memw_cb, *this);
m_out_hreq_cb.resolve_safe();
m_out_eop_cb.resolve_safe();
m_in_memr_cb.resolve_safe(0);
m_out_memw_cb.resolve_safe();
m_in_ior_0_cb.resolve_safe(0);
m_in_ior_1_cb.resolve_safe(0);
m_in_ior_2_cb.resolve_safe(0);
m_in_ior_3_cb.resolve_safe(0);
m_out_iow_0_cb.resolve_safe();
m_out_iow_1_cb.resolve_safe();
m_out_iow_2_cb.resolve_safe();
m_out_iow_3_cb.resolve_safe();
m_out_dack_0_cb.resolve_safe();
m_out_dack_1_cb.resolve_safe();
m_out_dack_2_cb.resolve_safe();
m_out_dack_3_cb.resolve_safe();
for (int i = 0; i < 4; i++)
{
m_channel[i].m_in_ior_func.resolve(m_in_ior_cb[i], *this);
m_channel[i].m_out_iow_func.resolve(m_out_iow_cb[i], *this);
m_channel[i].m_out_dack_func.resolve(m_out_dack_cb[i], *this);
m_channel[i].m_address = 0;
m_channel[i].m_count = 0;
m_channel[i].m_base_address = 0;

156
src/emu/machine/am9517a.h
View File

@ -40,58 +40,40 @@
#include "emu.h"
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define MCFG_AM9517A_ADD(_tag, _clock, _config) \
MCFG_DEVICE_ADD(_tag, AM9517A, _clock) \
MCFG_DEVICE_CONFIG(_config)
#define MCFG_I8237_ADD(_tag, _clock, _config) \
MCFG_DEVICE_ADD(_tag, AM9517A, _clock) \
MCFG_DEVICE_CONFIG(_config)
#define AM9517A_INTERFACE(_name) \
const am9517a_interface (_name) =
#define I8237_INTERFACE(_name) \
const am9517a_interface (_name) =
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
// ======================> am9517a_interface
struct am9517a_interface
{
devcb_write_line m_out_hreq_cb;
devcb_write_line m_out_eop_cb;
devcb_read8 m_in_memr_cb;
devcb_write8 m_out_memw_cb;
devcb_read8 m_in_ior_cb[4];
devcb_write8 m_out_iow_cb[4];
devcb_write_line m_out_dack_cb[4];
};
// ======================> am9517a_device
class am9517a_device : public device_t,
public device_execute_interface,
public am9517a_interface
public device_execute_interface
{
public:
// construction/destruction
am9517a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
template<class _Object> static devcb2_base &set_out_hreq_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_hreq_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_eop_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_eop_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_in_memr_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_in_memr_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_memw_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_memw_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_in_ior_0_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_in_ior_0_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_in_ior_1_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_in_ior_1_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_in_ior_2_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_in_ior_2_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_in_ior_3_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_in_ior_3_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_iow_0_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_iow_0_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_iow_1_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_iow_1_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_iow_2_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_iow_2_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_iow_3_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_iow_3_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_dack_0_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_dack_0_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_dack_1_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_dack_1_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_dack_2_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_dack_2_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_dack_3_callback(device_t &device, _Object object) { return downcast<am9517a_device &>(device).m_out_dack_3_cb.set_callback(object); }
DECLARE_READ8_MEMBER( read );
DECLARE_WRITE8_MEMBER( write );
@ -106,7 +88,6 @@ public:
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
virtual void execute_run();
@ -126,17 +107,27 @@ private:
inline void dma_advance();
inline void end_of_process();
devcb_resolved_write_line m_out_hreq_func;
devcb_resolved_write_line m_out_eop_func;
devcb_resolved_read8 m_in_memr_func;
devcb_resolved_write8 m_out_memw_func;
devcb2_write_line m_out_hreq_cb;
devcb2_write_line m_out_eop_cb;
devcb2_read8 m_in_memr_cb;
devcb2_write8 m_out_memw_cb;
devcb2_read8 m_in_ior_0_cb;
devcb2_read8 m_in_ior_1_cb;
devcb2_read8 m_in_ior_2_cb;
devcb2_read8 m_in_ior_3_cb;
devcb2_write8 m_out_iow_0_cb;
devcb2_write8 m_out_iow_1_cb;
devcb2_write8 m_out_iow_2_cb;
devcb2_write8 m_out_iow_3_cb;
devcb2_write_line m_out_dack_0_cb;
devcb2_write_line m_out_dack_1_cb;
devcb2_write_line m_out_dack_2_cb;
devcb2_write_line m_out_dack_3_cb;
struct
{
devcb_resolved_read8 m_in_ior_func;
devcb_resolved_write8 m_out_iow_func;
devcb_resolved_write_line m_out_dack_func;
UINT16 m_address;
UINT16 m_count;
UINT16 m_base_address;
@ -163,6 +154,73 @@ private:
// device type definition
extern const device_type AM9517A;
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define MCFG_AM9517A_OUT_HREQ_CB(_devcb) \
devcb = &am9517a_device::set_out_hreq_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_EOP_CB(_devcb) \
devcb = &am9517a_device::set_out_eop_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_IN_MEMR_CB(_devcb) \
devcb = &am9517a_device::set_in_memr_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_MEMW_CB(_devcb) \
devcb = &am9517a_device::set_out_memw_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_IN_IOR_0_CB(_devcb) \
devcb = &am9517a_device::set_in_ior_0_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_IN_IOR_1_CB(_devcb) \
devcb = &am9517a_device::set_in_ior_1_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_IN_IOR_2_CB(_devcb) \
devcb = &am9517a_device::set_in_ior_2_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_IN_IOR_3_CB(_devcb) \
devcb = &am9517a_device::set_in_ior_3_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_IOW_0_CB(_devcb) \
devcb = &am9517a_device::set_out_iow_0_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_IOW_1_CB(_devcb) \
devcb = &am9517a_device::set_out_iow_1_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_IOW_2_CB(_devcb) \
devcb = &am9517a_device::set_out_iow_2_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_IOW_3_CB(_devcb) \
devcb = &am9517a_device::set_out_iow_3_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_DACK_0_CB(_devcb) \
devcb = &am9517a_device::set_out_dack_0_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_DACK_1_CB(_devcb) \
devcb = &am9517a_device::set_out_dack_1_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_DACK_2_CB(_devcb) \
devcb = &am9517a_device::set_out_dack_2_callback(*device, DEVCB2_##_devcb);
#define MCFG_AM9517A_OUT_DACK_3_CB(_devcb) \
devcb = &am9517a_device::set_out_dack_3_callback(*device, DEVCB2_##_devcb);
#define MCFG_I8237_OUT_HREQ_CB MCFG_AM9517A_OUT_HREQ_CB
#define MCFG_I8237_OUT_EOP_CB MCFG_AM9517A_OUT_EOP_CB
#define MCFG_I8237_IN_MEMR_CB MCFG_AM9517A_IN_MEMR_CB
#define MCFG_I8237_OUT_MEMW_CB MCFG_AM9517A_OUT_MEMW_CB
#define MCFG_I8237_IN_IOR_0_CB MCFG_AM9517A_IN_IOR_0_CB
#define MCFG_I8237_IN_IOR_1_CB MCFG_AM9517A_IN_IOR_1_CB
#define MCFG_I8237_IN_IOR_2_CB MCFG_AM9517A_IN_IOR_2_CB
#define MCFG_I8237_IN_IOR_3_CB MCFG_AM9517A_IN_IOR_3_CB
#define MCFG_I8237_OUT_IOW_0_CB MCFG_AM9517A_OUT_IOW_0_CB
#define MCFG_I8237_OUT_IOW_1_CB MCFG_AM9517A_OUT_IOW_1_CB
#define MCFG_I8237_OUT_IOW_2_CB MCFG_AM9517A_OUT_IOW_2_CB
#define MCFG_I8237_OUT_IOW_3_CB MCFG_AM9517A_OUT_IOW_3_CB
#define MCFG_I8237_OUT_DACK_0_CB MCFG_AM9517A_OUT_DACK_0_CB
#define MCFG_I8237_OUT_DACK_1_CB MCFG_AM9517A_OUT_DACK_1_CB
#define MCFG_I8237_OUT_DACK_2_CB MCFG_AM9517A_OUT_DACK_2_CB
#define MCFG_I8237_OUT_DACK_3_CB MCFG_AM9517A_OUT_DACK_3_CB
#endif

85
src/emu/machine/cs4031.c
View File

@ -93,61 +93,38 @@ const float cs4031_device::m_dma_clock_divider[] =
// machine configurations
//-------------------------------------------------
I8237_INTERFACE( dma1_config )
{
DEVCB_DEVICE_LINE_MEMBER("dma2", am9517a_device, dreq0_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_eop_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma_read_byte),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma_write_byte),
{
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_ior0_r),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_ior1_r),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_ior2_r),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_ior3_r)
},
{
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_iow0_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_iow1_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_iow2_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_iow3_w)
},
{
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_dack0_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_dack1_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_dack2_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_dack3_w)
}
};
I8237_INTERFACE( dma2_config )
{
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_hreq_w),
DEVCB_NULL,
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma_read_word),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma_write_word),
{
DEVCB_NULL,
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_ior1_r),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_ior2_r),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_ior3_r)
},
{
DEVCB_NULL,
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_iow1_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_iow2_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_iow3_w)
},
{
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_dack0_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_dack1_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_dack2_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_dack3_w)
}
};
static MACHINE_CONFIG_FRAGMENT( cs4031 )
MCFG_I8237_ADD("dma1", 0, dma1_config)
MCFG_I8237_ADD("dma2", 0, dma2_config)
MCFG_DEVICE_ADD("dma1", AM9517A, 0)
MCFG_I8237_OUT_HREQ_CB(DEVWRITELINE("dma2", am9517a_device, dreq0_w))
MCFG_I8237_OUT_EOP_CB(WRITELINE(cs4031_device, dma1_eop_w))
MCFG_I8237_IN_MEMR_CB(READ8(cs4031_device, dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(cs4031_device, dma_write_byte))
MCFG_I8237_IN_IOR_0_CB(READ8(cs4031_device, dma1_ior0_r))
MCFG_I8237_IN_IOR_1_CB(READ8(cs4031_device, dma1_ior1_r))
MCFG_I8237_IN_IOR_2_CB(READ8(cs4031_device, dma1_ior2_r))
MCFG_I8237_IN_IOR_3_CB(READ8(cs4031_device, dma1_ior3_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(cs4031_device, dma1_iow0_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(cs4031_device, dma1_iow1_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(cs4031_device, dma1_iow2_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(cs4031_device, dma1_iow3_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(cs4031_device, dma1_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(cs4031_device, dma1_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(cs4031_device, dma1_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(cs4031_device, dma1_dack3_w))
MCFG_DEVICE_ADD("dma2", AM9517A, 0)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(cs4031_device, dma2_hreq_w))
MCFG_I8237_IN_MEMR_CB(READ8(cs4031_device, dma_read_word))
MCFG_I8237_OUT_MEMW_CB(WRITE8(cs4031_device, dma_write_word))
MCFG_I8237_IN_IOR_1_CB(READ8(cs4031_device, dma2_ior1_r))
MCFG_I8237_IN_IOR_2_CB(READ8(cs4031_device, dma2_ior2_r))
MCFG_I8237_IN_IOR_3_CB(READ8(cs4031_device, dma2_ior3_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(cs4031_device, dma2_iow1_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(cs4031_device, dma2_iow2_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(cs4031_device, dma2_iow3_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(cs4031_device, dma2_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(cs4031_device, dma2_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(cs4031_device, dma2_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(cs4031_device, dma2_dack3_w))
MCFG_PIC8259_ADD("intc1", WRITELINE(cs4031_device, intc1_int_w), VCC, READ8(cs4031_device, intc1_slave_ack_r))
MCFG_PIC8259_ADD("intc2", DEVWRITELINE("intc1", pic8259_device, ir2_w), GND, NULL)

28
src/mame/drivers/pcxt.c
View File

@ -17,7 +17,7 @@ TODO:
- 02851: tetriskr: Corrupt game graphics after some time of gameplay, caused by a wrong
reading of the i/o $3c8 bit 1.
- Add a proper FDC device.
- Filetto: Add UM5100 sound chip ,might be connected to the prototyping card;
- Filetto: Add UM5100 sound chip, might be connected to the prototyping card;
- buzzer sound has issues in both games
********************************************************************************************
@ -73,9 +73,9 @@ class pcxt_state : public driver_device
public:
pcxt_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_pit8253(*this,"pit8253"),
m_pic8259_1(*this,"pic8259_1"),
m_dma8237_1(*this,"dma8237_1") ,
m_pit8253(*this, "pit8253"),
m_pic8259_1(*this, "pic8259_1"),
m_dma8237_1(*this, "dma8237_1") ,
m_maincpu(*this, "maincpu"),
m_speaker(*this, "speaker") { }
@ -553,17 +553,6 @@ WRITE_LINE_MEMBER(pcxt_state::pc_dack1_w){ set_dma_channel(m_dma8237_1, 1, state
WRITE_LINE_MEMBER(pcxt_state::pc_dack2_w){ set_dma_channel(m_dma8237_1, 2, state); }
WRITE_LINE_MEMBER(pcxt_state::pc_dack3_w){ set_dma_channel(m_dma8237_1, 3, state); }
static I8237_INTERFACE( dma8237_1_config )
{
DEVCB_DRIVER_LINE_MEMBER(pcxt_state,pc_dma_hrq_changed),
DEVCB_NULL,
DEVCB_DRIVER_MEMBER(pcxt_state, pc_dma_read_byte),
DEVCB_DRIVER_MEMBER(pcxt_state, pc_dma_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_DRIVER_LINE_MEMBER(pcxt_state,pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(pcxt_state,pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(pcxt_state,pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(pcxt_state,pc_dack3_w) }
};
/******************
8259 IRQ controller
******************/
@ -730,7 +719,14 @@ static MACHINE_CONFIG_FRAGMENT(pcxt)
MCFG_I8255_OUT_PORTA_CB(WRITE8(pcxt_state, wss_2_w))
MCFG_I8255_OUT_PORTA_CB(WRITE8(pcxt_state, sys_reset_w))
MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
MCFG_DEVICE_ADD("dma8237_1", AM9517A, XTAL_14_31818MHz/3)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pcxt_state, pc_dma_hrq_changed))
MCFG_I8237_IN_MEMR_CB(READ8(pcxt_state, pc_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pcxt_state, pc_dma_write_byte))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pcxt_state, pc_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pcxt_state, pc_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pcxt_state, pc_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pcxt_state, pc_dack3_w))
MCFG_PIC8259_ADD( "pic8259_1", INPUTLINE("maincpu", 0), VCC, NULL )

34
src/mame/machine/pcshare.c
View File

@ -116,29 +116,6 @@ WRITE_LINE_MEMBER( pcat_base_state::pc_dack1_w ) { set_dma_channel(1, state); }
WRITE_LINE_MEMBER( pcat_base_state::pc_dack2_w ) { set_dma_channel(2, state); }
WRITE_LINE_MEMBER( pcat_base_state::pc_dack3_w ) { set_dma_channel(3, state); }
static I8237_INTERFACE( dma8237_1_config )
{
DEVCB_DRIVER_LINE_MEMBER(pcat_base_state, pc_dma_hrq_changed),
DEVCB_NULL,
DEVCB_DRIVER_MEMBER(pcat_base_state, pc_dma_read_byte),
DEVCB_DRIVER_MEMBER(pcat_base_state, pc_dma_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_DRIVER_LINE_MEMBER(pcat_base_state, pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(pcat_base_state, pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(pcat_base_state, pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(pcat_base_state, pc_dack3_w) }
};
static I8237_INTERFACE( dma8237_2_config )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
/******************
8259 IRQ controller
******************/
@ -173,8 +150,15 @@ ADDRESS_MAP_END
MACHINE_CONFIG_FRAGMENT(pcat_common)
MCFG_PIC8259_ADD( "pic8259_1", INPUTLINE("maincpu", 0), VCC, READ8(pcat_base_state, get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_2", DEVWRITELINE("pic8259_1", pic8259_device, ir2_w), GND, NULL )
MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
MCFG_DEVICE_ADD( "dma8237_1", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pcat_base_state, pc_dma_hrq_changed))
MCFG_I8237_IN_MEMR_CB(READ8(pcat_base_state, pc_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pcat_base_state, pc_dma_write_byte))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pcat_base_state, pc_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pcat_base_state, pc_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pcat_base_state, pc_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pcat_base_state, pc_dack3_w))
MCFG_DEVICE_ADD( "dma8237_2", AM9517A, XTAL_14_31818MHz/3 )
MCFG_DEVICE_ADD("pit8254", PIT8254, 0)
MCFG_PIT8253_CLK0(4772720/4) /* heartbeat IRQ */

22
src/mess/drivers/apc.c
View File

@ -896,16 +896,6 @@ CH1: FDC
CH2: ("reserved for future graphics expansion")
CH3: AUX
*/
static I8237_INTERFACE( dmac_intf )
{
DEVCB_DRIVER_LINE_MEMBER(apc_state, apc_dma_hrq_changed),
DEVCB_DRIVER_LINE_MEMBER(apc_state, apc_tc_w),
DEVCB_DRIVER_MEMBER(apc_state, apc_dma_read_byte),
DEVCB_DRIVER_MEMBER(apc_state, apc_dma_write_byte),
{ DEVCB_NULL, DEVCB_DRIVER_MEMBER(apc_state,fdc_r), DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_DRIVER_MEMBER(apc_state,fdc_w), DEVCB_NULL, DEVCB_NULL },
{ DEVCB_DRIVER_LINE_MEMBER(apc_state, apc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(apc_state, apc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(apc_state, apc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(apc_state, apc_dack3_w) }
};
static const floppy_format_type apc_floppy_formats[] = {
FLOPPY_D88_FORMAT,
@ -944,7 +934,17 @@ static MACHINE_CONFIG_START( apc, apc_state )
MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE("maincpu", 0), VCC, READ8(apc_state,get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir7_w), GND, NULL ) // TODO: check ir7_w
MCFG_I8237_ADD("i8237", MAIN_CLOCK, dmac_intf)
MCFG_DEVICE_ADD("i8237", AM9517A, MAIN_CLOCK)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(apc_state, apc_dma_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(apc_state, apc_tc_w))
MCFG_I8237_IN_MEMR_CB(READ8(apc_state, apc_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(apc_state, apc_dma_write_byte))
MCFG_I8237_IN_IOR_1_CB(READ8(apc_state, fdc_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(apc_state, fdc_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(apc_state, apc_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(apc_state, apc_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(apc_state, apc_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(apc_state, apc_dack3_w))
MCFG_NVRAM_ADD_1FILL("cmos")
MCFG_UPD1990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)

21
src/mess/drivers/apricotp.c
View File

@ -421,22 +421,6 @@ INPUT_PORTS_END
*/
//-------------------------------------------------
// I8237_INTERFACE( dmac_intf )
//-------------------------------------------------
static I8237_INTERFACE( dmac_intf )
{
DEVCB_NULL,
DEVCB_DEVICE_LINE_MEMBER(I8259A_TAG, pic8259_device, ir7_w),
DEVCB_NULL,
DEVCB_NULL,
{ DEVCB_NULL, DEVCB_DEVICE_MEMBER(WD2797_TAG, wd_fdc_t, data_r), DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_DEVICE_MEMBER(WD2797_TAG, wd_fdc_t, data_w), DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
//-------------------------------------------------
// wd17xx_interface fdc_intf
//-------------------------------------------------
@ -554,7 +538,10 @@ static MACHINE_CONFIG_START( fp, fp_state )
/* Devices */
MCFG_DEVICE_ADD(APRICOT_KEYBOARD_TAG, APRICOT_KEYBOARD, 0)
MCFG_I8237_ADD(I8237_TAG, 250000, dmac_intf)
MCFG_DEVICE_ADD(I8237_TAG, AM9517A, 250000)
MCFG_I8237_OUT_EOP_CB(DEVWRITELINE(I8259A_TAG, pic8259_device, ir7_w))
MCFG_I8237_IN_IOR_1_CB(DEVREAD8(WD2797_TAG, wd_fdc_t, data_r))
MCFG_I8237_OUT_IOW_1_CB(DEVWRITE8(WD2797_TAG, wd_fdc_t, data_w))
MCFG_PIC8259_ADD(I8259A_TAG, INPUTLINE(I8086_TAG, INPUT_LINE_IRQ0), VCC, NULL)
MCFG_DEVICE_ADD(I8253A5_TAG, PIT8253, 0)

33
src/mess/drivers/at.c
View File

@ -300,8 +300,37 @@ static MACHINE_CONFIG_FRAGMENT( at_motherboard )
MCFG_PIT8253_CLK2(4772720/4) /* pio port c pin 4, and speaker polling enough */
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(at_state, at_pit8254_out2_changed))
MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, at_dma8237_1_config )
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, at_dma8237_2_config )
MCFG_DEVICE_ADD( "dma8237_1", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq0_w))
MCFG_I8237_OUT_EOP_CB(WRITELINE(at_state, at_dma8237_out_eop))
MCFG_I8237_IN_MEMR_CB(READ8(at_state, pc_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(at_state, pc_dma_write_byte))
MCFG_I8237_IN_IOR_0_CB(READ8(at_state, pc_dma8237_0_dack_r))
MCFG_I8237_IN_IOR_1_CB(READ8(at_state, pc_dma8237_1_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(at_state, pc_dma8237_2_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(at_state, pc_dma8237_3_dack_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(at_state, pc_dma8237_0_dack_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(at_state, pc_dma8237_1_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(at_state, pc_dma8237_2_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(at_state, pc_dma8237_3_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(at_state, pc_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(at_state, pc_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(at_state, pc_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(at_state, pc_dack3_w))
MCFG_DEVICE_ADD( "dma8237_2", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(at_state, pc_dma_hrq_changed))
MCFG_I8237_IN_MEMR_CB(READ8(at_state, pc_dma_read_word))
MCFG_I8237_OUT_MEMW_CB(WRITE8(at_state, pc_dma_write_word))
MCFG_I8237_IN_IOR_1_CB(READ8(at_state, pc_dma8237_5_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(at_state, pc_dma8237_6_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(at_state, pc_dma8237_7_dack_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(at_state, pc_dma8237_5_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(at_state, pc_dma8237_6_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(at_state, pc_dma8237_7_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(at_state, pc_dack4_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(at_state, pc_dack5_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(at_state, pc_dack6_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(at_state, pc_dack7_w))
MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE("maincpu", 0), VCC, READ8(at_state, get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir2_w), GND, NULL )

20
src/mess/drivers/attache.c
View File

@ -871,17 +871,6 @@ static const ay8910_interface ay8912_interface =
DEVCB_NULL /* portB write */
};
static const am9517a_interface dma_interface =
{
DEVCB_DRIVER_LINE_MEMBER(attache_state,hreq_w), // out_hreq_cb
DEVCB_DRIVER_LINE_MEMBER(attache_state,eop_w), // out_eop_cb
DEVCB_DRIVER_MEMBER(attache_state,dma_mem_r), // in_memr_cb
DEVCB_DRIVER_MEMBER(attache_state,dma_mem_w), // out_memw_cb
{DEVCB_DRIVER_MEMBER(attache_state,fdc_dma_r), DEVCB_NULL, DEVCB_NULL, DEVCB_NULL}, // in_ior_cb[4]
{DEVCB_DRIVER_MEMBER(attache_state,fdc_dma_w), DEVCB_NULL, DEVCB_NULL, DEVCB_NULL}, // out_iow_cb[4]
{DEVCB_NULL,/*DEVCB_DRIVER_LINE_MEMBER(attache_state,fdc_dack_w),*/ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL} // out_dack_cb[4]
};
// IRQ daisy chain = CTC -> SIO -> Expansion
static const z80_daisy_config attache_daisy_chain[] =
{
@ -985,7 +974,14 @@ static MACHINE_CONFIG_START( attache, attache_state )
MCFG_DEVICE_ADD("ctc", Z80CTC, XTAL_8MHz / 4)
MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
MCFG_AM9517A_ADD("dma",XTAL_8MHz / 4, dma_interface)
MCFG_DEVICE_ADD("dma", AM9517A, XTAL_8MHz / 4)
MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(attache_state, hreq_w))
MCFG_AM9517A_OUT_EOP_CB(WRITELINE(attache_state, eop_w))
MCFG_AM9517A_IN_MEMR_CB(READ8(attache_state, dma_mem_r))
MCFG_AM9517A_OUT_MEMW_CB(WRITE8(attache_state, dma_mem_w))
MCFG_AM9517A_IN_IOR_0_CB(READ8(attache_state, fdc_dma_r))
MCFG_AM9517A_OUT_IOW_0_CB(WRITE8(attache_state, fdc_dma_w))
// MCFG_AM9517A_OUT_DACK_0_CB(WRITELINE(attache_state, fdc_dack_w))
MCFG_UPD765A_ADD("fdc", true, true)
MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE("ctc", z80ctc_device, trg3))

15
src/mess/drivers/b16.c
View File

@ -283,17 +283,6 @@ WRITE8_MEMBER(b16_state::memory_write_byte)
return prog_space.write_byte(offset, data);
}
static I8237_INTERFACE( b16_dma8237_interface )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_DRIVER_MEMBER(b16_state, memory_read_byte),
DEVCB_DRIVER_MEMBER(b16_state, memory_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
static MACHINE_CONFIG_START( b16, b16_state )
/* basic machine hardware */
@ -312,7 +301,9 @@ static MACHINE_CONFIG_START( b16, b16_state )
MCFG_SCREEN_PALETTE("palette")
MCFG_MC6845_ADD("crtc", H46505, "screen", XTAL_14_31818MHz/5, mc6845_intf) /* unknown clock, hand tuned to get ~60 fps */
MCFG_I8237_ADD("8237dma", XTAL_14_31818MHz/2, b16_dma8237_interface)
MCFG_DEVICE_ADD("8237dma", AM9517A, XTAL_14_31818MHz/2)
MCFG_I8237_IN_MEMR_CB(READ8(b16_state, memory_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(b16_state, memory_write_byte))
MCFG_GFXDECODE_ADD("gfxdecode", "palette", b16)
MCFG_PALETTE_ADD("palette", 8)

14
src/mess/drivers/bebox.c
View File

@ -165,9 +165,19 @@ static MACHINE_CONFIG_START( bebox, bebox_state )
MCFG_PIT8253_CLK2(4772720/4) /* pio port c pin 4, and speaker polling enough */
MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("kbdc", kbdc8042_device, write_out2))
MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, bebox_dma8237_1_config )
MCFG_DEVICE_ADD( "dma8237_1", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(bebox_state, bebox_dma_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(bebox_state, bebox_dma8237_out_eop))
MCFG_I8237_IN_MEMR_CB(READ8(bebox_state, bebox_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(bebox_state, bebox_dma_write_byte))
MCFG_I8237_IN_IOR_2_CB(READ8(bebox_state, bebox_dma8237_fdc_dack_r))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(bebox_state, bebox_dma8237_fdc_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(bebox_state, pc_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(bebox_state, pc_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(bebox_state, pc_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(bebox_state, pc_dack3_w))
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, bebox_dma8237_2_config )
MCFG_DEVICE_ADD( "dma8237_2", AM9517A, XTAL_14_31818MHz/3 )
MCFG_PIC8259_ADD( "pic8259_1", WRITELINE(bebox_state,bebox_pic8259_master_set_int_line), VCC, READ8(bebox_state,get_slave_ack) )

20
src/mess/drivers/dmv.c
View File

@ -253,7 +253,7 @@ GFXDECODE_END
//------------------------------------------------------------------------------------
// I8237_INTERFACE
// I8237
//------------------------------------------------------------------------------------
WRITE_LINE_MEMBER( dmv_state::dma_hrq_changed )
@ -276,17 +276,6 @@ WRITE8_MEMBER(dmv_state::memory_write_byte)
return prog_space.write_byte(offset, data);
}
static I8237_INTERFACE( dmv_dma8237_config )
{
DEVCB_DRIVER_LINE_MEMBER(dmv_state, dma_hrq_changed),
DEVCB_NULL,
DEVCB_DRIVER_MEMBER(dmv_state, memory_read_byte),
DEVCB_DRIVER_MEMBER(dmv_state, memory_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(dmv_state, fdc_dma_r) },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(dmv_state, fdc_dma_w) },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
static MACHINE_CONFIG_START( dmv, dmv_state )
/* basic machine hardware */
@ -319,7 +308,12 @@ static MACHINE_CONFIG_START( dmv, dmv_state )
MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(dmv_state, hgdc_display_pixels)
MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(dmv_state, hgdc_draw_text)
MCFG_I8237_ADD( "dma8237", XTAL_4MHz, dmv_dma8237_config )
MCFG_DEVICE_ADD( "dma8237", AM9517A, XTAL_4MHz )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(dmv_state, dma_hrq_changed))
MCFG_I8237_IN_MEMR_CB(READ8(dmv_state, memory_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(dmv_state, memory_write_byte))
MCFG_I8237_IN_IOR_3_CB(READ8(dmv_state, fdc_dma_r))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(dmv_state, fdc_dma_w))
MCFG_UPD765A_ADD( "upd765", true, true )
MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("dma8237", am9517a_device, dreq3_w))
MCFG_FLOPPY_DRIVE_ADD("upd765:0", dmv_floppies, "525dd", floppy_image_device::default_floppy_formats)

24
src/mess/drivers/mikromik.c
View File

@ -345,18 +345,6 @@ WRITE_LINE_MEMBER( mm1_state::dack3_w )
update_tc();
}
static I8237_INTERFACE( dmac_intf )
{
DEVCB_DRIVER_LINE_MEMBER(mm1_state, dma_hrq_w),
DEVCB_DRIVER_LINE_MEMBER(mm1_state, dma_eop_w),
DEVCB_DRIVER_MEMBER(mm1_state, read),
DEVCB_DRIVER_MEMBER(mm1_state, write),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(mm1_state, mpsc_dack_r), DEVCB_DEVICE_MEMBER(UPD765_TAG, upd765_family_device, mdma_r) },
{ DEVCB_DEVICE_MEMBER(I8275_TAG, i8275x_device, dack_w), DEVCB_DRIVER_MEMBER(mm1_state, mpsc_dack_w), DEVCB_NULL, DEVCB_DEVICE_MEMBER(UPD765_TAG, upd765_family_device, mdma_w) },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(mm1_state, dack3_w) }
};
WRITE_LINE_MEMBER( mm1_state::itxc_w )
{
if (!m_intc)
@ -479,7 +467,17 @@ static MACHINE_CONFIG_START( mm1, mm1_state )
MCFG_I8212_IRQ_CALLBACK(INPUTLINE(I8085A_TAG, I8085_RST65_LINE))
MCFG_I8212_DI_CALLBACK(DEVREAD8(KB_TAG, mm1_keyboard_t, read))
MCFG_I8237_ADD(I8237_TAG, XTAL_6_144MHz/2, dmac_intf)
MCFG_DEVICE_ADD(I8237_TAG, AM9517A, XTAL_6_144MHz/2)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(mm1_state, dma_hrq_w))
MCFG_I8237_OUT_EOP_CB(WRITELINE(mm1_state, dma_eop_w))
MCFG_I8237_IN_MEMR_CB(READ8(mm1_state, read))
MCFG_I8237_OUT_MEMW_CB(WRITE8(mm1_state, write))
MCFG_I8237_IN_IOR_2_CB(READ8(mm1_state, mpsc_dack_r))
MCFG_I8237_IN_IOR_3_CB(DEVREAD8(UPD765_TAG, upd765_family_device, mdma_r))
MCFG_I8237_OUT_IOW_0_CB(DEVWRITE8(I8275_TAG, i8275x_device, dack_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(mm1_state, mpsc_dack_w))
MCFG_I8237_OUT_IOW_3_CB(DEVWRITE8(UPD765_TAG, upd765_family_device, mdma_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(mm1_state, dack3_w))
MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
MCFG_PIT8253_CLK0(XTAL_6_144MHz/2/2)

16
src/mess/drivers/paso1600.c
View File

@ -312,18 +312,6 @@ WRITE8_MEMBER(paso1600_state::pc_dma_write_byte)
space.write_byte(offset, data);
}
static I8237_INTERFACE( paso1600_dma8237_interface )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_DRIVER_MEMBER(paso1600_state, pc_dma_read_byte),
DEVCB_DRIVER_MEMBER(paso1600_state, pc_dma_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
static MACHINE_CONFIG_START( paso1600, paso1600_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I8086, 16000000/2)
@ -347,7 +335,9 @@ static MACHINE_CONFIG_START( paso1600, paso1600_state )
/* Devices */
MCFG_MC6845_ADD("crtc", H46505, "screen", 16000000/4, mc6845_intf) /* unknown clock, hand tuned to get ~60 fps */
MCFG_PIC8259_ADD( "pic8259", INPUTLINE("maincpu", 0), GND, NULL )
MCFG_I8237_ADD("8237dma", 16000000/4, paso1600_dma8237_interface)
MCFG_DEVICE_ADD("8237dma", AM9517A, 16000000/4)
MCFG_I8237_IN_MEMR_CB(READ8(paso1600_state, pc_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(paso1600_state, pc_dma_write_byte))
MACHINE_CONFIG_END
ROM_START( paso1600 )

44
src/mess/drivers/pasogo.c
View File

@ -833,33 +833,6 @@ void pasogo_state::select_dma_channel(int channel, bool state)
}
}
static I8237_INTERFACE( dma8237_config )
{
DEVCB_DRIVER_LINE_MEMBER(pasogo_state, dma_hrq_changed),
DEVCB_DRIVER_LINE_MEMBER(pasogo_state, dma8237_out_eop),
DEVCB_DRIVER_MEMBER(pasogo_state, dma_read_byte),
DEVCB_DRIVER_MEMBER(pasogo_state, dma_write_byte),
{ DEVCB_NULL,
DEVCB_DRIVER_MEMBER(pasogo_state, dma8237_1_dack_r),
DEVCB_DRIVER_MEMBER(pasogo_state, dma8237_2_dack_r),
DEVCB_DRIVER_MEMBER(pasogo_state, dma8237_3_dack_r) },
{ DEVCB_DRIVER_MEMBER(pasogo_state, dma8237_0_dack_w),
DEVCB_DRIVER_MEMBER(pasogo_state, dma8237_1_dack_w),
DEVCB_DRIVER_MEMBER(pasogo_state, dma8237_2_dack_w),
DEVCB_DRIVER_MEMBER(pasogo_state, dma8237_3_dack_w) },
// DACK's
{ DEVCB_DRIVER_LINE_MEMBER(pasogo_state, dack0_w),
DEVCB_DRIVER_LINE_MEMBER(pasogo_state, dack1_w),
DEVCB_DRIVER_LINE_MEMBER(pasogo_state, dack2_w),
DEVCB_DRIVER_LINE_MEMBER(pasogo_state, dack3_w) }
};
READ8_MEMBER (pasogo_state::ppi_porta_r)
{
int data = 0xFF;
@ -945,7 +918,22 @@ static MACHINE_CONFIG_START( pasogo, pasogo_state )
MCFG_PIC8259_ADD( "pic8259", INPUTLINE("maincpu", 0), VCC, NULL )
MCFG_I8237_ADD( "dma8237", XTAL_14_31818MHz/3, dma8237_config )
MCFG_DEVICE_ADD( "dma8237", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pasogo_state, dma_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(pasogo_state, dma8237_out_eop))
MCFG_I8237_IN_MEMR_CB(READ8(pasogo_state, dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pasogo_state, dma_write_byte))
MCFG_I8237_IN_IOR_1_CB(READ8(pasogo_state, dma8237_1_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(pasogo_state, dma8237_2_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(pasogo_state, dma8237_3_dack_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(pasogo_state, dma8237_0_dack_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(pasogo_state, dma8237_1_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(pasogo_state, dma8237_2_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(pasogo_state, dma8237_3_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pasogo_state, dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pasogo_state, dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pasogo_state, dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pasogo_state, dack3_w))
MCFG_DEVICE_ADD("ppi8255", I8255, 0)
MCFG_I8255_IN_PORTA_CB(READ8(pasogo_state, ppi_porta_r))

55
src/mess/drivers/pc1512.c
View File

@ -950,27 +950,6 @@ WRITE_LINE_MEMBER( pc1512_state::dack3_w )
if (!state) m_dma_channel = 3;
}
static I8237_INTERFACE( dmac_intf )
{
DEVCB_DRIVER_LINE_MEMBER(pc1512_state, hrq_w),
DEVCB_DRIVER_LINE_MEMBER(pc1512_state, eop_w),
DEVCB_DRIVER_MEMBER(pc1512_state, memr_r),
DEVCB_DRIVER_MEMBER(pc1512_state, memw_w),
{ DEVCB_NULL,
DEVCB_DRIVER_MEMBER(pc1512_state, ior1_r),
DEVCB_DRIVER_MEMBER(pc1512_state, ior2_r),
DEVCB_DRIVER_MEMBER(pc1512_state, ior3_r) },
{ DEVCB_DRIVER_MEMBER(pc1512_state, iow0_w),
DEVCB_DRIVER_MEMBER(pc1512_state, iow1_w),
DEVCB_DRIVER_MEMBER(pc1512_state, iow2_w),
DEVCB_DRIVER_MEMBER(pc1512_state, iow3_w) },
{ DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack0_w),
DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack1_w),
DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack2_w),
DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack3_w) }
};
//-------------------------------------------------
// pit8253_config pit_intf
//-------------------------------------------------
@ -1256,7 +1235,22 @@ static MACHINE_CONFIG_START( pc1512, pc1512_state )
MCFG_DEVICE_ADD(PC1512_KEYBOARD_TAG, PC1512_KEYBOARD, 0)
MCFG_PC1512_KEYBOARD_CLOCK_CALLBACK(WRITELINE(pc1512_state, kbclk_w))
MCFG_PC1512_KEYBOARD_DATA_CALLBACK(WRITELINE(pc1512_state, kbdata_w))
MCFG_I8237_ADD(I8237A5_TAG, XTAL_24MHz/6, dmac_intf)
MCFG_DEVICE_ADD(I8237A5_TAG, AM9517A, XTAL_24MHz/6)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc1512_state, hrq_w))
MCFG_I8237_OUT_EOP_CB(WRITELINE(pc1512_state, eop_w))
MCFG_I8237_IN_MEMR_CB(READ8(pc1512_state, memr_r))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pc1512_state, memw_w))
MCFG_I8237_IN_IOR_1_CB(READ8(pc1512_state, ior1_r))
MCFG_I8237_IN_IOR_2_CB(READ8(pc1512_state, ior2_r))
MCFG_I8237_IN_IOR_3_CB(READ8(pc1512_state, ior3_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(pc1512_state, iow0_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(pc1512_state, iow1_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(pc1512_state, iow2_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(pc1512_state, iow3_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc1512_state, dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc1512_state, dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc1512_state, dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc1512_state, dack3_w))
MCFG_PIC8259_ADD(I8259A2_TAG, INPUTLINE(I8086_TAG, INPUT_LINE_IRQ0), VCC, NULL)
MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
@ -1357,7 +1351,22 @@ static MACHINE_CONFIG_START( pc1640, pc1640_state )
MCFG_DEVICE_ADD(PC1512_KEYBOARD_TAG, PC1512_KEYBOARD, 0)
MCFG_PC1512_KEYBOARD_CLOCK_CALLBACK(WRITELINE(pc1512_state, kbclk_w))
MCFG_PC1512_KEYBOARD_DATA_CALLBACK(WRITELINE(pc1512_state, kbdata_w))
MCFG_I8237_ADD(I8237A5_TAG, XTAL_24MHz/6, dmac_intf)
MCFG_DEVICE_ADD(I8237A5_TAG, AM9517A, XTAL_24MHz/6)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc1512_state, hrq_w))
MCFG_I8237_OUT_EOP_CB(WRITELINE(pc1512_state, eop_w))
MCFG_I8237_IN_MEMR_CB(READ8(pc1512_state, memr_r))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pc1512_state, memw_w))
MCFG_I8237_IN_IOR_1_CB(READ8(pc1512_state, ior1_r))
MCFG_I8237_IN_IOR_2_CB(READ8(pc1512_state, ior2_r))
MCFG_I8237_IN_IOR_3_CB(READ8(pc1512_state, ior3_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(pc1512_state, iow0_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(pc1512_state, iow1_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(pc1512_state, iow2_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(pc1512_state, iow3_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc1512_state, dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc1512_state, dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc1512_state, dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc1512_state, dack3_w))
MCFG_PIC8259_ADD(I8259A2_TAG, INPUTLINE(I8086_TAG, INPUT_LINE_IRQ0), VCC, NULL)
MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)

64
src/mess/drivers/pc9801.c
View File

@ -3136,35 +3136,11 @@ WRITE8_MEMBER(pc9801_state::fdc_2dd_w)
m_fdc_2dd->dma_w(data);
}
/* TODO: check channels 0 - 1 */
static I8237_INTERFACE( dmac_intf )
{
DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dma_hrq_changed),
DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_tc_w),
DEVCB_DRIVER_MEMBER(pc9801_state, pc9801_dma_read_byte),
DEVCB_DRIVER_MEMBER(pc9801_state, pc9801_dma_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(pc9801_state,fdc_2hd_r), DEVCB_DRIVER_MEMBER(pc9801_state,fdc_2dd_r) },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(pc9801_state,fdc_2hd_w), DEVCB_DRIVER_MEMBER(pc9801_state,fdc_2dd_w) },
{ DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack0_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack1_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack2_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack3_w) }
};
/*
ch1 cs-4231a
ch2 FDC
ch3 SCSI
*/
static I8237_INTERFACE( pc9801rs_dmac_intf )
{
DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dma_hrq_changed),
DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_tc_w),
DEVCB_DRIVER_MEMBER(pc9801_state, pc9801_dma_read_byte),
DEVCB_DRIVER_MEMBER(pc9801_state, pc9801_dma_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(pc9801_state,fdc_2hd_r), DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(pc9801_state,fdc_2hd_w), DEVCB_NULL },
{ DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack0_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack1_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack2_w), DEVCB_DRIVER_LINE_MEMBER(pc9801_state, pc9801_dack3_w) }
};
/****************************************
*
@ -3588,7 +3564,19 @@ static MACHINE_CONFIG_START( pc9801, pc9801_state )
MCFG_PIT8253_CLK2(MAIN_CLOCK_X1) /* RS-232c */
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(pc9801_state, write_uart_clock))
MCFG_I8237_ADD("i8237", 5000000, dmac_intf) // unknown clock
MCFG_DEVICE_ADD("i8237", AM9517A, 5000000) // unknown clock, TODO: check channels 0 - 1
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc9801_state, pc9801_dma_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(pc9801_state, pc9801_tc_w))
MCFG_I8237_IN_MEMR_CB(READ8(pc9801_state, pc9801_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pc9801_state, pc9801_dma_write_byte))
MCFG_I8237_IN_IOR_2_CB(READ8(pc9801_state, fdc_2hd_r))
MCFG_I8237_IN_IOR_3_CB(READ8(pc9801_state, fdc_2dd_r))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(pc9801_state, fdc_2hd_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(pc9801_state, fdc_2dd_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc9801_state, pc9801_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc9801_state, pc9801_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc9801_state, pc9801_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc9801_state, pc9801_dack3_w))
MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE("maincpu", 0), VCC, READ8(pc9801_state,get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir7_w), GND, NULL ) // TODO: Check ir7_w
@ -3689,7 +3677,17 @@ static MACHINE_CONFIG_START( pc9801rs, pc9801_state )
MCFG_PIT8253_CLK2(MAIN_CLOCK_X1) /* RS-232c */
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(pc9801_state, write_uart_clock))
MCFG_I8237_ADD("i8237", MAIN_CLOCK_X1*8, pc9801rs_dmac_intf) // unknown clock
MCFG_DEVICE_ADD("i8237", AM9517A, MAIN_CLOCK_X1*8) // unknown clock
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc9801_state, pc9801_dma_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(pc9801_state, pc9801_tc_w))
MCFG_I8237_IN_MEMR_CB(READ8(pc9801_state, pc9801_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pc9801_state, pc9801_dma_write_byte))
MCFG_I8237_IN_IOR_2_CB(READ8(pc9801_state, fdc_2hd_r))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(pc9801_state, fdc_2hd_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc9801_state, pc9801_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc9801_state, pc9801_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc9801_state, pc9801_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc9801_state, pc9801_dack3_w))
MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE("maincpu", 0), VCC, READ8(pc9801_state,get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir7_w), GND, NULL ) // TODO: Check ir7_w
@ -3767,7 +3765,7 @@ static MACHINE_CONFIG_DERIVED( pc9801ux, pc9801rs )
MCFG_80286_A20(pc9801_state, pc9801_286_a20)
MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
// MCFG_I8237_REPLACE("i8237", 10000000, pc9801rs_dmac_intf) // unknown clock
// MCFG_DEVICE_MODIFY("i8237", AM9157A, 10000000) // unknown clock
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( pc9801bx2, pc9801rs )
@ -3797,7 +3795,17 @@ static MACHINE_CONFIG_START( pc9821, pc9801_state )
MCFG_PIT8253_CLK2(MAIN_CLOCK_X2) /* RS-232c */
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(pc9801_state, write_uart_clock))
MCFG_I8237_ADD("i8237", 16000000, pc9801rs_dmac_intf) // unknown clock
MCFG_DEVICE_ADD("i8237", AM9517A, 16000000) // unknown clock
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc9801_state, pc9801_dma_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(pc9801_state, pc9801_tc_w))
MCFG_I8237_IN_MEMR_CB(READ8(pc9801_state, pc9801_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pc9801_state, pc9801_dma_write_byte))
MCFG_I8237_IN_IOR_2_CB(READ8(pc9801_state, fdc_2hd_r))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(pc9801_state, fdc_2hd_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc9801_state, pc9801_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc9801_state, pc9801_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc9801_state, pc9801_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc9801_state, pc9801_dack3_w))
MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE("maincpu", 0), VCC, READ8(pc9801_state,get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir7_w), GND, NULL ) // TODO: Check ir7_w

35
src/mess/drivers/qx10.c
View File

@ -395,17 +395,6 @@ WRITE8_MEMBER(qx10_state::memory_write_byte)
return prog_space.write_byte(offset, data);
}
static I8237_INTERFACE( qx10_dma8237_1_interface )
{
DEVCB_DRIVER_LINE_MEMBER(qx10_state,dma_hrq_changed),
DEVCB_DRIVER_LINE_MEMBER(qx10_state, tc_w),
DEVCB_DRIVER_MEMBER(qx10_state, memory_read_byte),
DEVCB_DRIVER_MEMBER(qx10_state, memory_write_byte),
{ DEVCB_DRIVER_MEMBER(qx10_state, fdc_dma_r), DEVCB_DRIVER_MEMBER(qx10_state, gdc_dack_r),/*DEVCB_DEVICE_MEMBER("upd7220", upd7220_device, dack_r)*/ DEVCB_NULL, DEVCB_NULL },
{ DEVCB_DRIVER_MEMBER(qx10_state, fdc_dma_w), DEVCB_DRIVER_MEMBER(qx10_state, gdc_dack_w),/*DEVCB_DEVICE_MEMBER("upd7220", upd7220_device, dack_w)*/ DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
/*
8237 DMA (Slave)
Channel 1: Option slots #1
@ -413,16 +402,6 @@ static I8237_INTERFACE( qx10_dma8237_1_interface )
Channel 3: Option slots #3
Channel 4: Option slots #4
*/
static I8237_INTERFACE( qx10_dma8237_2_interface )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
/*
MC146818
@ -806,8 +785,18 @@ static MACHINE_CONFIG_START( qx10, qx10_state )
MCFG_Z80DART_OUT_RTSB_CB(DEVWRITELINE(RS232_TAG, rs232_port_device, write_rts))
MCFG_Z80DART_OUT_INT_CB(WRITELINE(qx10_state, keyboard_irq))
MCFG_I8237_ADD("8237dma_1", MAIN_CLK/4, qx10_dma8237_1_interface)
MCFG_I8237_ADD("8237dma_2", MAIN_CLK/4, qx10_dma8237_2_interface)
MCFG_DEVICE_ADD("8237dma_1", AM9517A, MAIN_CLK/4)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(qx10_state, dma_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(qx10_state, tc_w))
MCFG_I8237_IN_MEMR_CB(READ8(qx10_state, memory_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(qx10_state, memory_write_byte))
MCFG_I8237_IN_IOR_0_CB(READ8(qx10_state, fdc_dma_r))
MCFG_I8237_IN_IOR_1_CB(READ8(qx10_state, gdc_dack_r))
//MCFG_I8237_IN_IOR_2_CB(DEVREAD8("upd7220", upd7220_device, dack_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(qx10_state, fdc_dma_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(qx10_state, gdc_dack_w))
//MCFG_I8237_OUT_IOW_2_CB(DEVWRITE8("upd7220", upd7220_device, dack_w))
MCFG_DEVICE_ADD("8237dma_2", AM9517A, MAIN_CLK/4)
MCFG_DEVICE_ADD("i8255", I8255, 0)

39
src/mess/drivers/wangpc.c
View File

@ -618,7 +618,7 @@ INPUT_PORTS_END
//**************************************************************************
//-------------------------------------------------
// I8237_INTERFACE( dmac_intf )
// I8237
//-------------------------------------------------
void wangpc_state::update_fdc_tc()
@ -707,27 +707,6 @@ WRITE_LINE_MEMBER( wangpc_state::dack3_w )
if (!state) m_dack = 3;
}
static AM9517A_INTERFACE( dmac_intf )
{
DEVCB_DRIVER_LINE_MEMBER(wangpc_state, hrq_w),
DEVCB_DRIVER_LINE_MEMBER(wangpc_state, eop_w),
DEVCB_DRIVER_MEMBER(wangpc_state, memr_r),
DEVCB_DRIVER_MEMBER(wangpc_state, memw_w),
{ DEVCB_NULL,
DEVCB_DEVICE_MEMBER(WANGPC_BUS_TAG, wangpcbus_device, dack1_r),
DEVCB_DRIVER_MEMBER(wangpc_state, ior2_r),
DEVCB_DEVICE_MEMBER(WANGPC_BUS_TAG, wangpcbus_device, dack3_r) },
{ DEVCB_NULL,
DEVCB_DEVICE_MEMBER(WANGPC_BUS_TAG, wangpcbus_device, dack1_w),
DEVCB_DRIVER_MEMBER(wangpc_state, iow2_w),
DEVCB_DEVICE_MEMBER(WANGPC_BUS_TAG, wangpcbus_device, dack3_w) },
{ DEVCB_DRIVER_LINE_MEMBER(wangpc_state, dack0_w),
DEVCB_DRIVER_LINE_MEMBER(wangpc_state, dack1_w),
DEVCB_DRIVER_LINE_MEMBER(wangpc_state, dack2_w),
DEVCB_DRIVER_LINE_MEMBER(wangpc_state, dack3_w) }
};
//-------------------------------------------------
// pic8259_interface pic_intf
//-------------------------------------------------
@ -1099,7 +1078,21 @@ static MACHINE_CONFIG_START( wangpc, wangpc_state )
//MCFG_QUANTUM_PERFECT_CPU(I8086_TAG)
// devices
MCFG_AM9517A_ADD(AM9517A_TAG, 4000000, dmac_intf)
MCFG_DEVICE_ADD(AM9517A_TAG, AM9517A, 4000000)
MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(wangpc_state, hrq_w))
MCFG_AM9517A_OUT_EOP_CB(WRITELINE(wangpc_state, eop_w))
MCFG_AM9517A_IN_MEMR_CB(READ8(wangpc_state, memr_r))
MCFG_AM9517A_OUT_MEMW_CB(WRITE8(wangpc_state, memw_w))
MCFG_AM9517A_IN_IOR_1_CB(DEVREAD8(WANGPC_BUS_TAG, wangpcbus_device, dack1_r))
MCFG_AM9517A_IN_IOR_2_CB(READ8(wangpc_state, ior2_r))
MCFG_AM9517A_IN_IOR_3_CB(DEVREAD8(WANGPC_BUS_TAG, wangpcbus_device, dack3_r))
MCFG_AM9517A_OUT_IOW_1_CB(DEVWRITE8(WANGPC_BUS_TAG, wangpcbus_device, dack1_w))
MCFG_AM9517A_OUT_IOW_2_CB(WRITE8(wangpc_state, iow2_w))
MCFG_AM9517A_OUT_IOW_3_CB(DEVWRITE8(WANGPC_BUS_TAG, wangpcbus_device, dack3_w))
MCFG_AM9517A_OUT_DACK_0_CB(WRITELINE(wangpc_state, dack0_w))
MCFG_AM9517A_OUT_DACK_1_CB(WRITELINE(wangpc_state, dack1_w))
MCFG_AM9517A_OUT_DACK_2_CB(WRITELINE(wangpc_state, dack2_w))
MCFG_AM9517A_OUT_DACK_3_CB(WRITELINE(wangpc_state, dack3_w))
MCFG_PIC8259_ADD(I8259A_TAG, INPUTLINE(I8086_TAG, INPUT_LINE_IRQ0), VCC, NULL)

20
src/mess/drivers/wicat.c
View File

@ -747,19 +747,6 @@ I8275_DRAW_CHARACTER_MEMBER(wicat_state::wicat_display_pixels)
}
}
AM9517A_INTERFACE( wicat_videodma_intf )
{
DEVCB_DRIVER_LINE_MEMBER(wicat_state,dma_hrq_w), // m_out_hreq_cb;
DEVCB_DRIVER_LINE_MEMBER(wicat_state,dma_nmi_cb), // m_out_eop_cb;
DEVCB_DRIVER_MEMBER(wicat_state,vram_r), // m_in_memr_cb;
DEVCB_DRIVER_MEMBER(wicat_state,vram_w), // m_out_memw_cb;
{ DEVCB_NULL,DEVCB_NULL,DEVCB_NULL,DEVCB_NULL }, // m_in_ior_cb[4];
{ DEVCB_DEVICE_MEMBER("video", i8275x_device, dack_w),DEVCB_NULL,DEVCB_NULL,DEVCB_NULL }, // m_out_iow_cb[4];
{ DEVCB_NULL,DEVCB_NULL,DEVCB_NULL,DEVCB_NULL } // m_out_dack_cb[4];
};
static MACHINE_CONFIG_START( wicat, wicat_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68000, XTAL_8MHz)
@ -856,7 +843,12 @@ static MACHINE_CONFIG_START( wicat, wicat_state )
MCFG_CPU_PROGRAM_MAP(wicat_video_mem)
MCFG_CPU_IO_MAP(wicat_video_io)
MCFG_AM9517A_ADD("videodma", XTAL_8MHz, wicat_videodma_intf) // clock is a bit of guess
MCFG_DEVICE_ADD("videodma", AM9517A, XTAL_8MHz) // clock is a bit of guess
MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(wicat_state, dma_hrq_w))
MCFG_AM9517A_OUT_EOP_CB(WRITELINE(wicat_state, dma_nmi_cb))
MCFG_AM9517A_IN_MEMR_CB(READ8(wicat_state, vram_r))
MCFG_AM9517A_OUT_MEMW_CB(WRITE8(wicat_state, vram_w))
MCFG_AM9517A_OUT_IOW_0_CB(DEVWRITE8("video", i8275x_device, dack_w))
MCFG_IM6402_ADD("videouart", 0, 0)
MCFG_IM6402_DR_CALLBACK(WRITELINE(wicat_state, kb_data_ready))

6
src/mess/includes/at.h
View File

@ -161,10 +161,4 @@ public:
UINT32 at_286_a20(bool state);
};
/*----------- defined in machine/at.c -----------*/
extern const am9517a_interface at_dma8237_1_config;
extern const am9517a_interface at_dma8237_2_config;
#endif /* AT_H_ */

2
src/mess/includes/bebox.h
View File

@ -119,8 +119,6 @@ protected:
/*----------- defined in machine/bebox.c -----------*/
extern const am9517a_interface bebox_dma8237_1_config;
extern const am9517a_interface bebox_dma8237_2_config;
extern const ins8250_interface bebox_uart_inteface_0;
extern const ins8250_interface bebox_uart_inteface_1;
extern const ins8250_interface bebox_uart_inteface_2;

55
src/mess/machine/apollo.c
View File

@ -501,28 +501,6 @@ WRITE_LINE_MEMBER(apollo_state::apollo_dma_2_hrq_changed ) {
m_dma8237_2->hack_w(state);
}
static I8237_INTERFACE( apollo_dma8237_1_config )
{
DEVCB_DRIVER_LINE_MEMBER(apollo_state, apollo_dma_1_hrq_changed),
DEVCB_DRIVER_LINE_MEMBER(apollo_state, apollo_dma8237_out_eop),
DEVCB_DRIVER_MEMBER(apollo_state, apollo_dma_read_byte),
DEVCB_DRIVER_MEMBER(apollo_state, apollo_dma_write_byte),
{ DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_0_dack_r), DEVCB_DRIVER_MEMBER(apollo_state, pc_dma8237_1_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_2_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_3_dack_r)},
{ DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_0_dack_w), DEVCB_DRIVER_MEMBER(apollo_state, pc_dma8237_1_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_2_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_3_dack_w)},
{ DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dack0_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dack1_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dack2_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dack3_w) }
};
static I8237_INTERFACE( apollo_dma8237_2_config )
{
DEVCB_DRIVER_LINE_MEMBER(apollo_state, apollo_dma_2_hrq_changed),
DEVCB_NULL,
DEVCB_DRIVER_MEMBER(apollo_state, apollo_dma_read_word),
DEVCB_DRIVER_MEMBER(apollo_state, apollo_dma_write_word),
{ DEVCB_NULL, DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_5_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_6_dack_r), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_7_dack_r) },
{ DEVCB_NULL, DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_5_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_6_dack_w), DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dma8237_7_dack_w) },
{ DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dack4_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dack5_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dack6_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, apollo_state, pc_dack7_w) }
};
READ8_MEMBER( apollo_state::pc_dma8237_0_dack_r ) { return m_isa->dack_r(0); }
READ8_MEMBER( apollo_state::pc_dma8237_1_dack_r ) { return m_isa->dack_r(1); }
READ8_MEMBER( apollo_state::pc_dma8237_2_dack_r ) { return m_isa->dack_r(2); }
@ -790,8 +768,37 @@ MACHINE_CONFIG_FRAGMENT( common )
// configuration MUST be reset first !
MCFG_DEVICE_ADD(APOLLO_CONF_TAG, APOLLO_CONF, 0)
MCFG_I8237_ADD( APOLLO_DMA1_TAG, XTAL_14_31818MHz/3, apollo_dma8237_1_config )
MCFG_I8237_ADD( APOLLO_DMA2_TAG, XTAL_14_31818MHz/3, apollo_dma8237_2_config )
MCFG_DEVICE_ADD( APOLLO_DMA1_TAG, AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(apollo_state, apollo_dma_1_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(apollo_state, apollo_dma8237_out_eop))
MCFG_I8237_IN_MEMR_CB(READ8(apollo_state, apollo_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(apollo_state, apollo_dma_write_byte))
MCFG_I8237_IN_IOR_0_CB(READ8(apollo_state, pc_dma8237_0_dack_r))
MCFG_I8237_IN_IOR_1_CB(READ8(apollo_state, pc_dma8237_1_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(apollo_state, pc_dma8237_2_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(apollo_state, pc_dma8237_3_dack_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(apollo_state, pc_dma8237_0_dack_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(apollo_state, pc_dma8237_1_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(apollo_state, pc_dma8237_2_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(apollo_state, pc_dma8237_3_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(apollo_state, pc_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(apollo_state, pc_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(apollo_state, pc_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(apollo_state, pc_dack3_w))
MCFG_DEVICE_ADD( APOLLO_DMA2_TAG, AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(apollo_state, apollo_dma_2_hrq_changed))
MCFG_I8237_IN_MEMR_CB(READ8(apollo_state, apollo_dma_read_word))
MCFG_I8237_OUT_MEMW_CB(WRITE8(apollo_state, apollo_dma_write_word))
MCFG_I8237_IN_IOR_1_CB(READ8(apollo_state, pc_dma8237_5_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(apollo_state, pc_dma8237_6_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(apollo_state, pc_dma8237_7_dack_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(apollo_state, pc_dma8237_5_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(apollo_state, pc_dma8237_6_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(apollo_state, pc_dma8237_7_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(apollo_state, pc_dack4_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(apollo_state, pc_dack5_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(apollo_state, pc_dack6_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(apollo_state, pc_dack7_w))
MCFG_PIC8259_ADD( APOLLO_PIC1_TAG, WRITELINE(apollo_state,apollo_pic8259_master_set_int_line), VCC, READ8(apollo_state, apollo_pic8259_get_slave_ack))
MCFG_PIC8259_ADD( APOLLO_PIC2_TAG, WRITELINE(apollo_state,apollo_pic8259_slave_set_int_line), GND, NULL)

23
src/mess/machine/at.c
View File

@ -215,29 +215,6 @@ WRITE_LINE_MEMBER( at_state::pc_dack5_w ) { pc_set_dma_channel(5, state); }
WRITE_LINE_MEMBER( at_state::pc_dack6_w ) { pc_set_dma_channel(6, state); }
WRITE_LINE_MEMBER( at_state::pc_dack7_w ) { pc_set_dma_channel(7, state); }
I8237_INTERFACE( at_dma8237_1_config )
{
DEVCB_DEVICE_LINE_MEMBER("dma8237_2", am9517a_device, dreq0_w),
DEVCB_DRIVER_LINE_MEMBER(at_state, at_dma8237_out_eop),
DEVCB_DRIVER_MEMBER(at_state, pc_dma_read_byte),
DEVCB_DRIVER_MEMBER(at_state, pc_dma_write_byte),
{ DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_0_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_1_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_2_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_3_dack_r) },
{ DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_0_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_1_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_2_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_3_dack_w) },
{ DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack3_w) }
};
I8237_INTERFACE( at_dma8237_2_config )
{
DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dma_hrq_changed),
DEVCB_NULL,
DEVCB_DRIVER_MEMBER(at_state, pc_dma_read_word),
DEVCB_DRIVER_MEMBER(at_state, pc_dma_write_word),
{ DEVCB_NULL, DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_5_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_6_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_7_dack_r) },
{ DEVCB_NULL, DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_5_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_6_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_7_dack_w) },
{ DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack4_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack5_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack6_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack7_w) }
};
READ8_MEMBER( at_state::at_portb_r )
{
UINT8 data = m_at_speaker;

25
src/mess/machine/bebox.c
View File

@ -633,31 +633,6 @@ WRITE_LINE_MEMBER(bebox_state::pc_dack1_w){ set_dma_channel(machine(), 1, state)
WRITE_LINE_MEMBER(bebox_state::pc_dack2_w){ set_dma_channel(machine(), 2, state); }
WRITE_LINE_MEMBER(bebox_state::pc_dack3_w){ set_dma_channel(machine(), 3, state); }
I8237_INTERFACE( bebox_dma8237_1_config )
{
DEVCB_DRIVER_LINE_MEMBER(bebox_state,bebox_dma_hrq_changed),
DEVCB_DRIVER_LINE_MEMBER(bebox_state,bebox_dma8237_out_eop),
DEVCB_DRIVER_MEMBER(bebox_state, bebox_dma_read_byte),
DEVCB_DRIVER_MEMBER(bebox_state, bebox_dma_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(bebox_state,bebox_dma8237_fdc_dack_r), DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(bebox_state,bebox_dma8237_fdc_dack_w), DEVCB_NULL },
{ DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack3_w) }
};
I8237_INTERFACE( bebox_dma8237_2_config )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
/*************************************
*
* 8254 PIT

45
src/mess/machine/genpc.c
View File

@ -154,32 +154,6 @@ WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack1_w ) { pc_select_dma_channel(1, st
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack2_w ) { pc_select_dma_channel(2, state); }
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack3_w ) { pc_select_dma_channel(3, state); }
I8237_INTERFACE( pc_dma8237_config )
{
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma_hrq_changed),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma8237_out_eop),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma_read_byte),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma_write_byte),
{ DEVCB_NULL,
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma8237_1_dack_r),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma8237_2_dack_r),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma8237_3_dack_r) },
{ DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma8237_0_dack_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma8237_1_dack_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma8237_2_dack_w),
DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma8237_3_dack_w) },
// DACK's
{ DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dack0_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dack1_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dack2_w),
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dack3_w) }
};
/*************************************************************
*
* pic8259 configuration
@ -432,8 +406,23 @@ static MACHINE_CONFIG_FRAGMENT( ibm5160_mb_config )
MCFG_PIT8253_CLK2(XTAL_14_31818MHz/12) /* pio port c pin 4, and speaker polling enough */
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(ibm5160_mb_device, pc_pit8253_out2_changed))
MCFG_I8237_ADD( "dma8237", XTAL_14_31818MHz/3, pc_dma8237_config )
MCFG_DEVICE_ADD( "dma8237", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(ibm5160_mb_device, pc_dma_hrq_changed))
MCFG_I8237_OUT_EOP_CB(WRITELINE(ibm5160_mb_device, pc_dma8237_out_eop))
MCFG_I8237_IN_MEMR_CB(READ8(ibm5160_mb_device, pc_dma_read_byte))
MCFG_I8237_OUT_MEMW_CB(WRITE8(ibm5160_mb_device, pc_dma_write_byte))
MCFG_I8237_IN_IOR_1_CB(READ8(ibm5160_mb_device, pc_dma8237_1_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(ibm5160_mb_device, pc_dma8237_2_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(ibm5160_mb_device, pc_dma8237_3_dack_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(ibm5160_mb_device, pc_dma8237_0_dack_w))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(ibm5160_mb_device, pc_dma8237_1_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(ibm5160_mb_device, pc_dma8237_2_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(ibm5160_mb_device, pc_dma8237_3_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(ibm5160_mb_device, pc_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(ibm5160_mb_device, pc_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(ibm5160_mb_device, pc_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(ibm5160_mb_device, pc_dack3_w))
MCFG_PIC8259_ADD( "pic8259", INPUTLINE(":maincpu", 0), VCC, NULL )
MCFG_DEVICE_ADD("ppi8255", I8255A, 0)