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netlist: Add CD4011, CD4024, 7407 and CD4053 devices.

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This commit is contained in:
Aaron Giles 2020-07-28 20:43:01 +02:00 committed by couriersud
parent 0cbbbdc846
commit 44e4ea141d
13 changed files with 451 additions and 22 deletions
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1
src/lib/netlist/build/makefile
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@ -155,6 +155,7 @@ NLOBJS := \
$(NLOBJ)/devices/nld_4006.o \
$(NLOBJ)/devices/nld_4013.o \
$(NLOBJ)/devices/nld_4020.o \
$(NLOBJ)/devices/nld_4053.o \
$(NLOBJ)/devices/nld_4066.o \
$(NLOBJ)/devices/nld_4316.o \
$(NLOBJ)/devices/nld_7442.o \

2
src/lib/netlist/devices/net_lib.cpp
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@ -154,6 +154,8 @@ namespace devices
LIB_ENTRY(CD4006_dip)
LIB_ENTRY(CD4020_WI)
LIB_ENTRY(CD4020)
LIB_ENTRY(CD4024)
LIB_ENTRY(CD4053_GATE)
LIB_ENTRY(CD4066_GATE)
LIB_ENTRY(CD4316_GATE)
LIB_ENTRY(4538)

1
src/lib/netlist/devices/net_lib.h
View File

@ -49,6 +49,7 @@ NETLIST_EXTERNAL(ROMS_lib)
#include "nld_4006.h"
#include "nld_4013.h"
#include "nld_4020.h"
#include "nld_4053.h"
#include "nld_4066.h"
#include "nld_4316.h"
#include "nld_74107.h"

71
src/lib/netlist/devices/nld_4020.cpp
View File

@ -13,10 +13,16 @@ namespace netlist
{
namespace devices
{
template <unsigned _LiveBitmask>
NETLIB_OBJECT(CD4020_sub)
{
static constexpr unsigned MAX_BITS = 14;
static constexpr unsigned MAX_BITMASK = (1 << MAX_BITS) - 1;
NETLIB_CONSTRUCTOR_MODEL(CD4020_sub, "CD4XXX")
, m_IP(*this, "IP", NETLIB_DELEGATE(ip))
, m_RESET(*this, "RESET", NETLIB_DELEGATE(reseti))
, m_Q(*this, {"Q1", "_Q2", "_Q3", "Q4", "Q5", "Q6", "Q7", "Q8", "Q9",
"Q10", "Q11", "Q12", "Q13", "Q14"})
, m_cnt(*this, "m_cnt", 0)
@ -33,10 +39,24 @@ namespace netlist
NETLIB_HANDLERI(ip)
{
++m_cnt;
m_cnt &= 0x3fff;
update_outputs(m_cnt);
}
NETLIB_HANDLERI(reseti)
{
if (m_RESET())
{
m_cnt = 0;
m_IP.inactivate();
/* static */ const netlist_time reset_time = netlist_time::from_nsec(140);
for (int i = 0; i < MAX_BITS; i++)
if (((_LiveBitmask >> i) & 1) != 0)
m_Q[i].push(0, reset_time);
}
else
m_IP.activate_hl();
}
public:
void update_outputs(const unsigned cnt) noexcept
{
@ -50,12 +70,13 @@ namespace netlist
NLTIME_FROM_NS(1380), NLTIME_FROM_NS(1480),
};
m_Q[0].push(cnt & 1, out_delayQn[0]);
for (std::size_t i=3; i<14; i++)
m_Q[i].push((cnt >> i) & 1, out_delayQn[i]);
for (int i = 0; i < MAX_BITS; i++)
if (((_LiveBitmask >> i) & 1) != 0)
m_Q[i].push(cnt & 1, out_delayQn[i]);
}
logic_input_t m_IP;
object_array_t<logic_output_t, 14> m_Q;
logic_input_t m_RESET;
object_array_t<logic_output_t, MAX_BITS> m_Q;
state_var<unsigned> m_cnt;
nld_power_pins m_supply;
@ -65,9 +86,9 @@ namespace netlist
{
NETLIB_CONSTRUCTOR_MODEL(CD4020, "CD4XXX")
, m_sub(*this, "sub")
, m_RESET(*this, "RESET", NETLIB_DELEGATE(inputs))
{
register_subalias("IP", m_sub.m_IP);
register_subalias("RESET", m_sub.m_RESET);
register_subalias("Q1", m_sub.m_Q[0]);
register_subalias("Q4", m_sub.m_Q[3]);
register_subalias("Q5", m_sub.m_Q[4]);
@ -86,24 +107,32 @@ namespace netlist
//NETLIB_RESETI() {}
NETLIB_HANDLERI(inputs)
private:
NETLIB_SUB(CD4020_sub)<0x3ff9> m_sub;
};
NETLIB_OBJECT(CD4024)
{
NETLIB_CONSTRUCTOR_MODEL(CD4024, "CD4XXX")
, m_sub(*this, "sub")
{
if (m_RESET())
{
m_sub.m_cnt = 0;
m_sub.m_IP.inactivate();
/* static */ const netlist_time reset_time = netlist_time::from_nsec(140);
m_sub.m_Q[0].push(0, reset_time);
for (std::size_t i=3; i<14; i++)
m_sub.m_Q[i].push(0, reset_time);
}
else
m_sub.m_IP.activate_hl();
register_subalias("IP", m_sub.m_IP);
register_subalias("RESET", m_sub.m_RESET);
register_subalias("Q1", m_sub.m_Q[0]);
register_subalias("Q2", m_sub.m_Q[1]);
register_subalias("Q3", m_sub.m_Q[2]);
register_subalias("Q4", m_sub.m_Q[3]);
register_subalias("Q5", m_sub.m_Q[4]);
register_subalias("Q6", m_sub.m_Q[5]);
register_subalias("Q7", m_sub.m_Q[6]);
register_subalias("VDD", "sub.VDD");
register_subalias("VSS", "sub.VSS");
}
//NETLIB_RESETI() {}
private:
NETLIB_SUB(CD4020_sub) m_sub;
logic_input_t m_RESET;
NETLIB_SUB(CD4020_sub)<0x7f> m_sub;
};
@ -111,5 +140,7 @@ namespace netlist
NETLIB_DEVICE_IMPL(CD4020, "CD4020", "")
NETLIB_DEVICE_IMPL_ALIAS(CD4020_WI, CD4020, "CD4020_WI", "+IP,+RESET,+VDD,+VSS")
NETLIB_DEVICE_IMPL(CD4024, "CD4024", "")
} //namespace devices
} // namespace netlist

16
src/lib/netlist/devices/nld_4020.h
View File

@ -17,6 +17,19 @@
* +--------------+
*
*
* CD4024: 7-Stage Ripple Carry Binary Counters
*
* +--------------+
* IP |1 ++ 14| VDD
* RESET |2 13| NC
* Q7 |3 12| Q1
* Q6 |4 4024 11| Q2
* Q5 |5 10| NC
* Q4 |6 9| Q3
* VSS |7 8| NC
* +--------------+
*
*
* Naming conventions follow Texas Instruments datasheet
*
* FIXME: Timing depends on VDD-VSS
@ -40,4 +53,7 @@
#define CD4020(name) \
NET_REGISTER_DEV(CD4020, name)
#define CD4024(name) \
NET_REGISTER_DEV(CD4024, name)
#endif /* NLD_4020_H_ */

116
src/lib/netlist/devices/nld_4053.cpp Normal file
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@ -0,0 +1,116 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_4053.c
*
*/
#include "nld_4053.h"
#include "netlist/analog/nlid_twoterm.h"
#include "netlist/solver/nld_solver.h"
namespace netlist
{
namespace devices
{
NETLIB_OBJECT(CD4053_GATE)
{
NETLIB_CONSTRUCTOR_MODEL(CD4053_GATE, "CD4XXX")
, m_RX(*this, "RX")
, m_RY(*this, "RY")
, m_select(*this, "S", NETLIB_DELEGATE(controls))
, m_inhibit(*this, "INH", NETLIB_DELEGATE(controls))
, m_base_r(*this, "BASER", nlconst::magic(270.0))
, m_lastx(*this, "m_lastx", false)
, m_lasty(*this, "m_lasty", false)
, m_select_state(*this, "m_select_state", false)
, m_inhibit_state(*this, "m_inhibit_state", false)
, m_supply(*this)
{
connect(m_RX.N(), m_RY.N());
register_subalias("X", m_RX.P());
register_subalias("Y", m_RY.P());
register_subalias("XY", m_RX.N());
}
NETLIB_RESETI()
{
// Start in off condition
// FIXME: is ROFF correct?
m_RX.set_R(plib::reciprocal(exec().gmin()));
m_RY.set_R(plib::reciprocal(exec().gmin()));
}
private:
NETLIB_HANDLERI(controls)
{
bool newx = false, newy = false;
if (!on(m_inhibit, m_inhibit_state))
{
if (!on(m_select, m_select_state))
{
newx = true;
}
else
{
newy = true;
}
}
if (newx != m_lastx)
{
update_state(m_RX, newx);
m_lastx = newx;
}
if (newy != m_lasty)
{
update_state(m_RY, newy);
m_lasty = newy;
}
}
bool on(analog_input_t &input, bool &state)
{
nl_fptype sup = (m_supply.VCC().Q_Analog() - m_supply.GND().Q_Analog());
nl_fptype in = input() - m_supply.GND().Q_Analog();
nl_fptype low = nlconst::magic(0.45) * sup;
nl_fptype high = nlconst::magic(0.55) * sup;
if (in < low)
{
state = false;
}
else if (in > high)
{
state = true;
}
return state;
}
void update_state(analog::NETLIB_SUB(R_base) &R, bool state)
{
nl_fptype Rval = plib::reciprocal(exec().gmin());
if (state)
{
nl_fptype sup = (m_supply.VCC().Q_Analog() - m_supply.GND().Q_Analog());
Rval = m_base_r() * nlconst::magic(5.0) / sup;
}
R.change_state([this, &R, Rval]() -> void { this->m_RX.set_R(Rval);});
}
analog::NETLIB_SUB(R_base) m_RX;
analog::NETLIB_SUB(R_base) m_RY;
analog_input_t m_select;
analog_input_t m_inhibit;
param_fp_t m_base_r;
state_var<bool> m_lastx;
state_var<bool> m_lasty;
state_var<bool> m_select_state;
state_var<bool> m_inhibit_state;
nld_power_pins m_supply;
};
NETLIB_DEVICE_IMPL(CD4053_GATE, "CD4053_GATE", "")
} //namespace devices
} // namespace netlist

35
src/lib/netlist/devices/nld_4053.h Normal file
View File

@ -0,0 +1,35 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_4053.h
*
* CD4053: Triple 2-Channel Analog Multiplexer/Demultiplexer
*
* +--------------+
* INOUTBY |1 ++ 16| VDD
* INOUTBX |2 15| OUTINB
* INOUTCY |3 14| OUTINA
* OUTINC |4 4053 13| INOUTAY
* INOUTCX |5 12| INOUTAX
* INH |6 11| A
* VEE |7 10| B
* VSS |8 9| C
* +--------------+
*
* FIXME: These devices are slow (~125 ns). This is currently not reflected
*
* Naming conventions follow National semiconductor datasheet
*
*/
#ifndef NLD_4053_H_
#define NLD_4053_H_
#include "netlist/nl_setup.h"
// FIXME: Implement pure CMOS version
#define CD4053_GATE(name) \
NET_REGISTER_DEV(CD4053_GATE, name)
#endif /* NLD_4053_H_ */

2
src/lib/netlist/devices/nld_4316.h
View File

@ -9,7 +9,7 @@
* 1Z |1 ++ 16| VCC
* 1Y |2 15| 1S
* 2Y |3 14| 4S
* 2Z |4 4066 13| 4Z
* 2Z |4 4316 13| 4Z
* 2S |5 12| 4Y
* 3S |6 11| 3Y
* /E |7 10| 3Z

31
src/lib/netlist/devices/nld_devinc.h
View File

@ -715,6 +715,17 @@
#define CD4020(...) \
NET_REGISTER_DEVEXT(CD4020, __VA_ARGS__)
// usage : CD4024(name)
#define CD4024(...) \
NET_REGISTER_DEVEXT(CD4024, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_4053.cpp
// ---------------------------------------------------------------------
// usage : CD4053_GATE(name)
#define CD4053_GATE(...) \
NET_REGISTER_DEVEXT(CD4053_GATE, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_4066.cpp
// ---------------------------------------------------------------------
@ -945,6 +956,10 @@
#define TTL_7406_GATE(...) \
NET_REGISTER_DEVEXT(TTL_7406_GATE, __VA_ARGS__)
// usage : TTL_7407_GATE(name)
#define TTL_7407_GATE(...) \
NET_REGISTER_DEVEXT(TTL_7407_GATE, __VA_ARGS__)
// usage : TTL_7408_GATE(name)
#define TTL_7408_GATE(...) \
NET_REGISTER_DEVEXT(TTL_7408_GATE, __VA_ARGS__)
@ -1105,6 +1120,10 @@
#define TTL_7406_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7406_DIP, __VA_ARGS__)
// usage : TTL_7407_DIP(name)
#define TTL_7407_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7407_DIP, __VA_ARGS__)
// usage : TTL_7408_DIP(name)
#define TTL_7408_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7408_DIP, __VA_ARGS__)
@ -1244,6 +1263,10 @@
#define CD4001_DIP(...) \
NET_REGISTER_DEVEXT(CD4001_DIP, __VA_ARGS__)
// usage : CD4011_DIP(name)
#define CD4011_DIP(...) \
NET_REGISTER_DEVEXT(CD4011_DIP, __VA_ARGS__)
// usage : CD4069_DIP(name)
#define CD4069_DIP(...) \
NET_REGISTER_DEVEXT(CD4069_DIP, __VA_ARGS__)
@ -1256,10 +1279,18 @@
#define CD4020_DIP(...) \
NET_REGISTER_DEVEXT(CD4020_DIP, __VA_ARGS__)
// usage : CD4024_DIP(name)
#define CD4024_DIP(...) \
NET_REGISTER_DEVEXT(CD4024_DIP, __VA_ARGS__)
// usage : CD4016_DIP(name)
#define CD4016_DIP(...) \
NET_REGISTER_DEVEXT(CD4016_DIP, __VA_ARGS__)
// usage : CD4053_DIP(name)
#define CD4053_DIP(...) \
NET_REGISTER_DEVEXT(CD4053_DIP, __VA_ARGS__)
// usage : CD4066_DIP(name)
#define CD4066_DIP(...) \
NET_REGISTER_DEVEXT(CD4066_DIP, __VA_ARGS__)

137
src/lib/netlist/macro/nlm_cd4xxx.cpp
View File

@ -39,6 +39,45 @@ static NETLIST_START(CD4001_DIP)
NETLIST_END()
/* CD4011: Quad 2-Input NAND Gates
*
* +--------------+
* A |1 ++ 14| VDD
* B |2 13| H
* J |3 12| G
* K |4 4011 11| M
* C |5 10| L
* D |6 9| F
* VSS |7 8| E
* +--------------+
*
* Naming conventions follow National Semiconductor datasheet
*
* FIXME: Timing depends on VDD-VSS
* This needs a cmos d-a/a-d proxy implementation.
*/
static NETLIST_START(CD4011_DIP)
CD4011_GATE(A)
CD4011_GATE(B)
CD4011_GATE(C)
CD4011_GATE(D)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
DIPPINS( /* +--------------+ */
A.A, /* A |1 ++ 14| VDD */ A.VDD,
A.B, /* B |2 13| H */ D.B,
A.Q, /* J |3 12| G */ D.A,
B.Q, /* K |4 4011 11| M */ D.Q,
B.A, /* C |5 10| L */ C.Q,
B.B, /* D |6 9| F */ C.B,
A.VSS,/* VSS |7 8| E */ C.A
/* +--------------+ */
)
NETLIST_END()
/* CD4020: 14-Stage Ripple Carry Binary Counters
*
* +--------------+
@ -78,6 +117,91 @@ static NETLIST_START(CD4020_DIP)
NETLIST_END()
/* CD4024: 7-Stage Ripple Carry Binary Counters
*
* +--------------+
* IP |1 ++ 14| VDD
* RESET |2 13| NC
* Q7 |3 12| Q1
* Q6 |4 4024 11| Q2
* Q5 |5 10| NC
* Q4 |6 9| Q3
* VSS |7 8| NC
* +--------------+
*
* Naming conventions follow Texas Instruments datasheet
*
* FIXME: Timing depends on VDD-VSS
* This needs a cmos d-a/a-d proxy implementation.
*/
static NETLIST_START(CD4024_DIP)
CD4024(s1)
NC_PIN(NC)
DIPPINS( /* +--------------+ */
s1.IP, /* IP |1 ++ 14| VDD */ s1.VDD,
s1.RESET, /* RESET |2 13| NC */ NC.I,
s1.Q7, /* Q7 |3 12| Q1 */ s1.Q1,
s1.Q6, /* Q6 |4 4024 11| Q2 */ s1.Q2,
s1.Q5, /* Q5 |5 10| NC */ NC.I,
s1.Q4, /* Q4 |6 9| Q3 */ s1.Q3,
s1.VSS, /* VSS |7 8| NC */ NC.I
/* +--------------+ */
)
/*
* IP = (Input pulses)
*/
NETLIST_END()
/* CD4053: Triple 2-Channel Analog Multiplexer/Demultiplexer
*
* +--------------+
* INOUTBY |1 ++ 16| VDD
* INOUTBX |2 15| OUTINB
* INOUTCY |3 14| OUTINA
* OUTINC |4 4053 13| INOUTAY
* INOUTCX |5 12| INOUTAX
* INH |6 11| A
* VEE |7 10| B
* VSS |8 9| C
* +--------------+
*
* FIXME: These devices are slow (~125 ns). THis is currently not reflected
*
* Naming conventions follow National semiconductor datasheet
*
*/
static NETLIST_START(CD4053_DIP)
CD4053_GATE(A)
CD4053_GATE(B)
CD4053_GATE(C)
NET_C(A.VEE, B.VEE, C.VEE)
NET_C(A.VDD, B.VDD, C.VDD)
NET_C(A.VSS, B.VSS, C.VSS)
NET_C(A.INH, B.INH, C.INH)
PARAM(A.BASER, 270.0)
PARAM(B.BASER, 270.0)
PARAM(C.BASER, 270.0)
DIPPINS( /* +--------------+ */
B.Y, /* INOUTBY |1 ++ 16| VDD */ A.VDD,
B.X, /* INOUTBX |2 15| OUTINB */ B.XY,
C.Y, /* INOUTCY |3 14| OUTINA */ A.XY,
C.XY, /* OUTINC |4 4053 13| INOUTAY */ A.Y,
C.X, /* INOUTCX |5 12| INOUTAX */ A.X,
A.INH, /* INH |6 11| A */ A.S,
A.VEE, /* VEE |7 10| B */ B.S,
A.VSS, /* VSS |8 9| C */ C.S
/* +--------------+ */
)
NETLIST_END()
/* CD4066: Quad Bilateral Switch
*
* +--------------+
@ -171,7 +295,7 @@ static NETLIST_START(CD4069_DIP)
CD4069_GATE(E)
CD4069_GATE(F)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, E.VDD)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, F.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
DIPPINS( /* +--------------+ */
@ -318,6 +442,14 @@ NETLIST_START(CD4XXX_lib)
TT_FAMILY("CD4XXX")
TRUTHTABLE_END()
TRUTHTABLE_START(CD4011_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|1|100")
TT_LINE("X,0|1|100")
TT_LINE("1,1|0|100")
TT_FAMILY("CDXXXX")
TRUTHTABLE_END()
TRUTHTABLE_START(CD4069_GATE, 1, 1, "")
TT_HEAD("A|Q ")
TT_LINE("0|1|55")
@ -335,12 +467,15 @@ NETLIST_START(CD4XXX_lib)
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(CD4001_DIP)
LOCAL_LIB_ENTRY(CD4011_DIP)
LOCAL_LIB_ENTRY(CD4069_DIP)
LOCAL_LIB_ENTRY(CD4070_DIP)
/* DIP ONLY */
LOCAL_LIB_ENTRY(CD4020_DIP)
LOCAL_LIB_ENTRY(CD4024_DIP)
LOCAL_LIB_ENTRY(CD4016_DIP)
LOCAL_LIB_ENTRY(CD4053_DIP)
LOCAL_LIB_ENTRY(CD4066_DIP)
LOCAL_LIB_ENTRY(CD4316_DIP)
LOCAL_LIB_ENTRY(CD4538_DIP)

14
src/lib/netlist/macro/nlm_cd4xxx.h
View File

@ -14,7 +14,9 @@
* CD4001_NOR : single gate
* CD4001_DIP : dip package
* CD4020_DIP : dip package (device model in core)
* CD4024_DIP : dip package (device model in core)
* CD4016_DIP : dip package (device model in core)
* CD4053_DIP : dip package (device model in core)
* CD4066_DIP : dip package (device model in core)
*
*/
@ -33,6 +35,12 @@
#define CD4001_DIP(name) \
NET_REGISTER_DEV(CD4001_DIP, name)
#define CD4011_GATE(name) \
NET_REGISTER_DEV(CD4001_GATE, name)
#define CD4011_DIP(name) \
NET_REGISTER_DEV(CD4011_DIP, name)
#define CD4069_GATE(name) \
NET_REGISTER_DEV(CD4069_GATE, name)
@ -52,6 +60,12 @@
#define CD4020_DIP(name) \
NET_REGISTER_DEV(CD4020_DIP, name)
#define CD4024_DIP(name) \
NET_REGISTER_DEV(CD4024_DIP, name)
#define CD4053_DIP(name) \
NET_REGISTER_DEV(CD4053_DIP, name)
#define CD4066_DIP(name) \
NET_REGISTER_DEV(CD4066_DIP, name)

40
src/lib/netlist/macro/nlm_ttl74xx.cpp
View File

@ -163,6 +163,37 @@ static NETLIST_START(TTL_7406_DIP)
)
NETLIST_END()
/*
* DM7407: Hex Buffers with
* High Voltage Open-Collector Outputs
*
* Naming conventions follow Fairchild Semiconductor datasheet
*
*/
static NETLIST_START(TTL_7407_DIP)
TTL_7407_GATE(A)
TTL_7407_GATE(B)
TTL_7407_GATE(C)
TTL_7407_GATE(D)
TTL_7407_GATE(E)
TTL_7407_GATE(F)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
A.Y, /* Y1 |2 13| A6 */ F.A,
B.A, /* A2 |3 12| Y6 */ F.Y,
B.Y, /* Y2 |4 7406 11| A5 */ E.A,
C.A, /* A3 |5 10| Y5 */ E.Y,
C.Y, /* Y3 |6 9| A4 */ D.A,
A.GND,/* GND |7 8| Y4 */ D.Y
/* +--------------+ */
)
NETLIST_END()
/*
* DM7408: Quad 2-Input AND Gates
*
@ -1431,6 +1462,14 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XXOC")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7407_GATE, 1, 1, "")
TT_HEAD("A|Y ")
TT_LINE("0|0|15")
TT_LINE("1|1|23")
/* Open Collector */
TT_FAMILY("74XXOC")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7408_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|0|15")
@ -1886,6 +1925,7 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_7402_DIP)
LOCAL_LIB_ENTRY(TTL_7404_DIP)
LOCAL_LIB_ENTRY(TTL_7406_DIP)
LOCAL_LIB_ENTRY(TTL_7407_DIP)
LOCAL_LIB_ENTRY(TTL_7408_DIP)
LOCAL_LIB_ENTRY(TTL_7410_DIP)
LOCAL_LIB_ENTRY(TTL_7411_DIP)

7
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -65,6 +65,13 @@
NET_REGISTER_DEV(TTL_7406_DIP, name)
#define TTL_7407_GATE(name) \
NET_REGISTER_DEV(TTL_7407_GATE, name)
#define TTL_7407_DIP(name) \
NET_REGISTER_DEV(TTL_7407_DIP, name)
#define TTL_7408_GATE(name) \
NET_REGISTER_DEV(TTL_7408_GATE, name)