diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua
index 359fb71be9d..788e2cd3eb6 100644
--- a/scripts/src/cpu.lua
+++ b/scripts/src/cpu.lua
@@ -1675,34 +1675,34 @@ if (CPUS["M680X0"]~=null or _OPTIONS["with-tools"]) then
 end
 
 --------------------------------------------------
--- Motorola/Freescale dsp56k
---@src/devices/cpu/dsp56k/dsp56k.h,CPUS["DSP56156"] = true
+-- Motorola/Freescale DSP56156
+--@src/devices/cpu/dsp56156/dsp56156.h,CPUS["DSP56156"] = true
 --------------------------------------------------
 
 if (CPUS["DSP56156"]~=null) then
 	files {
-		MAME_DIR .. "src/devices/cpu/dsp56k/dsp56k.cpp",
-		MAME_DIR .. "src/devices/cpu/dsp56k/dsp56k.h",
-		MAME_DIR .. "src/devices/cpu/dsp56k/dsp56mem.cpp",
-		MAME_DIR .. "src/devices/cpu/dsp56k/dsp56mem.h",
-		MAME_DIR .. "src/devices/cpu/dsp56k/dsp56pcu.cpp",
-		MAME_DIR .. "src/devices/cpu/dsp56k/dsp56pcu.h",
-		MAME_DIR .. "src/devices/cpu/dsp56k/dsp56def.h",
-		MAME_DIR .. "src/devices/cpu/dsp56k/dsp56ops.hxx",
+		MAME_DIR .. "src/devices/cpu/dsp56156/dsp56156.cpp",
+		MAME_DIR .. "src/devices/cpu/dsp56156/dsp56156.h",
+		MAME_DIR .. "src/devices/cpu/dsp56156/dsp56mem.cpp",
+		MAME_DIR .. "src/devices/cpu/dsp56156/dsp56mem.h",
+		MAME_DIR .. "src/devices/cpu/dsp56156/dsp56pcu.cpp",
+		MAME_DIR .. "src/devices/cpu/dsp56156/dsp56pcu.h",
+		MAME_DIR .. "src/devices/cpu/dsp56156/dsp56def.h",
+		MAME_DIR .. "src/devices/cpu/dsp56156/dsp56ops.hxx",
 	}
 end
 
 if (CPUS["DSP56156"]~=null or _OPTIONS["with-tools"]) then
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/dsp56dsm.cpp")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/dsp56dsm.h")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/opcode.cpp")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/opcode.h")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/inst.cpp")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/inst.h")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/pmove.cpp")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/pmove.h")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/tables.cpp")
-	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/tables.h")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/dsp56dsm.cpp")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/dsp56dsm.h")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/opcode.cpp")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/opcode.h")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/inst.cpp")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/inst.h")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/pmove.cpp")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/pmove.h")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/tables.cpp")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/tables.h")
 end
 
 --------------------------------------------------
diff --git a/src/devices/cpu/dsp56156/dsp56156.cpp b/src/devices/cpu/dsp56156/dsp56156.cpp
new file mode 100644
index 00000000000..a308e5329bc
--- /dev/null
+++ b/src/devices/cpu/dsp56156/dsp56156.cpp
@@ -0,0 +1,515 @@
+// license:BSD-3-Clause
+// copyright-holders:Andrew Gardner
+/***************************************************************************
+
+    dsp56156.cpp
+    Core implementation for the portable DSP56156 emulator.
+    Written by Andrew Gardner
+
+****************************************************************************
+
+    Note:
+    This CPU emulator is very much a work-in-progress.
+
+    DONE:
+    1:  1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
+       11,  ,  ,  ,  ,  ,  ,18,  ,   ,
+
+    TODO:
+    X 1-6 Explore CORE naming scheme.
+    - 1-9 paragraph 1 : memory access timings
+    - 1-9 Data ALU arithmetic operations generally use fractional two's complement arithmetic
+          (Unsigned numbers are only supported by the multiply and multiply-accumulate instruction)
+    - 1-9 For fractional arithmetic, the 31-bit product is added to the 40-bit contents of A or B.  No pipeline!
+    - 1-10 Two types of rounding: convergent rounding and two's complement rounding.  See status register bit R.
+    - 1-10 Logic unit is 16-bits wide and works on MSP portion of accum register
+    - 1-10 The AGU can implement three types of arithmetic: linear, modulo, and reverse carry.
+    - 1-12 "Two external interrupt pins!!!"
+    - 1-12 Take care of all interrupt priority (IPR) stuff!
+    - 1-19 Memory WAIT states
+    - 1-20 The timer's interesting!
+    - 1-21 Vectored exception requests on the Host Interface!
+***************************************************************************/
+
+#include "emu.h"
+#include "dsp56156.h"
+#include "dsp56dsm.h"
+
+#include "opcode.h"
+
+#include "debugger.h"
+
+#include "dsp56def.h"
+
+/***************************************************************************
+    COMPONENT FUNCTIONALITY
+***************************************************************************/
+/* 1-9 ALU */
+// #include "dsp56alu.h"
+
+/* 1-10 Address Generation Unit (AGU) */
+// #include "dsp56agu.h"
+
+/* 1-11 Program Control Unit (PCU) */
+#include "dsp56pcu.h"
+
+/* 5-1 Host Interface (HI) */
+//#include "dsp56hi.h"
+
+/* 4-8 Memory handlers for on-chip peripheral memory. */
+#include "dsp56mem.h"
+
+
+DEFINE_DEVICE_TYPE_NS(DSP56156, DSP_56156, dsp56156_device, "dsp56156", "Motorola DSP56156")
+
+
+namespace DSP_56156 {
+
+enum
+{
+	// PCU
+	DSP56156_PC=1,
+	DSP56156_SR,
+	DSP56156_LC,
+	DSP56156_LA,
+	DSP56156_SP,
+	DSP56156_OMR,
+
+	// ALU
+	DSP56156_X, DSP56156_Y,
+	DSP56156_A, DSP56156_B,
+
+	// AGU
+	DSP56156_R0,DSP56156_R1,DSP56156_R2,DSP56156_R3,
+	DSP56156_N0,DSP56156_N1,DSP56156_N2,DSP56156_N3,
+	DSP56156_M0,DSP56156_M1,DSP56156_M2,DSP56156_M3,
+	DSP56156_TEMP,
+	DSP56156_STATUS,
+
+	// CPU STACK
+	DSP56156_ST0,
+	DSP56156_ST1,
+	DSP56156_ST2,
+	DSP56156_ST3,
+	DSP56156_ST4,
+	DSP56156_ST5,
+	DSP56156_ST6,
+	DSP56156_ST7,
+	DSP56156_ST8,
+	DSP56156_ST9,
+	DSP56156_ST10,
+	DSP56156_ST11,
+	DSP56156_ST12,
+	DSP56156_ST13,
+	DSP56156_ST14,
+	DSP56156_ST15
+};
+
+
+/****************************************************************************
+ *  Internal Memory Maps
+ ****************************************************************************/
+void dsp56156_device::dsp56156_program_map(address_map &map)
+{
+	map(0x0000, 0x07ff).ram().share("dsk56156_program_ram");   /* 1-5 */
+//  AM_RANGE(0x2f00,0x2fff) AM_ROM                              /* 1-5 PROM reserved memory.  Is this the right spot for it? */
+}
+
+void dsp56156_device::dsp56156_x_data_map(address_map &map)
+{
+	map(0x0000, 0x07ff).ram();                              /* 1-5 */
+	map(0xffc0, 0xffff).rw(FUNC(dsp56156_device::peripheral_register_r), FUNC(dsp56156_device::peripheral_register_w));   /* 1-5 On-chip peripheral registers memory mapped in data space */
+}
+
+
+dsp56156_device::dsp56156_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: cpu_device(mconfig, DSP56156, tag, owner, clock)
+	, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_program_map), this))
+	, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_x_data_map), this))
+	, m_program_ram(*this, "dsk56156_program_ram")
+{
+}
+
+device_memory_interface::space_config_vector dsp56156_device::memory_space_config() const
+{
+	return space_config_vector {
+		std::make_pair(AS_PROGRAM, &m_program_config),
+		std::make_pair(AS_DATA,    &m_data_config)
+	};
+}
+
+/***************************************************************************
+    MEMORY ACCESSORS
+***************************************************************************/
+#define ROPCODE(pc)   cpustate->cache->read_word(pc)
+
+
+/***************************************************************************
+    IRQ HANDLING
+***************************************************************************/
+void dsp56156_device::execute_set_input(int irqline, int state)
+{
+	//logerror("DSP56156 set irq line %d %d\n", irqline, state);
+
+	switch(irqline)
+	{
+		case DSP56156_IRQ_MODA:
+			// TODO: 1-12 Get this triggering right
+			if (irqa_trigger(&m_core))
+				logerror("DSP56156 IRQA is set to fire on the \"Negative Edge\".\n");
+
+			if (state != CLEAR_LINE)
+				m_core.modA_state = true;
+			else
+				m_core.modA_state = false;
+
+			if (m_core.reset_state != true)
+				dsp56156_add_pending_interrupt(&m_core, "IRQA");
+			break;
+
+		case DSP56156_IRQ_MODB:
+			// TODO: 1-12 Get this triggering right
+			if (irqb_trigger(&m_core))
+				logerror("DSP56156 IRQB is set to fire on the \"Negative Edge\".\n");
+
+			if (state != CLEAR_LINE)
+				m_core.modB_state = true;
+			else
+				m_core.modB_state = false;
+
+			if (m_core.reset_state != true)
+				dsp56156_add_pending_interrupt(&m_core, "IRQB");
+			break;
+
+		case DSP56156_IRQ_MODC:
+			if (state != CLEAR_LINE)
+				m_core.modC_state = true;
+			else
+				m_core.modC_state = false;
+
+			// TODO : Set bus mode or whatever
+			break;
+
+		case DSP56156_IRQ_RESET:
+			if (state != CLEAR_LINE)
+				m_core.reset_state = true;
+			else
+			{
+				/* If it changes state from asserted to cleared.  Call the reset function. */
+				if (m_core.reset_state == true)
+					device_reset();
+
+				m_core.reset_state = false;
+			}
+
+			// dsp56156_add_pending_interrupt("Hardware RESET");
+			break;
+
+		default:
+			logerror("DSP56156 setting some weird irq line : %d", irqline);
+			break;
+	}
+
+	/* If the reset line isn't asserted, service interrupts */
+	// TODO: Is it right to immediately service interrupts?
+	//if (cpustate->reset_state != true)
+	//  pcu_service_interrupts();
+}
+
+
+/***************************************************************************
+    INITIALIZATION AND SHUTDOWN
+***************************************************************************/
+void dsp56156_device::agu_init()
+{
+	/* save states - dsp56156_agu members */
+	save_item(NAME(m_core.AGU.r0));
+	save_item(NAME(m_core.AGU.r1));
+	save_item(NAME(m_core.AGU.r2));
+	save_item(NAME(m_core.AGU.r3));
+	save_item(NAME(m_core.AGU.n0));
+	save_item(NAME(m_core.AGU.n1));
+	save_item(NAME(m_core.AGU.n2));
+	save_item(NAME(m_core.AGU.n3));
+	save_item(NAME(m_core.AGU.m0));
+	save_item(NAME(m_core.AGU.m1));
+	save_item(NAME(m_core.AGU.m2));
+	save_item(NAME(m_core.AGU.m3));
+	save_item(NAME(m_core.AGU.temp));
+}
+
+void dsp56156_device::alu_init()
+{
+	/* save states - dsp56156_alu members */
+	save_item(NAME(m_core.ALU.x));
+	save_item(NAME(m_core.ALU.y));
+	save_item(NAME(m_core.ALU.a));
+	save_item(NAME(m_core.ALU.b));
+}
+
+void dsp56156_device::device_start()
+{
+	memset(&m_core, 0, sizeof(m_core));
+
+	m_core.device = this;
+	m_core.program_ram = m_program_ram;
+
+	/* Call specific module inits */
+	pcu_init(&m_core, this);
+	agu_init();
+	alu_init();
+
+	/* HACK - You're not in bootstrap mode upon bootup */
+	m_core.bootstrap_mode = BOOTSTRAP_OFF;
+
+	/* Clear the irq states */
+	m_core.modA_state = false;
+	m_core.modB_state = false;
+	m_core.modC_state = false;
+	m_core.reset_state = false;
+
+	/* save states - dsp56156_core members */
+	save_item(NAME(m_core.modA_state));
+	save_item(NAME(m_core.modB_state));
+	save_item(NAME(m_core.modC_state));
+	save_item(NAME(m_core.reset_state));
+	save_item(NAME(m_core.bootstrap_mode));
+	save_item(NAME(m_core.repFlag));
+	save_item(NAME(m_core.repAddr));
+	save_item(NAME(m_core.ppc));
+	save_item(NAME(m_core.op));
+	save_item(NAME(m_core.interrupt_cycles));
+
+	/* save states - dsp56156_host_interface members */
+	save_item(NAME(m_core.HI.icr));
+	save_item(NAME(m_core.HI.cvr));
+	save_item(NAME(m_core.HI.isr));
+	save_item(NAME(m_core.HI.ivr));
+	save_item(NAME(m_core.HI.trxh));
+	save_item(NAME(m_core.HI.trxl));
+	save_item(NAME(m_core.HI.bootstrap_offset));
+
+	save_item(NAME(m_core.peripheral_ram));
+
+	m_core.program = &space(AS_PROGRAM);
+	m_core.cache = m_core.program->cache<1, -1, ENDIANNESS_LITTLE>();
+	m_core.data = &space(AS_DATA);
+
+	state_add(DSP56156_PC,     "PC", m_core.PCU.pc).formatstr("%04X");
+	state_add(DSP56156_SR,     "SR", m_core.PCU.sr).formatstr("%04X");
+	state_add(DSP56156_LC,     "LC", m_core.PCU.lc).formatstr("%04X");
+	state_add(DSP56156_LA,     "LA", m_core.PCU.la).formatstr("%04X");
+	state_add(DSP56156_SP,     "SP", m_core.PCU.sp).formatstr("%02X");
+	state_add(DSP56156_OMR,    "OMR", m_core.PCU.omr).formatstr("%02X");
+
+	state_add(DSP56156_X,      "X", m_core.ALU.x.d).mask(0xffffffff).formatstr("%9s");
+	state_add(DSP56156_Y,      "Y", m_core.ALU.y.d).mask(0xffffffff).formatstr("%9s");
+
+	state_add(DSP56156_A,      "A", m_core.ALU.a.q).mask(u64(0xffffffffffffffffU)).formatstr("%12s"); /* could benefit from a better mask? */
+	state_add(DSP56156_B,      "B", m_core.ALU.b.q).mask(u64(0xffffffffffffffffU)).formatstr("%12s"); /* could benefit from a better mask? */
+
+	state_add(DSP56156_R0,     "R0", m_core.AGU.r0).formatstr("%04X");
+	state_add(DSP56156_R1,     "R1", m_core.AGU.r1).formatstr("%04X");
+	state_add(DSP56156_R2,     "R2", m_core.AGU.r2).formatstr("%04X");
+	state_add(DSP56156_R3,     "R3", m_core.AGU.r3).formatstr("%04X");
+
+	state_add(DSP56156_N0,     "N0", m_core.AGU.n0).formatstr("%04X");
+	state_add(DSP56156_N1,     "N1", m_core.AGU.n1).formatstr("%04X");
+	state_add(DSP56156_N2,     "N2", m_core.AGU.n2).formatstr("%04X");
+	state_add(DSP56156_N3,     "N3", m_core.AGU.n3).formatstr("%04X");
+
+	state_add(DSP56156_M0,     "M0", m_core.AGU.m0).formatstr("%04X");
+	state_add(DSP56156_M1,     "M1", m_core.AGU.m1).formatstr("%04X");
+	state_add(DSP56156_M2,     "M2", m_core.AGU.m2).formatstr("%04X");
+	state_add(DSP56156_M3,     "M3", m_core.AGU.m3).formatstr("%04X");
+
+	state_add(DSP56156_TEMP,   "TMP", m_core.AGU.temp).formatstr("%04X").noshow();
+	//state_add(DSP56156_STATUS, "STS", STATUS).formatstr("%02X");
+
+	state_add(DSP56156_ST0,    "ST0", m_core.PCU.ss[0].d).formatstr("%08X");
+	state_add(DSP56156_ST1,    "ST1", m_core.PCU.ss[1].d).formatstr("%08X");
+	state_add(DSP56156_ST2,    "ST2", m_core.PCU.ss[2].d).formatstr("%08X");
+	state_add(DSP56156_ST3,    "ST3", m_core.PCU.ss[3].d).formatstr("%08X");
+	state_add(DSP56156_ST4,    "ST4", m_core.PCU.ss[4].d).formatstr("%08X");
+	state_add(DSP56156_ST5,    "ST5", m_core.PCU.ss[5].d).formatstr("%08X");
+	state_add(DSP56156_ST6,    "ST6", m_core.PCU.ss[6].d).formatstr("%08X");
+	state_add(DSP56156_ST7,    "ST7", m_core.PCU.ss[7].d).formatstr("%08X");
+	state_add(DSP56156_ST8,    "ST8", m_core.PCU.ss[8].d).formatstr("%08X");
+	state_add(DSP56156_ST9,    "ST9", m_core.PCU.ss[9].d).formatstr("%08X");
+	state_add(DSP56156_ST10,   "ST10", m_core.PCU.ss[10].d).formatstr("%08X");
+	state_add(DSP56156_ST11,   "ST11", m_core.PCU.ss[11].d).formatstr("%08X");
+	state_add(DSP56156_ST12,   "ST12", m_core.PCU.ss[12].d).formatstr("%08X");
+	state_add(DSP56156_ST13,   "ST13", m_core.PCU.ss[13].d).formatstr("%08X");
+	state_add(DSP56156_ST14,   "ST14", m_core.PCU.ss[14].d).formatstr("%08X");
+	state_add(DSP56156_ST15,   "ST15", m_core.PCU.ss[15].d).formatstr("%08X");
+
+	state_add(STATE_GENPC, "GENPC", m_core.PCU.pc).noshow();
+	state_add(STATE_GENPCBASE, "CURPC", m_core.ppc).noshow();
+	state_add(STATE_GENSP, "GENSP", m_core.PCU.sp).noshow();
+	state_add(STATE_GENFLAGS, "GENFLAGS", m_core.PCU.sr).formatstr("%14s").noshow();
+
+	set_icountptr(m_core.icount);
+}
+
+
+void dsp56156_device::state_string_export(const device_state_entry &entry, std::string &str) const
+{
+	const dsp56156_core *cpustate = &m_core;
+
+	switch (entry.index())
+	{
+		case STATE_GENFLAGS:
+			str = string_format("%s%s %s%s%s%s%s%s%s%s %s%s",
+				/* Status Register */
+				LF_bit(cpustate) ? "L" : ".",
+				FV_bit(cpustate) ? "F" : ".",
+
+				S_bit(cpustate) ? "S" : ".",
+				L_bit(cpustate) ? "L" : ".",
+				E_bit(cpustate) ? "E" : ".",
+				U_bit(cpustate) ? "U" : ".",
+				N_bit(cpustate) ? "N" : ".",
+				Z_bit(cpustate) ? "Z" : ".",
+				V_bit(cpustate) ? "V" : ".",
+				C_bit(cpustate) ? "C" : ".",
+
+				/* Stack Pointer */
+				UF_bit(cpustate) ? "U" : ".",
+				SE_bit(cpustate) ? "S" : ".");
+			break;
+
+		case DSP56156_X:
+			str = string_format("%04x %04x", X1, X0);
+			break;
+
+		case DSP56156_Y:
+			str = string_format("%04x %04x", Y1, Y0);
+			break;
+
+		case DSP56156_A:
+			str = string_format("%02x %04x %04x", A2, A1, A0);
+			break;
+
+		case DSP56156_B:
+			str = string_format("%02x %04x %04x", B2, B1, B0);
+			break;
+	}
+}
+
+/***************************************************************************
+    RESET BEHAVIOR
+***************************************************************************/
+static void agu_reset(dsp56156_core* cpustate)
+{
+	/* FM.4-3 */
+	R0 = 0x0000;
+	R1 = 0x0000;
+	R2 = 0x0000;
+	R3 = 0x0000;
+
+	N0 = 0x0000;
+	N1 = 0x0000;
+	N2 = 0x0000;
+	N3 = 0x0000;
+
+	M0 = 0xffff;
+	M1 = 0xffff;
+	M2 = 0xffff;
+	M3 = 0xffff;
+
+	TEMP = 0x0000;
+}
+
+static void alu_reset(dsp56156_core* cpustate)
+{
+	X = 0x00000000;
+	Y = 0x00000000;
+	A = 0x0000000000;
+	B = 0x0000000000;
+}
+
+void dsp56156_device::device_reset()
+{
+	logerror("DSP56156 reset\n");
+
+	m_core.interrupt_cycles = 0;
+
+	m_core.repFlag = 0;
+	m_core.repAddr = 0x0000;
+
+	pcu_reset(&m_core);
+	mem_reset(&m_core);
+	agu_reset(&m_core);
+	alu_reset(&m_core);
+
+	m_core.ppc = m_core.PCU.pc;
+
+	/* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU locked to the instruction at address 0x0000 */
+	m_core.program->write_word(0x0000, 0x0124);
+}
+
+
+
+/***************************************************************************
+    CORE INCLUDE
+***************************************************************************/
+#include "dsp56ops.hxx"
+
+
+/***************************************************************************
+    CORE EXECUTION LOOP
+***************************************************************************/
+// Execute a single opcode and return how many cycles it took.
+static size_t execute_one_new(dsp56156_core* cpustate)
+{
+	// For MAME
+	cpustate->ppc = PC;
+	if (cpustate->device->machine().debug_flags & DEBUG_FLAG_CALL_HOOK) // FIXME: if this was a member, the helper would work
+		cpustate->device->debug()->instruction_hook(PC);
+
+	cpustate->op = ROPCODE(PC);
+	uint16_t w0 = ROPCODE(PC);
+	uint16_t w1 = ROPCODE(PC + 1);
+
+	Opcode op(w0, w1);
+	op.evaluate(cpustate);
+	PC += op.evalSize();    // Special size function needed to handle jmps, etc.
+
+	// TODO: Currently all operations take up 4 cycles (inst->cycles()).
+	return 4;
+}
+
+void dsp56156_device::execute_run()
+{
+	/* If reset line is asserted, do nothing */
+	if (m_core.reset_state)
+	{
+		m_core.icount = 0;
+		return;
+	}
+
+	/* HACK - if you're in bootstrap mode, simply pretend you ate up all your cycles waiting for data. */
+	if (m_core.bootstrap_mode != BOOTSTRAP_OFF)
+	{
+		m_core.icount = 0;
+		return;
+	}
+
+	//m_core.icount -= m_core.interrupt_cycles;
+	//m_core.interrupt_cycles = 0;
+
+	while(m_core.icount > 0)
+	{
+		execute_one(&m_core);
+		if (0) m_core.icount -= execute_one_new(&m_core);
+		pcu_service_interrupts(&m_core);   // TODO: Is it incorrect to service after each instruction?
+	}
+}
+
+
+std::unique_ptr<util::disasm_interface> dsp56156_device::create_disassembler()
+{
+	return std::make_unique<dsp56156_disassembler>();
+}
+
+} // namespace DSP_56156
diff --git a/src/devices/cpu/dsp56k/dsp56k.h b/src/devices/cpu/dsp56156/dsp56156.h
similarity index 81%
rename from src/devices/cpu/dsp56k/dsp56k.h
rename to src/devices/cpu/dsp56156/dsp56156.h
index bee7c335b03..9276e4e8702 100644
--- a/src/devices/cpu/dsp56k/dsp56k.h
+++ b/src/devices/cpu/dsp56156/dsp56156.h
@@ -2,15 +2,15 @@
 // copyright-holders:Andrew Gardner
 /***************************************************************************
 
-    dsp56k.h
-    Interface file for the portable Motorola/Freescale DSP56k emulator.
+    dsp56156.h
+    Interface file for the portable Motorola/Freescale DSP56156 emulator.
     Written by Andrew Gardner
 
 ***************************************************************************/
 
 
-#ifndef MAME_CPU_DSP56K_DSP56K_H
-#define MAME_CPU_DSP56K_DSP56K_H
+#ifndef MAME_CPU_DSP56156_DSP56156_H
+#define MAME_CPU_DSP56156_DSP56156_H
 
 #pragma once
 
@@ -18,21 +18,21 @@
 
 // IRQ Lines
 // MODA and MODB are also known as IRQA and IRQB
-#define DSP56K_IRQ_MODA  0
-#define DSP56K_IRQ_MODB  1
-#define DSP56K_IRQ_MODC  2
-#define DSP56K_IRQ_RESET 3  /* Is this needed? */
+#define DSP56156_IRQ_MODA  0
+#define DSP56156_IRQ_MODB  1
+#define DSP56156_IRQ_MODC  2
+#define DSP56156_IRQ_RESET 3  /* Is this needed? */
 
 
-namespace DSP56K {
+namespace DSP_56156 {
 
 /***************************************************************************
     STRUCTURES & TYPEDEFS
 ***************************************************************************/
 // 5-4 Host Interface
-struct dsp56k_host_interface
+struct dsp56156_host_interface
 {
-	// **** Dsp56k side **** //
+	// **** DSP56156 side **** //
 	// Host Control Register
 	uint16_t* hcr;
 
@@ -65,7 +65,7 @@ struct dsp56k_host_interface
 };
 
 // 1-9 ALU
-struct dsp56k_data_alu
+struct dsp56156_data_alu
 {
 	// Four 16-bit input registers (can be accessed as 2 32-bit registers)
 	PAIR x;
@@ -82,7 +82,7 @@ struct dsp56k_data_alu
 };
 
 // 1-10 Address Generation Unit (AGU)
-struct dsp56k_agu
+struct dsp56156_agu
 {
 	// Four address registers
 	uint16_t r0;
@@ -112,7 +112,7 @@ struct dsp56k_agu
 };
 
 // 1-11 Program Control Unit (PCU)
-struct dsp56k_pcu
+struct dsp56156_pcu
 {
 	// Program Counter
 	uint16_t pc;
@@ -138,7 +138,7 @@ struct dsp56k_pcu
 	// Controls IRQ processing
 	void (*service_interrupts)(void);
 
-	// A list of pending interrupts (indices into dsp56k_interrupt_sources array)
+	// A list of pending interrupts (indices into dsp56156_interrupt_sources array)
 	int8_t pending_interrupts[32];
 
 	// Basics
@@ -149,26 +149,26 @@ struct dsp56k_pcu
 };
 
 // 1-8 The dsp56156 CORE
-struct dsp56k_core
+struct dsp56156_core
 {
 	// PROGRAM CONTROLLER
-	dsp56k_pcu PCU;
+	dsp56156_pcu PCU;
 
 	// ADR ALU (AGU)
-	dsp56k_agu AGU;
+	dsp56156_agu AGU;
 
 	// CLOCK GEN
-	//static emu_timer *dsp56k_timer;   // 1-5, 1-8 - Clock gen
+	//static emu_timer *dsp56156_timer;   // 1-5, 1-8 - Clock gen
 
 	// DATA ALU
-	dsp56k_data_alu ALU;
+	dsp56156_data_alu ALU;
 
 	// OnCE
 
 	// IBS and BITFIELD UNIT
 
 	// Host Interface
-	dsp56k_host_interface HI;
+	dsp56156_host_interface HI;
 
 	// IRQ line states
 	bool modA_state;
@@ -200,10 +200,10 @@ struct dsp56k_core
 };
 
 
-class dsp56k_device : public cpu_device
+class dsp56156_device : public cpu_device
 {
 public:
-	dsp56k_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
+	dsp56156_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
 
 	DECLARE_READ16_MEMBER( peripheral_register_r );
 	DECLARE_WRITE16_MEMBER( peripheral_register_w );
@@ -226,7 +226,7 @@ protected:
 	virtual uint32_t execute_min_cycles() const override { return 1; }
 	virtual uint32_t execute_max_cycles() const override { return 8; }
 	virtual uint32_t execute_input_lines() const override { return 4; }
-	virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == DSP56K_IRQ_RESET; }
+	virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == DSP56156_IRQ_RESET; }
 	virtual void execute_run() override;
 	virtual void execute_set_input(int inputnum, int state) override;
 
@@ -244,16 +244,16 @@ private:
 	address_space_config m_data_config;
 	required_shared_ptr<uint16_t> m_program_ram;
 
-	dsp56k_core m_dsp56k_core;
+	dsp56156_core m_core;
 
 	void agu_init();
 	void alu_init();
 };
 
-} // namespace DSP56K
+} // namespace DSP_56156
 
 
-DECLARE_DEVICE_TYPE_NS(DSP56156, DSP56K, dsp56k_device)
-using DSP56K::dsp56k_device;
+DECLARE_DEVICE_TYPE_NS(DSP56156, DSP_56156, dsp56156_device)
+using DSP_56156::dsp56156_device;
 
-#endif // MAME_CPU_DSP56K_DSP56K_H
+#endif // MAME_CPU_DSP56156_DSP56156_H
diff --git a/src/devices/cpu/dsp56k/dsp56def.h b/src/devices/cpu/dsp56156/dsp56def.h
similarity index 95%
rename from src/devices/cpu/dsp56k/dsp56def.h
rename to src/devices/cpu/dsp56156/dsp56def.h
index 14fe208dbb8..3ae4dd414ec 100644
--- a/src/devices/cpu/dsp56k/dsp56def.h
+++ b/src/devices/cpu/dsp56156/dsp56def.h
@@ -7,9 +7,9 @@
 #ifndef __DSP56_DEF_H__
 #define __DSP56_DEF_H__
 
-#include "dsp56k.h"
+#include "dsp56156.h"
 
-namespace DSP56K
+namespace DSP_56156
 {
 /***************************************************************************
     ALU
@@ -51,6 +51,6 @@ namespace DSP56K
 
 #define TEMP    cpustate->AGU.temp
 
-} // namespace DSP56K
+} // namespace DSP_56156
 
 #endif
diff --git a/src/devices/cpu/dsp56k/dsp56dsm.cpp b/src/devices/cpu/dsp56156/dsp56dsm.cpp
similarity index 67%
rename from src/devices/cpu/dsp56k/dsp56dsm.cpp
rename to src/devices/cpu/dsp56156/dsp56dsm.cpp
index 847a4bda6a0..58397c3284f 100644
--- a/src/devices/cpu/dsp56k/dsp56dsm.cpp
+++ b/src/devices/cpu/dsp56156/dsp56dsm.cpp
@@ -2,8 +2,8 @@
 // copyright-holders:Andrew Gardner
 /***************************************************************************
 
-    dsp56dsm.c
-    Disassembler for the portable Motorola/Freescale dsp56k emulator.
+    dsp56dsm.cpp
+    Disassembler for the portable Motorola/Freescale DSP56156 emulator.
     Written by Andrew Gardner
 
 ***************************************************************************/
@@ -12,7 +12,7 @@
 #include "opcode.h"
 #include "dsp56dsm.h"
 
-u32 dsp56k_disassembler::opcode_alignment() const
+u32 dsp56156_disassembler::opcode_alignment() const
 {
 	return 1;
 }
@@ -20,13 +20,13 @@ u32 dsp56k_disassembler::opcode_alignment() const
 /*****************************/
 /* Main disassembly function */
 /*****************************/
-offs_t dsp56k_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
+offs_t dsp56156_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
 {
 	const uint16_t w0 = opcodes.r16(pc);
 	const uint16_t w1 = opcodes.r16(pc+1);
 
 	// Decode and disassemble.
-	DSP56K::Opcode op(w0, w1);
+	DSP_56156::Opcode op(w0, w1);
 	stream << op.disassemble();
 
 	const unsigned size = op.size();
diff --git a/src/devices/cpu/dsp56k/dsp56dsm.h b/src/devices/cpu/dsp56156/dsp56dsm.h
similarity index 59%
rename from src/devices/cpu/dsp56k/dsp56dsm.h
rename to src/devices/cpu/dsp56156/dsp56dsm.h
index 3e0f7cb87ff..c750bebfdb1 100644
--- a/src/devices/cpu/dsp56k/dsp56dsm.h
+++ b/src/devices/cpu/dsp56156/dsp56dsm.h
@@ -2,22 +2,22 @@
 // copyright-holders:Andrew Gardner
 /***************************************************************************
 
-    dsp56dsm.c
-    Disassembler for the portable Motorola/Freescale dsp56k emulator.
+    dsp56dsm.cpp
+    Disassembler for the portable Motorola/Freescale DSP56156 emulator.
     Written by Andrew Gardner
 
 ***************************************************************************/
 
-#ifndef MAME_CPU_DSP56K_DSP56DSM_H
-#define MAME_CPU_DSP56K_DSP56DSM_H
+#ifndef MAME_CPU_DSP56156_DSP56156DSM_H
+#define MAME_CPU_DSP56156_DSP56156DSM_H
 
 #pragma once
 
-class dsp56k_disassembler : public util::disasm_interface
+class dsp56156_disassembler : public util::disasm_interface
 {
 public:
-	dsp56k_disassembler() = default;
-	virtual ~dsp56k_disassembler() = default;
+	dsp56156_disassembler() = default;
+	virtual ~dsp56156_disassembler() = default;
 
 	virtual u32 opcode_alignment() const override;
 	virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params) override;
diff --git a/src/devices/cpu/dsp56k/dsp56mem.cpp b/src/devices/cpu/dsp56156/dsp56mem.cpp
similarity index 67%
rename from src/devices/cpu/dsp56k/dsp56mem.cpp
rename to src/devices/cpu/dsp56156/dsp56mem.cpp
index 257865cb325..37e249f15ca 100644
--- a/src/devices/cpu/dsp56k/dsp56mem.cpp
+++ b/src/devices/cpu/dsp56156/dsp56mem.cpp
@@ -7,32 +7,32 @@
 #include "dsp56mem.h"
 #include "dsp56pcu.h"
 
-namespace DSP56K {
+namespace DSP_56156 {
 
 /* IPR Accessor Implementations */
-void IPR_set(dsp56k_core* cpustate, uint16_t value)
+void IPR_set(dsp56156_core* cpustate, uint16_t value)
 {
 	/* TODO: Is there anything else? */
 	IPR = value;
 }
 
-int8_t  irqa_ipl(dsp56k_core* cpustate)   { return ((IPR & 0x0003) >> 0) - 1;  }
-uint8_t irqa_trigger(dsp56k_core* cpustate){ return  (IPR & 0x0004) >> 2;       }
-int8_t  irqb_ipl(dsp56k_core* cpustate)   { return ((IPR & 0x0018) >> 3) - 1;  }
-uint8_t irqb_trigger(dsp56k_core* cpustate){ return  (IPR & 0x0002) >> 5;       }
-int8_t  codec_ipl(dsp56k_core* cpustate)  { return ((IPR & 0x00c0) >> 6) - 1;  }
-int8_t  host_ipl(dsp56k_core* cpustate)   { return ((IPR & 0x0300) >> 8) - 1;  }
-int8_t  ssi0_ipl(dsp56k_core* cpustate)   { return ((IPR & 0x0c00) >> 10) - 1; }
-int8_t  ssi1_ipl(dsp56k_core* cpustate)   { return ((IPR & 0x3000) >> 12) - 1; }
-int8_t  tm_ipl(dsp56k_core* cpustate)     { return ((IPR & 0xc000) >> 14) - 1; }
+int8_t  irqa_ipl(dsp56156_core* cpustate)   { return ((IPR & 0x0003) >> 0) - 1;  }
+uint8_t irqa_trigger(dsp56156_core* cpustate){ return  (IPR & 0x0004) >> 2;       }
+int8_t  irqb_ipl(dsp56156_core* cpustate)   { return ((IPR & 0x0018) >> 3) - 1;  }
+uint8_t irqb_trigger(dsp56156_core* cpustate){ return  (IPR & 0x0002) >> 5;       }
+int8_t  codec_ipl(dsp56156_core* cpustate)  { return ((IPR & 0x00c0) >> 6) - 1;  }
+int8_t  host_ipl(dsp56156_core* cpustate)   { return ((IPR & 0x0300) >> 8) - 1;  }
+int8_t  ssi0_ipl(dsp56156_core* cpustate)   { return ((IPR & 0x0c00) >> 10) - 1; }
+int8_t  ssi1_ipl(dsp56156_core* cpustate)   { return ((IPR & 0x3000) >> 12) - 1; }
+int8_t  tm_ipl(dsp56156_core* cpustate)     { return ((IPR & 0xc000) >> 14) - 1; }
 
-void mem_reset(dsp56k_core* cpustate)
+void mem_reset(dsp56156_core* cpustate)
 {
 	// Reset the HI registers
-	dsp56k_host_interface_reset(cpustate);
+	dsp56156_host_interface_reset(cpustate);
 
 	// Reset the IO registers
-	dsp56k_io_reset(cpustate);
+	dsp56156_io_reset(cpustate);
 }
 
 
@@ -45,7 +45,7 @@ void mem_reset(dsp56k_core* cpustate)
 /************************************/
 /* Host Control Register (HCR) Bits */
 /************************************/
-void HCR_set(dsp56k_core* cpustate, uint16_t value)
+void HCR_set(dsp56156_core* cpustate, uint16_t value)
 {
 	HF3_bit_set (cpustate, (value & 0x0010) >> 4);
 	HF2_bit_set (cpustate, (value & 0x0008) >> 3);
@@ -53,13 +53,13 @@ void HCR_set(dsp56k_core* cpustate, uint16_t value)
 	HTIE_bit_set(cpustate, (value & 0x0002) >> 1);
 	HRIE_bit_set(cpustate, (value & 0x0001) >> 0);
 }
-//uint16_t HF3_bit(dsp56k_core* cpustate) { return ((HCR & 0x0010) != 0); }
-//uint16_t HF2_bit(dsp56k_core* cpustate) { return ((HCR & 0x0008) != 0); }
-uint16_t HCIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0004) != 0); }
-uint16_t HTIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0002) != 0); }
-uint16_t HRIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0001) != 0); }
+//uint16_t HF3_bit(dsp56156_core* cpustate) { return ((HCR & 0x0010) != 0); }
+//uint16_t HF2_bit(dsp56156_core* cpustate) { return ((HCR & 0x0008) != 0); }
+uint16_t HCIE_bit(dsp56156_core* cpustate) { return ((HCR & 0x0004) != 0); }
+uint16_t HTIE_bit(dsp56156_core* cpustate) { return ((HCR & 0x0002) != 0); }
+uint16_t HRIE_bit(dsp56156_core* cpustate) { return ((HCR & 0x0001) != 0); }
 
-void HF3_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HF3_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HCR &= ~(0x0010);
@@ -67,7 +67,7 @@ void HF3_bit_set(dsp56k_core* cpustate, uint16_t value)
 
 	HF3_bit_host_set(cpustate, value);
 }
-void HF2_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HF2_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HCR &= ~(0x0008);
@@ -75,19 +75,19 @@ void HF2_bit_set(dsp56k_core* cpustate, uint16_t value)
 
 	HF2_bit_host_set(cpustate, value);
 }
-void HCIE_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HCIE_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HCR &= ~(0x0004);
 	HCR |=  (value << 2);
 }
-void HTIE_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HTIE_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HCR &= ~(0x0002);
 	HCR |=  (value << 1);
 }
-void HRIE_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HRIE_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HCR &= ~(0x0001);
@@ -97,42 +97,42 @@ void HRIE_bit_set(dsp56k_core* cpustate, uint16_t value)
 /***********************************/
 /* Host Status Register (HSR) Bits */
 /***********************************/
-//uint16_t DMA_bit(dsp56k_core* cpustate) { return ((HSR & 0x0080) != 0); }
-//uint16_t HF1_bit(dsp56k_core* cpustate) { return ((HSR & 0x0010) != 0); }
-//uint16_t HF0_bit(dsp56k_core* cpustate) { return ((HSR & 0x0008) != 0); }
-//uint16_t HCP_bit(dsp56k_core* cpustate) { return ((HSR & 0x0004) != 0); }
-uint16_t HTDE_bit(dsp56k_core* cpustate) { return ((HSR & 0x0002) != 0); }
-uint16_t HRDF_bit(dsp56k_core* cpustate) { return ((HSR & 0x0001) != 0); }
+//uint16_t DMA_bit(dsp56156_core* cpustate) { return ((HSR & 0x0080) != 0); }
+//uint16_t HF1_bit(dsp56156_core* cpustate) { return ((HSR & 0x0010) != 0); }
+//uint16_t HF0_bit(dsp56156_core* cpustate) { return ((HSR & 0x0008) != 0); }
+//uint16_t HCP_bit(dsp56156_core* cpustate) { return ((HSR & 0x0004) != 0); }
+uint16_t HTDE_bit(dsp56156_core* cpustate) { return ((HSR & 0x0002) != 0); }
+uint16_t HRDF_bit(dsp56156_core* cpustate) { return ((HSR & 0x0001) != 0); }
 
-void DMA_bit_set(dsp56k_core* cpustate, uint16_t value)
+void DMA_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HSR &= ~(0x0080);
 	HSR |= (value << 7);
 	// TODO: 5-12 When the DMA bit is set, the DMA mode is enabled by the Host Mode bits HM0 & HM1
 }
-void HF1_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HF1_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HSR &= ~(0x0010);
 	HSR |= (value << 4);
 }
-void HF0_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HF0_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HSR &= ~(0x0008);
 	HSR |= (value << 3);
 }
-void HCP_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HCP_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HSR &= ~(0x0004);
 	HSR |=  (value << 2);
 
 	if (value && HCIE_bit(cpustate))
-		dsp56k_add_pending_interrupt(cpustate, "Host Command");
+		dsp56156_add_pending_interrupt(cpustate, "Host Command");
 }
-void HTDE_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HTDE_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HSR &= ~(0x0002);
@@ -140,13 +140,13 @@ void HTDE_bit_set(dsp56k_core* cpustate, uint16_t value)
 
 	// 5-10 If HTIE bit is set, whip out a Host Transmit Data interrupt
 	if (value && HTIE_bit(cpustate))
-		dsp56k_add_pending_interrupt(cpustate, "Host Transmit Data");
+		dsp56156_add_pending_interrupt(cpustate, "Host Transmit Data");
 
 	// 5-5 If both me and RXDF are cleared, transmit data to the host
 	if (!value && !RXDF_bit(cpustate))
-		dsp56k_host_interface_HTX_to_host(cpustate);
+		dsp56156_host_interface_HTX_to_host(cpustate);
 }
-void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value)
+void HRDF_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x01;
 	HSR &= ~(0x0001);
@@ -154,11 +154,11 @@ void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value)
 
 	// 5-10 If HRIE is set, whip out a Host Receive Data interrupt
 	if (value && HRIE_bit(cpustate))
-		dsp56k_add_pending_interrupt(cpustate, "Host Receive Data");
+		dsp56156_add_pending_interrupt(cpustate, "Host Receive Data");
 
-	// 5-5 If both me and TXDE are cleared, transmit data to the dsp56k
+	// 5-5 If both me and TXDE are cleared, transmit data to the dsp56156
 	if (!value && !TXDE_bit(cpustate))
-		dsp56k_host_interface_host_to_HTX(cpustate);
+		dsp56156_host_interface_host_to_HTX(cpustate);
 }
 
 
@@ -169,7 +169,7 @@ void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value)
 /*****************************************/
 /* Interrupt Control Register (ICR) Bits */
 /*****************************************/
-void ICR_set(dsp56k_core* cpustate, uint8_t value)
+void ICR_set(dsp56156_core* cpustate, uint8_t value)
 {
 	HF1_bit_host_set(cpustate, (value & 0x10) >> 4);
 	HF0_bit_host_set(cpustate, (value & 0x08) >> 3);
@@ -177,18 +177,18 @@ void ICR_set(dsp56k_core* cpustate, uint8_t value)
 	RREQ_bit_set(cpustate, (value & 0x01) >> 0);
 }
 
-//uint8_t INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0)
-//uint8_t HM1_bit(dsp56k_core* cpustate);  #define x_hm1BIT  ((dsp56k.HI.ICR & 0x0040) != 0)
-//uint8_t HM0_bit(dsp56k_core* cpustate);  #define x_hm0BIT  ((dsp56k.HI.ICR & 0x0020) != 0)
-//uint8_t HF1_bit_host(dsp56k_core* cpustate);  #define x_hf1BIT  ((dsp56k.HI.ICR & 0x0010) != 0)
-//uint8_t HF0_bit_host(dsp56k_core* cpustate);  #define x_hf0BIT  ((dsp56k.HI.ICR & 0x0008) != 0)
-//uint8_t TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0)
-//uint8_t RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0)
+//uint8_t INIT_bit(dsp56156_core* cpustate); #define x_initBIT ((dsp56156.HI.ICR & 0x0080) != 0)
+//uint8_t HM1_bit(dsp56156_core* cpustate);  #define x_hm1BIT  ((dsp56156.HI.ICR & 0x0040) != 0)
+//uint8_t HM0_bit(dsp56156_core* cpustate);  #define x_hm0BIT  ((dsp56156.HI.ICR & 0x0020) != 0)
+//uint8_t HF1_bit_host(dsp56156_core* cpustate);  #define x_hf1BIT  ((dsp56156.HI.ICR & 0x0010) != 0)
+//uint8_t HF0_bit_host(dsp56156_core* cpustate);  #define x_hf0BIT  ((dsp56156.HI.ICR & 0x0008) != 0)
+//uint8_t TREQ_bit(dsp56156_core* cpustate); #define x_treqBIT ((dsp56156.HI.ICR & 0x0002) != 0)
+//uint8_t RREQ_bit(dsp56156_core* cpustate); #define x_rreqBIT ((dsp56156.HI.ICR & 0x0001) != 0)
 
-//void INIT_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080))
-//void HM1_bit_set(dsp56k_core* cpustate, uint8_t value);  #define CLEAR_x_hm1BIT()  (dsp56k.HI.ICR &= (~0x0040))
-//void HM0_bit_set(dsp56k_core* cpustate, uint8_t value);  #define CLEAR_x_hm0BIT()  (dsp56k.HI.ICR &= (~0x0020))
-void HF1_bit_host_set(dsp56k_core* cpustate, uint8_t value)
+//void INIT_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56156.HI.ICR &= (~0x0080))
+//void HM1_bit_set(dsp56156_core* cpustate, uint8_t value);  #define CLEAR_x_hm1BIT()  (dsp56156.HI.ICR &= (~0x0040))
+//void HM0_bit_set(dsp56156_core* cpustate, uint8_t value);  #define CLEAR_x_hm0BIT()  (dsp56156.HI.ICR &= (~0x0020))
+void HF1_bit_host_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	ICR &= ~(0x10);
@@ -196,7 +196,7 @@ void HF1_bit_host_set(dsp56k_core* cpustate, uint8_t value)
 
 	HF1_bit_set(cpustate, value);       // 5-14
 }
-void HF0_bit_host_set(dsp56k_core* cpustate, uint8_t value)
+void HF0_bit_host_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	ICR &= ~(0x08);
@@ -204,13 +204,13 @@ void HF0_bit_host_set(dsp56k_core* cpustate, uint8_t value)
 
 	HF0_bit_set(cpustate, value);       // 5-13
 }
-void TREQ_bit_set(dsp56k_core* cpustate, uint8_t value)
+void TREQ_bit_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	ICR &= ~(0x02);
 	ICR |=  (value << 1);
 }
-void RREQ_bit_set(dsp56k_core* cpustate, uint8_t value)
+void RREQ_bit_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	ICR &= ~(0x01);
@@ -228,16 +228,16 @@ void RREQ_bit_set(dsp56k_core* cpustate, uint8_t value)
 /**************************************/
 /* Command Vector Register (CVR) Bits */
 /**************************************/
-uint8_t HV_bits(dsp56k_core* cpustate) { return (CVR & 0x1f); }
+uint8_t HV_bits(dsp56156_core* cpustate) { return (CVR & 0x1f); }
 
-void CVR_set(dsp56k_core* cpustate, uint8_t value)
+void CVR_set(dsp56156_core* cpustate, uint8_t value)
 {
 	/* A single, unified place to run all callbacks for each of the bits */
 	HC_bit_set(cpustate, (value & 0x80) >> 7);
 	HV_bits_set(cpustate, (value & 0x1f));
 }
 
-void HC_bit_set(dsp56k_core* cpustate, uint8_t value)
+void HC_bit_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	CVR &= ~(0x80);
@@ -245,7 +245,7 @@ void HC_bit_set(dsp56k_core* cpustate, uint8_t value)
 
 	HCP_bit_set(cpustate, value);   // 5-9 & 5-11
 }
-void HV_bits_set(dsp56k_core* cpustate, uint8_t value)
+void HV_bits_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x1f;
 	CVR &= ~(0x1f);
@@ -256,34 +256,34 @@ void HV_bits_set(dsp56k_core* cpustate, uint8_t value)
 /****************************************/
 /* Interrupt Status Register (ISR) Bits */
 /****************************************/
-uint8_t TXDE_bit(dsp56k_core* cpustate) { return ((ISR & 0x0002) != 0); }
-uint8_t RXDF_bit(dsp56k_core* cpustate) { return ((ISR & 0x0001) != 0); }
+uint8_t TXDE_bit(dsp56156_core* cpustate) { return ((ISR & 0x0002) != 0); }
+uint8_t RXDF_bit(dsp56156_core* cpustate) { return ((ISR & 0x0001) != 0); }
 
-void HF3_bit_host_set(dsp56k_core* cpustate, uint8_t value)
+void HF3_bit_host_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	ISR &= ~(0x0010);
 	ISR |=  (value << 4);
 }
-void HF2_bit_host_set(dsp56k_core* cpustate, uint8_t value)
+void HF2_bit_host_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	ISR &= ~(0x0008);
 	ISR |=  (value << 3);
 }
 
-void TXDE_bit_set(dsp56k_core* cpustate, uint8_t value)
+void TXDE_bit_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	ISR &= ~(0x0002);
 	ISR |=  (value << 1);
 
-	// If both me and the HRDF are cleared, transmit data to the dsp56k
+	// If both me and the HRDF are cleared, transmit data to the dsp56156
 	if (!value && !HRDF_bit(cpustate))
-		dsp56k_host_interface_host_to_HTX(cpustate);
+		dsp56156_host_interface_host_to_HTX(cpustate);
 }
 
-void RXDF_bit_set(dsp56k_core* cpustate, uint8_t value)
+void RXDF_bit_set(dsp56156_core* cpustate, uint8_t value)
 {
 	value = value & 0x01;
 	ISR &= ~(0x0001);
@@ -291,13 +291,13 @@ void RXDF_bit_set(dsp56k_core* cpustate, uint8_t value)
 
 	// If both me and HTDE are cleared, transmit data to the host
 	if (!value && !HTDE_bit(cpustate))
-		dsp56k_host_interface_HTX_to_host(cpustate);
+		dsp56156_host_interface_HTX_to_host(cpustate);
 }
 
 
 // TODO: 5-11 What is the host processor Initialize function?
 
-void dsp56k_host_interface_reset(dsp56k_core* cpustate)
+void dsp56156_host_interface_reset(dsp56156_core* cpustate)
 {
 	// Hook up the CPU-side pointers properly.
 	cpustate->HI.hcr = &cpustate->peripheral_ram[A2O(0xffc4)];
@@ -325,7 +325,7 @@ void dsp56k_host_interface_reset(dsp56k_core* cpustate)
 	/* TODO: ISR (at least) */
 }
 
-void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate)
+void dsp56156_host_interface_HTX_to_host(dsp56156_core* cpustate)
 {
 	RXH = ((HTX & 0xff00) >> 8);
 	RXL = ((HTX & 0x00ff));
@@ -333,7 +333,7 @@ void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate)
 	HTDE_bit_set(cpustate, 1);
 }
 
-void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate)
+void dsp56156_host_interface_host_to_HTX(dsp56156_core* cpustate)
 {
 	HRX &= 0x00ff;
 	HRX |= (TXH << 8);
@@ -348,7 +348,7 @@ void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate)
     I/O INTERFACE
 ***************************************************************************/
 /* BCR */
-void BCR_set(dsp56k_core* cpustate, uint16_t value)
+void BCR_set(dsp56156_core* cpustate, uint16_t value)
 {
 	RH_bit_set(cpustate, (value & 0x8000) >> 15);
 	BS_bit_set(cpustate, (value & 0x4000) >> 14);
@@ -356,12 +356,12 @@ void BCR_set(dsp56k_core* cpustate, uint16_t value)
 	external_p_wait_states_set(cpustate, (value & 0x001f) >> 0);
 }
 
-//uint16_t RH_bit(dsp56k_core* cpustate);
-//uint16_t BS_bit(dsp56k_core* cpustate);
-//uint16_t external_x_wait_states(dsp56k_core* cpustate);
-//uint16_t external_p_wait_states(dsp56k_core* cpustate);
+//uint16_t RH_bit(dsp56156_core* cpustate);
+//uint16_t BS_bit(dsp56156_core* cpustate);
+//uint16_t external_x_wait_states(dsp56156_core* cpustate);
+//uint16_t external_p_wait_states(dsp56156_core* cpustate);
 
-void RH_bit_set(dsp56k_core* cpustate, uint16_t value)
+void RH_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x0001;
 	BCR &= ~(0x8000);
@@ -369,7 +369,7 @@ void RH_bit_set(dsp56k_core* cpustate, uint16_t value)
 
 	// TODO: 4-6 Assert BR pin?
 }
-void BS_bit_set(dsp56k_core* cpustate, uint16_t value)
+void BS_bit_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x0001;
 	BCR &= ~(0x4000);
@@ -377,13 +377,13 @@ void BS_bit_set(dsp56k_core* cpustate, uint16_t value)
 
 	// TODO: 4-6 Respond to BR pin?
 }
-void external_x_wait_states_set(dsp56k_core* cpustate, uint16_t value)
+void external_x_wait_states_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x001f;
 	BCR &= ~(0x03e0);
 	BCR |= (value << 5);
 }
-void external_p_wait_states_set(dsp56k_core* cpustate, uint16_t value)
+void external_p_wait_states_set(dsp56156_core* cpustate, uint16_t value)
 {
 	value = value & 0x001f;
 	BCR &= ~(0x001f);
@@ -392,7 +392,7 @@ void external_p_wait_states_set(dsp56k_core* cpustate, uint16_t value)
 
 
 /* Port B Control Register PBC */
-void PBC_set(dsp56k_core* cpustate, uint16_t value)
+void PBC_set(dsp56156_core* cpustate, uint16_t value)
 {
 	if (value & 0xfffe)
 		cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBC.  Ignoring.\n");
@@ -403,7 +403,7 @@ void PBC_set(dsp56k_core* cpustate, uint16_t value)
 }
 
 #ifdef UNUSED_FUNCTION
-int host_interface_active(dsp56k_core* cpustate)
+int host_interface_active(dsp56156_core* cpustate)
 {
 	/* The host interface is active if the 0th bit in the PBC is set */
 	return PBC & 0x0001;
@@ -411,7 +411,7 @@ int host_interface_active(dsp56k_core* cpustate)
 #endif
 
 /* Port B Data Direction Register (PBDDR) */
-void PBDDR_set(dsp56k_core* cpustate, uint16_t value)
+void PBDDR_set(dsp56156_core* cpustate, uint16_t value)
 {
 	if (value & 0x8000)
 		cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBDDR.  Ignoring.\n");
@@ -420,11 +420,11 @@ void PBDDR_set(dsp56k_core* cpustate, uint16_t value)
 	PBDDR &= ~(0x7fff);
 	PBDDR |= (value << 0);
 
-	/* TODO: Implement dsp56k io restrictions, etc. */
+	/* TODO: Implement dsp56156 io restrictions, etc. */
 }
 
 /* Port B Data Register (PBD) */
-void PBD_set(dsp56k_core* cpustate, uint16_t value)
+void PBD_set(dsp56156_core* cpustate, uint16_t value)
 {
 	if (value & 0x8000)
 		cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBD.  Ignoring.\n");
@@ -433,11 +433,11 @@ void PBD_set(dsp56k_core* cpustate, uint16_t value)
 	PBD &= ~(0x7fff);
 	PBD |= (value << 0);
 
-	/* TODO: Implement dsp56k io restrictions, etc. */
+	/* TODO: Implement dsp56156 io restrictions, etc. */
 }
 
 /* Port C Control Register (PCC) */
-void PCC_set(dsp56k_core* cpustate, uint16_t value)
+void PCC_set(dsp56156_core* cpustate, uint16_t value)
 {
 	if (value & 0xf000)
 		cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCC.  Ignoring.\n");
@@ -446,11 +446,11 @@ void PCC_set(dsp56k_core* cpustate, uint16_t value)
 	PCC &= ~(0x0fff);
 	PCC |= (value << 0);
 
-	/* TODO: Implement dsp56k timer and control glue */
+	/* TODO: Implement dsp56156 timer and control glue */
 }
 
 /* Port C Data Direction Register (PCDDR) */
-void PCDDR_set(dsp56k_core* cpustate, uint16_t value)
+void PCDDR_set(dsp56156_core* cpustate, uint16_t value)
 {
 	if (value & 0xf000)
 		cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCDDR.  Ignoring.\n");
@@ -459,11 +459,11 @@ void PCDDR_set(dsp56k_core* cpustate, uint16_t value)
 	PCDDR &= ~(0x0fff);
 	PCDDR |= (value << 0);
 
-	/* TODO: Implement dsp56k io restrictions, etc. */
+	/* TODO: Implement dsp56156 io restrictions, etc. */
 }
 
 /* Port C Data Register (PCD) */
-void PCD_set(dsp56k_core* cpustate, uint16_t value)
+void PCD_set(dsp56156_core* cpustate, uint16_t value)
 {
 	if (value & 0xf000)
 		cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCD.  Ignoring.\n");
@@ -476,7 +476,7 @@ void PCD_set(dsp56k_core* cpustate, uint16_t value)
 	PCD |= (value << 0);
 }
 
-void dsp56k_io_reset(dsp56k_core* cpustate)
+void dsp56156_io_reset(dsp56156_core* cpustate)
 {
 	/* The BCR = 0x43ff */
 	RH_bit_set(cpustate, 0);
@@ -487,9 +487,9 @@ void dsp56k_io_reset(dsp56k_core* cpustate)
 
 
 /* Work */
-READ16_MEMBER( dsp56k_device::peripheral_register_r )
+READ16_MEMBER( dsp56156_device::peripheral_register_r )
 {
-	dsp56k_core* cpustate = &m_dsp56k_core;
+	dsp56156_core* cpustate = &m_core;
 	// (printf) cpustate->device->logerror("Peripheral read 0x%04x\n", O2A(offset));
 
 	switch (O2A(offset))
@@ -551,12 +551,12 @@ READ16_MEMBER( dsp56k_device::peripheral_register_r )
 		// HTX/HRX: Host TX/RX Register
 		case 0xffe5:
 			// 5-5
-			if (!DSP56K::HRDF_bit(cpustate))
+			if (!DSP_56156::HRDF_bit(cpustate))
 				return 0xbeef;
 			else
 			{
 				uint16_t value = HRX;     // TODO: Maybe not exactly right?  Just being safe.
-				DSP56K::HRDF_bit_set(cpustate, 0);
+				DSP_56156::HRDF_bit_set(cpustate, 0);
 				return value;
 			}
 		// COSR
@@ -621,9 +621,9 @@ READ16_MEMBER( dsp56k_device::peripheral_register_r )
 	return cpustate->peripheral_ram[offset];
 }
 
-WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
+WRITE16_MEMBER( dsp56156_device::peripheral_register_w )
 {
-	dsp56k_core* cpustate = &m_dsp56k_core;
+	dsp56156_core* cpustate = &m_core;
 
 	// Its primary behavior is RAM
 	// COMBINE_DATA(&cpustate->peripheral_ram[offset]);
@@ -635,27 +635,27 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
 	{
 		// Port B Control Register (PBC)
 		case 0xffc0:
-			DSP56K::PBC_set(cpustate, data);
+			DSP_56156::PBC_set(cpustate, data);
 			break;
 
 		// Port C Control Register (PCC)
 		case 0xffc1:
-			DSP56K::PCC_set(cpustate, data);
+			DSP_56156::PCC_set(cpustate, data);
 			break;
 
 		// Port B Data Direction Register (PBDDR)
 		case 0xffc2:
-			DSP56K::PBDDR_set(cpustate, data);
+			DSP_56156::PBDDR_set(cpustate, data);
 			break;
 
 		// Port C Data Direction Register (PCDDR)
 		case 0xffc3:
-			DSP56K::PCDDR_set(cpustate, data);
+			DSP_56156::PCDDR_set(cpustate, data);
 			break;
 
 		// HCR: Host Control Register
 		case 0xffc4:
-			DSP56K::HCR_set(cpustate, data);
+			DSP_56156::HCR_set(cpustate, data);
 			break;
 
 		// COCR
@@ -688,22 +688,22 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
 
 		// BCR: Bus Control Register
 		case 0xffde:
-			DSP56K::BCR_set(cpustate, data);
+			DSP_56156::BCR_set(cpustate, data);
 			break;
 
 		// IPR: Interrupt Priority Register
 		case 0xffdf:
-			DSP56K::IPR_set(cpustate, data);
+			DSP_56156::IPR_set(cpustate, data);
 			break;
 
 		// Port B Data Register (PBD)
 		case 0xffe2:
-			DSP56K::PBD_set(cpustate, data);
+			DSP_56156::PBD_set(cpustate, data);
 			break;
 
 		// Port C Data Register (PCD)
 		case 0xffe3:
-			DSP56K::PCD_set(cpustate, data);
+			DSP_56156::PCD_set(cpustate, data);
 			break;
 
 		// HSR: Host Status Register
@@ -712,7 +712,7 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
 		// HTX/HRX: Host TX/RX Register
 		case 0xffe5:
 			HTX = data;
-			DSP56K::HTDE_bit_set(cpustate, 0);  // 5-5
+			DSP_56156::HTDE_bit_set(cpustate, 0);  // 5-5
 			break;
 
 		// COSR
@@ -777,10 +777,10 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
 }
 
 /* These two functions are exposed to the outside world */
-/* They represent the host side of the dsp56k's host interface */
-void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
+/* They represent the host side of the dsp56156's host interface */
+void dsp56156_device::host_interface_write(uint8_t offset, uint8_t data)
 {
-	dsp56k_core* cpustate = &m_dsp56k_core;
+	dsp56156_core* cpustate = &m_core;
 
 	/* Not exactly correct since the bootstrap hack doesn't need this to be true */
 	/*
@@ -805,12 +805,12 @@ void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
 					break;
 				}
 			}
-			DSP56K::ICR_set(cpustate, data);
+			DSP_56156::ICR_set(cpustate, data);
 			break;
 
 		// Command Vector Register (CVR)
 		case 0x01:
-			DSP56K::CVR_set(cpustate, data);
+			DSP_56156::CVR_set(cpustate, data);
 			break;
 
 		// Interrupt status register (ISR) - Read only!
@@ -841,7 +841,7 @@ void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
 				break;  /* Probably the right thing to do, given this is a hack */
 			}
 
-			if (DSP56K::TXDE_bit(cpustate)) // 5-5
+			if (DSP_56156::TXDE_bit(cpustate)) // 5-5
 			{
 				TXH = data;
 			}
@@ -863,20 +863,20 @@ void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
 				break;  /* Probably the right thing to do, given this is a hack */
 			}
 
-			if (DSP56K::TXDE_bit(cpustate)) // 5-5
+			if (DSP_56156::TXDE_bit(cpustate)) // 5-5
 			{
 				TXL = data;
-				DSP56K::TXDE_bit_set(cpustate, 0);
+				DSP_56156::TXDE_bit_set(cpustate, 0);
 			}
 			break;
 
-		default: cpustate->device->logerror("DSP56k : dsp56k_host_interface_write called with invalid address 0x%02x.\n", offset);
+		default: cpustate->device->logerror("DSP56k : dsp56156_host_interface_write called with invalid address 0x%02x.\n", offset);
 	}
 }
 
-uint8_t dsp56k_device::host_interface_read(uint8_t offset)
+uint8_t dsp56156_device::host_interface_read(uint8_t offset)
 {
-	dsp56k_core* cpustate = &m_dsp56k_core;
+	dsp56156_core* cpustate = &m_core;
 
 	/* Not exactly correct since the bootstrap hack doesn't need this to be true */
 	/*
@@ -914,7 +914,7 @@ uint8_t dsp56k_device::host_interface_read(uint8_t offset)
 		// Receive byte register - high byte (RXH)
 		case 0x06:
 			// 5-5
-			if (!DSP56K::RXDF_bit(cpustate))
+			if (!DSP_56156::RXDF_bit(cpustate))
 				return 0xbf;
 			else
 				return RXH;
@@ -922,16 +922,16 @@ uint8_t dsp56k_device::host_interface_read(uint8_t offset)
 		// Receive byte register - low byte (RXL)
 		case 0x07:
 			// 5-5
-			if (!DSP56K::RXDF_bit(cpustate))
+			if (!DSP_56156::RXDF_bit(cpustate))
 				return 0xbf;
 			else
 			{
 				uint8_t value = RXL;  // TODO: Maybe not exactly right?  I'm just being safe.
-				DSP56K::RXDF_bit_set(cpustate, 0);
+				DSP_56156::RXDF_bit_set(cpustate, 0);
 				return value;
 			}
 
-		default: cpustate->device->logerror("DSP56k : dsp56k_host_interface_read called with invalid address 0x%02x.\n", offset);
+		default: cpustate->device->logerror("DSP56k : dsp56156_host_interface_read called with invalid address 0x%02x.\n", offset);
 	}
 
 	/* Shouldn't get here */
@@ -939,11 +939,11 @@ uint8_t dsp56k_device::host_interface_read(uint8_t offset)
 }
 
 /* MISC*/
-uint16_t dsp56k_device::get_peripheral_memory(uint16_t addr)
+uint16_t dsp56156_device::get_peripheral_memory(uint16_t addr)
 {
-	dsp56k_core* cpustate = &m_dsp56k_core;
+	dsp56156_core* cpustate = &m_core;
 	return cpustate->peripheral_ram[A2O(addr)];
 }
 
 
-} // namespace DSP56K
+} // namespace DSP_56156
diff --git a/src/devices/cpu/dsp56156/dsp56mem.h b/src/devices/cpu/dsp56156/dsp56mem.h
new file mode 100644
index 00000000000..fb5ac5f4334
--- /dev/null
+++ b/src/devices/cpu/dsp56156/dsp56mem.h
@@ -0,0 +1,241 @@
+// license:BSD-3-Clause
+// copyright-holders:Andrew Gardner
+#ifndef MAME_CPU_DSP56156_DSP56MEM_H
+#define MAME_CPU_DSP56156_DSP56MEM_H
+
+#include "dsp56156.h"
+
+namespace DSP_56156 {
+
+/***************************************************************************
+    MEMORY
+***************************************************************************/
+void mem_reset(dsp56156_core* cpustate);
+
+// Adjusts the documented address to match the offset in peripheral RAM
+#define A2O(a) (a - 0xffc0)
+
+// Adjusts the offset in peripheral RAM to match the documented address
+#define O2A(a) (a + 0xffc0)
+
+// The memory 'registers'
+#define PBC      (cpustate->peripheral_ram[A2O(0xffc0)])
+#define PCC      (cpustate->peripheral_ram[A2O(0xffc1)])
+#define PBDDR    (cpustate->peripheral_ram[A2O(0xffc2)])
+#define PCDDR    (cpustate->peripheral_ram[A2O(0xffc3)])
+#define HCR      (cpustate->peripheral_ram[A2O(0xffc4)])
+#define COCR     (cpustate->peripheral_ram[A2O(0xffc8)])
+#define CRASSI0  (cpustate->peripheral_ram[A2O(0xffd0)])
+#define CRBSSI0  (cpustate->peripheral_ram[A2O(0xffd1)])
+#define CRASSI1  (cpustate->peripheral_ram[A2O(0xffd8)])
+#define CRBSSI1  (cpustate->peripheral_ram[A2O(0xffd9)])
+#define PLCR     (cpustate->peripheral_ram[A2O(0xffdc)])
+#define BCR      (cpustate->peripheral_ram[A2O(0xffde)])
+#define IPR      (cpustate->peripheral_ram[A2O(0xffdf)])
+#define PBD      (cpustate->peripheral_ram[A2O(0xffe2)])
+#define PCD      (cpustate->peripheral_ram[A2O(0xffe3)])
+#define HSR      (cpustate->peripheral_ram[A2O(0xffe4)])
+#define HTXHRX   (cpustate->peripheral_ram[A2O(0xffe5)])
+#define COSR     (cpustate->peripheral_ram[A2O(0xffe8)])
+#define CRXCTX   (cpustate->peripheral_ram[A2O(0xffe9)])
+#define TCR      (cpustate->peripheral_ram[A2O(0xffec)])
+#define TCTR     (cpustate->peripheral_ram[A2O(0xffed)])
+#define TCPR     (cpustate->peripheral_ram[A2O(0xffee)])
+#define TPR      (cpustate->peripheral_ram[A2O(0xffef)])
+#define TSRSSI0  (cpustate->peripheral_ram[A2O(0xfff0)])
+#define TRXSSI0  (cpustate->peripheral_ram[A2O(0xfff1)])
+#define RSMA0    (cpustate->peripheral_ram[A2O(0xfff2)])
+#define RSMB0    (cpustate->peripheral_ram[A2O(0xfff3)])
+#define TSMA0    (cpustate->peripheral_ram[A2O(0xfff4)])
+#define TSMB0    (cpustate->peripheral_ram[A2O(0xfff5)])
+#define TSRSSI1  (cpustate->peripheral_ram[A2O(0xfff8)])
+#define TRXSSI1  (cpustate->peripheral_ram[A2O(0xfff9)])
+#define RSMA1    (cpustate->peripheral_ram[A2O(0xfffa)])
+#define RSMB1    (cpustate->peripheral_ram[A2O(0xfffb)])
+#define TSMA1    (cpustate->peripheral_ram[A2O(0xfffc)])
+#define TSMB1    (cpustate->peripheral_ram[A2O(0xfffd)])
+
+/* Interrupt priority register (IPR) bits */
+void IPR_set(dsp56156_core* cpustate, uint16_t value);
+
+/* A return value of -1 means disabled */
+int8_t irqa_ipl(dsp56156_core* cpustate);
+int8_t irqb_ipl(dsp56156_core* cpustate);
+uint8_t irqa_trigger(dsp56156_core* cpustate);
+uint8_t irqb_trigger(dsp56156_core* cpustate);
+
+int8_t codec_ipl(dsp56156_core* cpustate);
+int8_t host_ipl(dsp56156_core* cpustate);
+int8_t ssi0_ipl(dsp56156_core* cpustate);
+int8_t ssi1_ipl(dsp56156_core* cpustate);
+int8_t tm_ipl(dsp56156_core* cpustate);
+
+
+/***************************************************************************
+    HOST INTERFACE
+***************************************************************************/
+void dsp56156_host_interface_reset(dsp56156_core* cpustate);
+#define HTX (HTXHRX)
+#define HRX (HTXHRX)
+
+#define ICR (cpustate->HI.icr)
+#define CVR (cpustate->HI.cvr)
+#define ISR (cpustate->HI.isr)
+#define IVR (cpustate->HI.ivr)
+#define TXH (cpustate->HI.trxh)
+#define TXL (cpustate->HI.trxl)
+#define RXH (cpustate->HI.trxh)
+#define RXL (cpustate->HI.trxl)
+
+/*****************/
+/* DSP56156 SIDE */
+/*****************/
+/* Host Control Register (HCR) Bits */
+void HCR_set(dsp56156_core* cpustate, uint16_t value);
+
+//uint16_t HF3_bit(dsp56156_core* cpustate);  #define hf3BIT  ((HCR & 0x0010) != 0)
+//uint16_t HF2_bit(dsp56156_core* cpustate);  #define hf2BIT  ((HCR & 0x0008) != 0)
+uint16_t HCIE_bit(dsp56156_core* cpustate);
+uint16_t HTIE_bit(dsp56156_core* cpustate);
+uint16_t HRIE_bit(dsp56156_core* cpustate);
+
+void HF3_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HF2_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HCIE_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HTIE_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HRIE_bit_set(dsp56156_core* cpustate, uint16_t value);
+
+/* Host Status Register (HSR) Bits */
+//void HSR_set(dsp56156_core* cpustate, uint16_t value);
+
+//uint16_t DMA_bit(dsp56156_core* cpustate);  #define dmaBIT  ((HSR & 0x0080) != 0)
+//uint16_t HF1_bit(dsp56156_core* cpustate);  #define hf1BIT  ((HSR & 0x0010) != 0)
+//uint16_t HF0_bit(dsp56156_core* cpustate);  #define hf0BIT  ((HSR & 0x0008) != 0)
+//uint16_t HCP_bit(dsp56156_core* cpustate);  #define hcpBIT  ((HSR & 0x0004) != 0)
+uint16_t HTDE_bit(dsp56156_core* cpustate);
+uint16_t HRDF_bit(dsp56156_core* cpustate);
+
+void DMA_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HF1_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HF0_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HCP_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HTDE_bit_set(dsp56156_core* cpustate, uint16_t value);
+void HRDF_bit_set(dsp56156_core* cpustate, uint16_t value);
+
+/*************/
+/* HOST SIDE */
+/*************/
+/* Interrupt Control Register (ICR) Bits */
+void ICR_set(dsp56156_core* cpustate, uint8_t value);
+
+//uint8_t INIT_bit(dsp56156_core* cpustate); #define x_initBIT ((dsp56156.HI.ICR & 0x0080) != 0)
+//uint8_t HM1_bit(dsp56156_core* cpustate);  #define x_hm1BIT  ((dsp56156.HI.ICR & 0x0040) != 0)
+//uint8_t HM0_bit(dsp56156_core* cpustate);  #define x_hm0BIT  ((dsp56156.HI.ICR & 0x0020) != 0)
+//uint8_t HF1_bit_host(dsp56156_core* cpustate);  #define x_hf1BIT  ((dsp56156.HI.ICR & 0x0010) != 0)
+//uint8_t HF0_bit_host(dsp56156_core* cpustate);  #define x_hf0BIT  ((dsp56156.HI.ICR & 0x0008) != 0)
+//uint8_t TREQ_bit(dsp56156_core* cpustate); #define x_treqBIT ((dsp56156.HI.ICR & 0x0002) != 0)
+//uint8_t RREQ_bit(dsp56156_core* cpustate); #define x_rreqBIT ((dsp56156.HI.ICR & 0x0001) != 0)
+
+//void INIT_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56156.HI.ICR &= (~0x0080))
+//void HM1_bit_set(dsp56156_core* cpustate, uint8_t value);  #define CLEAR_x_hm1BIT()  (dsp56156.HI.ICR &= (~0x0040))
+//void HM0_bit_set(dsp56156_core* cpustate, uint8_t value);  #define CLEAR_x_hm0BIT()  (dsp56156.HI.ICR &= (~0x0020))
+void HF1_bit_host_set(dsp56156_core* cpustate, uint8_t value);
+void HF0_bit_host_set(dsp56156_core* cpustate, uint8_t value);
+void TREQ_bit_set(dsp56156_core* cpustate, uint8_t value);
+void RREQ_bit_set(dsp56156_core* cpustate, uint8_t value);
+
+/* Command Vector Register (CVR) Bits */
+void CVR_set(dsp56156_core* cpustate, uint8_t value);
+
+//uint8_t HC_bit();
+uint8_t HV_bits(dsp56156_core* cpustate);
+
+void HC_bit_set(dsp56156_core* cpustate, uint8_t value);
+void HV_bits_set(dsp56156_core* cpustate, uint8_t value);
+
+/* Interrupt Status Register (ISR) Bits */
+// void ISR_set(dsp56156_core* cpustate, uint8_t value);
+
+//uint8_t HREQ_bit(dsp56156_core* cpustate); #define x_hreqBIT ((dsp56156.HI.ISR & 0x0080) != 0)
+//uint8_t DMA_bit(dsp56156_core* cpustate);  #define x_dmaBIT  ((dsp56156.HI.ISR & 0x0040) != 0)
+//uint8_t HF3_bit_host(dsp56156_core* cpustate);  #define x_hf3BIT  ((dsp56156.HI.ISR & 0x0010) != 0)
+//uint8_t HF2_bit_host(dsp56156_core* cpustate);  #define x_hf2BIT  ((dsp56156.HI.ISR & 0x0008) != 0)
+//uint8_t TRDY_bit(dsp56156_core* cpustate); #define x_trdyBIT ((dsp56156.HI.ISR & 0x0004) != 0)
+uint8_t TXDE_bit(dsp56156_core* cpustate);
+uint8_t RXDF_bit(dsp56156_core* cpustate);
+
+//void HREQ_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_hreqBIT() (dsp56156.HI.ISR &= (~0x0080))
+//void DMA_bit_set(dsp56156_core* cpustate, uint8_t value);  #define CLEAR_x_dmaBIT()  (dsp56156.HI.ISR &= (~0x0040))
+void HF3_bit_host_set(dsp56156_core* cpustate, uint8_t value);
+void HF2_bit_host_set(dsp56156_core* cpustate, uint8_t value);
+//void TRDY_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_trdyBIT() (dsp56156.HI.ISR &= (~0x0004))
+void TXDE_bit_set(dsp56156_core* cpustate, uint8_t value);
+void RXDF_bit_set(dsp56156_core* cpustate, uint8_t value);
+
+/* Interrupt Vector Register (IVR) Bits */
+//void IVR_set(dsp56156_core* cpustate, uint8_t value);
+
+//uint8_t IV7_bit(dsp56156_core* cpustate);
+//uint8_t IV6_bit(dsp56156_core* cpustate);
+//uint8_t IV5_bit(dsp56156_core* cpustate);
+//uint8_t IV4_bit(dsp56156_core* cpustate);
+//uint8_t IV3_bit(dsp56156_core* cpustate);
+//uint8_t IV2_bit(dsp56156_core* cpustate);
+//uint8_t IV1_bit(dsp56156_core* cpustate);
+//uint8_t IV0_bit(dsp56156_core* cpustate);
+
+//void IV7_bit_set(dsp56156_core* cpustate, uint8_t value);
+//void IV6_bit_set(dsp56156_core* cpustate, uint8_t value);
+//void IV5_bit_set(dsp56156_core* cpustate, uint8_t value);
+//void IV4_bit_set(dsp56156_core* cpustate, uint8_t value);
+//void IV3_bit_set(dsp56156_core* cpustate, uint8_t value);
+//void IV2_bit_set(dsp56156_core* cpustate, uint8_t value);
+//void IV1_bit_set(dsp56156_core* cpustate, uint8_t value);
+//void IV0_bit_set(dsp56156_core* cpustate, uint8_t value);
+
+
+/* PROTOTYPES */
+void dsp56156_host_interface_HTX_to_host(dsp56156_core* cpustate);
+void dsp56156_host_interface_host_to_HTX(dsp56156_core* cpustate);
+
+
+/***************************************************************************
+    I/O INTERFACE
+***************************************************************************/
+void dsp56156_io_reset(dsp56156_core* cpustate);
+
+/* Port A Bus Control Register (BCR) */
+void BCR_set(dsp56156_core* cpustate, uint16_t value);
+
+//uint16_t RH_bit(dsp56156_core* cpustate);
+//uint16_t BS_bit(dsp56156_core* cpustate);
+//uint16_t external_x_wait_states(dsp56156_core* cpustate);
+//uint16_t external_p_wait_states(dsp56156_core* cpustate);
+
+void RH_bit_set(dsp56156_core* cpustate, uint16_t value);
+void BS_bit_set(dsp56156_core* cpustate, uint16_t value);
+void external_x_wait_states_set(dsp56156_core* cpustate, uint16_t value);
+void external_p_wait_states_set(dsp56156_core* cpustate, uint16_t value);
+
+/* Port B Control Register (PBC) */
+void PBC_set(dsp56156_core* cpustate, uint16_t value);
+//int host_interface_active(dsp56156_core* cpustate);
+
+/* Port B Data Direction Register (PBDDR) */
+void PBDDR_set(dsp56156_core* cpustate, uint16_t value);
+
+/* Port B Data Register (PBD) */
+void PBD_set(dsp56156_core* cpustate, uint16_t value);
+
+/* Port C Control Register (PCC) */
+void PCC_set(dsp56156_core* cpustate, uint16_t value);
+
+/* Port C Data Direction Register (PCDDR) */
+void PCDDR_set(dsp56156_core* cpustate, uint16_t value);
+
+/* Port C Dtaa Register (PCD) */
+void PCD_set(dsp56156_core* cpustate, uint16_t value);
+
+} // namespace DSP_56156
+
+#endif // MAME_CPU_DSP56156_DSP56MEM_H
diff --git a/src/devices/cpu/dsp56k/dsp56ops.hxx b/src/devices/cpu/dsp56156/dsp56ops.hxx
similarity index 67%
rename from src/devices/cpu/dsp56k/dsp56ops.hxx
rename to src/devices/cpu/dsp56156/dsp56ops.hxx
index 7e52d1b2cd0..52ff4f5560c 100644
--- a/src/devices/cpu/dsp56k/dsp56ops.hxx
+++ b/src/devices/cpu/dsp56156/dsp56ops.hxx
@@ -2,8 +2,8 @@
 // copyright-holders:Andrew Gardner
 /***************************************************************************
 
-    dsp56ops.inc
-    Core implementation for the portable Motorola/Freescale DSP56k emulator.
+    dsp56ops.hxx
+    Core implementation for the portable Motorola/Freescale DSP56156 emulator.
     Written by Andrew Gardner
 
 ***************************************************************************/
@@ -42,188 +42,188 @@ struct typed_pointer
 	char  data_type;
 };
 
-#define BITS(CUR,MASK) (Dsp56kOpMask(CUR,MASK))
+#define BITS(CUR,MASK) (Dsp56156OpMask(CUR,MASK))
 
 /*********************/
 /* Opcode prototypes */
 /*********************/
-static size_t dsp56k_op_addsub_2 (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
-static size_t dsp56k_op_mac_1    (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
-static size_t dsp56k_op_macr_1   (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
-static size_t dsp56k_op_move_1   (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
-static size_t dsp56k_op_mpy_1    (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
-static size_t dsp56k_op_mpyr_1   (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
-static size_t dsp56k_op_tfr_2    (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
-static size_t dsp56k_op_mpy_2    (dsp56k_core* cpustate, const uint16_t op_byte, uint8_t* cycles);
-static size_t dsp56k_op_mac_2    (dsp56k_core* cpustate, const uint16_t op_byte, uint8_t* cycles);
-static size_t dsp56k_op_clr      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_add      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_move     (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_tfr      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_rnd      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_tst      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_inc      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_inc24    (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_or       (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_asr      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_asl      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_lsr      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_lsl      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_eor      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_subl     (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_sub      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_clr24    (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_sbc      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_cmp      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_neg      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_not      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_dec      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_dec24    (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_and      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_abs      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_ror      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_rol      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_cmpm     (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_mpy      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_mpyr     (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_mac      (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_macr     (dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
-static size_t dsp56k_op_adc      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_andi     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_asl4     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_asr4     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_asr16    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_bfop     (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_bfop_1   (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_bfop_2   (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_bcc      (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_bcc_1    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_bcc_2    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_bra      (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_bra_1    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_bra_2    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_brkcc    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_bscc     (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_bscc_1   (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_bsr      (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_bsr_1    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_chkaau   (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_debug    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_debugcc  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_div      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_dmac     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_do       (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_do_1     (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_do_2     (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_doforever(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_enddo    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_ext      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_illegal  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_imac     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_impy     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_jcc      (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_jcc_1    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_jmp      (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_jmp_1    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_jscc     (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_jscc_1   (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_jsr      (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_jsr_1    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_jsr_2    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_lea      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_lea_1    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_macsuuu  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_move_2   (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_movec    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_movec_1  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_movec_2  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_movec_3  (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_movec_4  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_movec_5  (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_movei    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_movem    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_movem_1  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_movem_2  (dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
-static size_t dsp56k_op_movep    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_movep_1  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_moves    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_mpysuuu  (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_negc     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_nop      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_norm     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_ori      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_rep      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_rep_1    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_rep_2    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_repcc    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_reset    (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_rti      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_rts      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_stop     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_swap     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_swi      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_tcc      (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_tfr2     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_tfr3     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_tst2     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_wait     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
-static size_t dsp56k_op_zero     (dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_addsub_2 (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
+static size_t dsp56156_op_mac_1    (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
+static size_t dsp56156_op_macr_1   (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
+static size_t dsp56156_op_move_1   (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
+static size_t dsp56156_op_mpy_1    (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
+static size_t dsp56156_op_mpyr_1   (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
+static size_t dsp56156_op_tfr_2    (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles);
+static size_t dsp56156_op_mpy_2    (dsp56156_core* cpustate, const uint16_t op_byte, uint8_t* cycles);
+static size_t dsp56156_op_mac_2    (dsp56156_core* cpustate, const uint16_t op_byte, uint8_t* cycles);
+static size_t dsp56156_op_clr      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_add      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_move     (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_tfr      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_rnd      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_tst      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_inc      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_inc24    (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_or       (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_asr      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_asl      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_lsr      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_lsl      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_eor      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_subl     (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_sub      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_clr24    (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_sbc      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_cmp      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_neg      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_not      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_dec      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_dec24    (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_and      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_abs      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_ror      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_rol      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_cmpm     (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_mpy      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_mpyr     (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_mac      (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_macr     (dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles);
+static size_t dsp56156_op_adc      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_andi     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_asl4     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_asr4     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_asr16    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_bfop     (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_bfop_1   (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_bfop_2   (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_bcc      (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_bcc_1    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_bcc_2    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_bra      (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_bra_1    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_bra_2    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_brkcc    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_bscc     (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_bscc_1   (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_bsr      (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_bsr_1    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_chkaau   (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_debug    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_debugcc  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_div      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_dmac     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_do       (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_do_1     (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_do_2     (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_doforever(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_enddo    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_ext      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_illegal  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_imac     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_impy     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_jcc      (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_jcc_1    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_jmp      (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_jmp_1    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_jscc     (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_jscc_1   (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_jsr      (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_jsr_1    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_jsr_2    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_lea      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_lea_1    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_macsuuu  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_move_2   (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_movec    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_movec_1  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_movec_2  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_movec_3  (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_movec_4  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_movec_5  (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_movei    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_movem    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_movem_1  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_movem_2  (dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles);
+static size_t dsp56156_op_movep    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_movep_1  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_moves    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_mpysuuu  (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_negc     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_nop      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_norm     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_ori      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_rep      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_rep_1    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_rep_2    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_repcc    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_reset    (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_rti      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_rts      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_stop     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_swap     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_swi      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_tcc      (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_tfr2     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_tfr3     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_tst2     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_wait     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
+static size_t dsp56156_op_zero     (dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles);
 
 
-static void execute_register_to_register_data_move(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value);
-static void execute_address_register_update(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value);
-static void execute_x_memory_data_move (dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value);
-static void execute_x_memory_data_move2(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register);
-static void execute_dual_x_memory_data_read(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register);
-static void execute_x_memory_data_move_with_short_displacement(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2);
+static void execute_register_to_register_data_move(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value);
+static void execute_address_register_update(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value);
+static void execute_x_memory_data_move (dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value);
+static void execute_x_memory_data_move2(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register);
+static void execute_dual_x_memory_data_read(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register);
+static void execute_x_memory_data_move_with_short_displacement(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2);
 
-static uint16_t   decode_BBB_bitmask(dsp56k_core* cpustate, uint16_t BBB, uint16_t *iVal);
-static int      decode_cccc_table(dsp56k_core* cpustate, uint16_t cccc);
-static void     decode_DDDDD_table(dsp56k_core* cpustate, uint16_t DDDDD, typed_pointer* ret);
-static void     decode_DD_table(dsp56k_core* cpustate, uint16_t DD, typed_pointer* ret);
-static void     decode_DDF_table(dsp56k_core* cpustate, uint16_t DD, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
-static void     decode_F_table(dsp56k_core* cpustate, uint16_t F, typed_pointer* ret);
-static void     decode_h0hF_table(dsp56k_core* cpustate, uint16_t h0h, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
-static void     decode_HH_table(dsp56k_core* cpustate, uint16_t HH, typed_pointer* ret);
-static void     decode_HHH_table(dsp56k_core* cpustate, uint16_t HHH, typed_pointer* ret);
-static void     decode_IIII_table(dsp56k_core* cpustate, uint16_t IIII, typed_pointer* src_ret, typed_pointer* dst_ret, void* working);
-static void     decode_JJJF_table(dsp56k_core* cpustate, uint16_t JJJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
-static void     decode_JJF_table(dsp56k_core* cpustate, uint16_t JJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
-static void     decode_JF_table(dsp56k_core* cpustate, uint16_t JJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
-static void     decode_KKK_table(dsp56k_core* cpustate, uint16_t KKK, typed_pointer* dst_ret1, typed_pointer* dst_ret2, void* working);
-static void     decode_QQF_table(dsp56k_core* cpustate, uint16_t QQ, uint16_t F, void **S1, void **S2, void **D);
-static void     decode_QQF_special_table(dsp56k_core* cpustate, uint16_t QQ, uint16_t F, void **S1, void **S2, void **D);
-static void     decode_QQQF_table(dsp56k_core* cpustate, uint16_t QQQ, uint16_t F, void **S1, void **S2, void **D);
-static void     decode_RR_table(dsp56k_core* cpustate, uint16_t RR, typed_pointer* ret);
-static void     decode_TT_table(dsp56k_core* cpustate, uint16_t TT, typed_pointer* ret);
-static void     decode_uuuuF_table(dsp56k_core* cpustate, uint16_t uuuu, uint16_t F, uint8_t add_sub_other, typed_pointer* src_ret, typed_pointer* dst_ret);
-static void     decode_Z_table(dsp56k_core* cpustate, uint16_t Z, typed_pointer* ret);
+static uint16_t   decode_BBB_bitmask(dsp56156_core* cpustate, uint16_t BBB, uint16_t *iVal);
+static int      decode_cccc_table(dsp56156_core* cpustate, uint16_t cccc);
+static void     decode_DDDDD_table(dsp56156_core* cpustate, uint16_t DDDDD, typed_pointer* ret);
+static void     decode_DD_table(dsp56156_core* cpustate, uint16_t DD, typed_pointer* ret);
+static void     decode_DDF_table(dsp56156_core* cpustate, uint16_t DD, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
+static void     decode_F_table(dsp56156_core* cpustate, uint16_t F, typed_pointer* ret);
+static void     decode_h0hF_table(dsp56156_core* cpustate, uint16_t h0h, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
+static void     decode_HH_table(dsp56156_core* cpustate, uint16_t HH, typed_pointer* ret);
+static void     decode_HHH_table(dsp56156_core* cpustate, uint16_t HHH, typed_pointer* ret);
+static void     decode_IIII_table(dsp56156_core* cpustate, uint16_t IIII, typed_pointer* src_ret, typed_pointer* dst_ret, void* working);
+static void     decode_JJJF_table(dsp56156_core* cpustate, uint16_t JJJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
+static void     decode_JJF_table(dsp56156_core* cpustate, uint16_t JJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
+static void     decode_JF_table(dsp56156_core* cpustate, uint16_t JJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret);
+static void     decode_KKK_table(dsp56156_core* cpustate, uint16_t KKK, typed_pointer* dst_ret1, typed_pointer* dst_ret2, void* working);
+static void     decode_QQF_table(dsp56156_core* cpustate, uint16_t QQ, uint16_t F, void **S1, void **S2, void **D);
+static void     decode_QQF_special_table(dsp56156_core* cpustate, uint16_t QQ, uint16_t F, void **S1, void **S2, void **D);
+static void     decode_QQQF_table(dsp56156_core* cpustate, uint16_t QQQ, uint16_t F, void **S1, void **S2, void **D);
+static void     decode_RR_table(dsp56156_core* cpustate, uint16_t RR, typed_pointer* ret);
+static void     decode_TT_table(dsp56156_core* cpustate, uint16_t TT, typed_pointer* ret);
+static void     decode_uuuuF_table(dsp56156_core* cpustate, uint16_t uuuu, uint16_t F, uint8_t add_sub_other, typed_pointer* src_ret, typed_pointer* dst_ret);
+static void     decode_Z_table(dsp56156_core* cpustate, uint16_t Z, typed_pointer* ret);
 
-static void     execute_m_table(dsp56k_core* cpustate, int x, uint16_t m);
-static void     execute_mm_table(dsp56k_core* cpustate, uint16_t rnum, uint16_t mm);
-static void     execute_MM_table(dsp56k_core* cpustate, uint16_t rnum, uint16_t MM);
-static uint16_t   execute_q_table(dsp56k_core* cpustate, int RR, uint16_t q);
-static void     execute_z_table(dsp56k_core* cpustate, int RR, uint16_t z);
+static void     execute_m_table(dsp56156_core* cpustate, int x, uint16_t m);
+static void     execute_mm_table(dsp56156_core* cpustate, uint16_t rnum, uint16_t mm);
+static void     execute_MM_table(dsp56156_core* cpustate, uint16_t rnum, uint16_t MM);
+static uint16_t   execute_q_table(dsp56156_core* cpustate, int RR, uint16_t q);
+static void     execute_z_table(dsp56156_core* cpustate, int RR, uint16_t z);
 
-static uint16_t   assemble_address_from_Pppppp_table(dsp56k_core* cpustate, uint16_t P, uint16_t ppppp);
-static uint16_t   assemble_address_from_IO_short_address(dsp56k_core* cpustate, uint16_t pp);
-static uint16_t   assemble_address_from_6bit_signed_relative_short_address(dsp56k_core* cpustate, uint16_t srs);
+static uint16_t   assemble_address_from_Pppppp_table(dsp56156_core* cpustate, uint16_t P, uint16_t ppppp);
+static uint16_t   assemble_address_from_IO_short_address(dsp56156_core* cpustate, uint16_t pp);
+static uint16_t   assemble_address_from_6bit_signed_relative_short_address(dsp56156_core* cpustate, uint16_t srs);
 
-static void dsp56k_process_loop(dsp56k_core* cpustate);
-static void dsp56k_process_rep(dsp56k_core* cpustate, size_t repSize);
+static void dsp56156_process_loop(dsp56156_core* cpustate);
+static void dsp56156_process_rep(dsp56156_core* cpustate, size_t repSize);
 
 
 
 /********************/
 /* Helper Functions */
 /********************/
-static uint16_t Dsp56kOpMask(uint16_t op, uint16_t mask);
+static uint16_t Dsp56156OpMask(uint16_t op, uint16_t mask);
 
 /* These arguments are written source->destination to fall in line with the processor's paradigm. */
 static void SetDestinationValue(typed_pointer source, typed_pointer dest);
 
-static void SetDataMemoryValue(dsp56k_core* cpustate, typed_pointer source, uint32_t destinationAddr);
-static void SetProgramMemoryValue(dsp56k_core* cpustate, typed_pointer source, uint32_t destinationAddr);
+static void SetDataMemoryValue(dsp56156_core* cpustate, typed_pointer source, uint32_t destinationAddr);
+static void SetProgramMemoryValue(dsp56156_core* cpustate, typed_pointer source, uint32_t destinationAddr);
 
 
 
@@ -231,7 +231,7 @@ static void SetProgramMemoryValue(dsp56k_core* cpustate, typed_pointer source, u
     IMPLEMENTATION
 ***************************************************************************/
 
-static void execute_one(dsp56k_core* cpustate)
+static void execute_one(dsp56156_core* cpustate)
 {
 	uint16_t op;
 	uint16_t op2;
@@ -263,22 +263,22 @@ static void execute_one(dsp56k_core* cpustate)
 		/* Note: 0x0094 check allows command to drop through to MOVE and TFR */
 		if (((op & 0xe080) == 0x6000) && ((op & 0x0094) != 0x0010))
 		{
-			size = dsp56k_op_addsub_2(cpustate, op_byte, &d_register, &cycle_count);
+			size = dsp56156_op_addsub_2(cpustate, op_byte, &d_register, &cycle_count);
 		}
 		/* MAC : 011m mKKK 1xx0 F1QQ : A-122 */
 		else if ((op & 0xe094) == 0x6084)
 		{
-			size = dsp56k_op_mac_1(cpustate, op_byte, &d_register, &cycle_count);
+			size = dsp56156_op_mac_1(cpustate, op_byte, &d_register, &cycle_count);
 		}
 		/* MACR: 011m mKKK 1--1 F1QQ : A-124 */
 		else if ((op & 0xe094) == 0x6094)
 		{
-			size = dsp56k_op_macr_1(cpustate, op_byte, &d_register, &cycle_count);
+			size = dsp56156_op_macr_1(cpustate, op_byte, &d_register, &cycle_count);
 		}
 		/* TFR : 011m mKKK 0rr1 F0DD : A-212 */
 		else if ((op & 0xe094) == 0x6010)
 		{
-			size = dsp56k_op_tfr_2(cpustate, op_byte, &d_register, &cycle_count);
+			size = dsp56156_op_tfr_2(cpustate, op_byte, &d_register, &cycle_count);
 		}
 		/* MOVE : 011m mKKK 0rr1 0000 : A-128 */
 		else if ((op & 0xe09f) == 0x6010)
@@ -289,17 +289,17 @@ static void execute_one(dsp56k_core* cpustate)
 			         documentation.  Real-world examples would need to be examined to come
 			         to a satisfactory conclusion, but as it stands, tfr will override this
 			         move operation. */
-			size = dsp56k_op_move_1(cpustate, op_byte, &d_register, &cycle_count);
+			size = dsp56156_op_move_1(cpustate, op_byte, &d_register, &cycle_count);
 		}
 		/* MPY : 011m mKKK 1xx0 F0QQ : A-160 */
 		else if ((op & 0xe094) == 0x6080)
 		{
-			size = dsp56k_op_mpy_1(cpustate, op_byte, &d_register, &cycle_count);
+			size = dsp56156_op_mpy_1(cpustate, op_byte, &d_register, &cycle_count);
 		}
 		/* MPYR : 011m mKKK 1--1 F0QQ : A-162 */
 		else if ((op & 0xe094) == 0x6090)
 		{
-			size = dsp56k_op_mpyr_1(cpustate, op_byte, &d_register, &cycle_count);
+			size = dsp56156_op_mpyr_1(cpustate, op_byte, &d_register, &cycle_count);
 		}
 
 		/* Now evaluate the parallel data move */
@@ -314,17 +314,17 @@ static void execute_one(dsp56k_core* cpustate)
 		/* MPY : 0001 0110 RRDD FQQQ : A-160 */
 		if ((op & 0xff00) == 0x1600)
 		{
-			size = dsp56k_op_mpy_2(cpustate, op_byte, &cycle_count);
+			size = dsp56156_op_mpy_2(cpustate, op_byte, &cycle_count);
 		}
 		/* MAC : 0001 0111 RRDD FQQQ : A-122 */
 		else if ((op & 0xff00) == 0x1700)
 		{
-			size = dsp56k_op_mac_2(cpustate, op_byte, &cycle_count);
+			size = dsp56156_op_mac_2(cpustate, op_byte, &cycle_count);
 		}
 
 		/* Now evaluate the parallel data move */
 		/* TODO // decode_x_memory_data_write_and_register_data_move(op, parallel_move_str, parallel_move_str2); */
-		cpustate->device->logerror("DSP56k: Unemulated Dual X Memory Data And Register Data Move @ 0x%x\n", PC);
+		cpustate->device->logerror("DSP56156: Unemulated Dual X Memory Data And Register Data Move @ 0x%x\n", PC);
 	}
 
 	/* Handle Other parallel types */
@@ -405,178 +405,178 @@ static void execute_one(dsp56k_core* cpustate)
 			/* CLR : .... .... 0000 F001 : A-60 */
 			if ((op_byte & 0x00f7) == 0x0001)
 			{
-				size = dsp56k_op_clr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_clr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* ADD : .... .... 0000 FJJJ : A-22 */
 			else if ((op_byte & 0x00f0) == 0x0000)
 			{
-				size = dsp56k_op_add(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_add(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
 			/* MOVE : .... .... 0001 0001 : A-128 */
 			else if ((op_byte & 0x00ff) == 0x0011)
 			{
-				size = dsp56k_op_move(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_move(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* TFR : .... .... 0001 FJJJ : A-212 */
 			else if ((op_byte & 0x00f0) == 0x0010)
 			{
-				size = dsp56k_op_tfr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_tfr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
 			/* RND : .... .... 0010 F000 : A-188 */
 			else if ((op_byte & 0x00f7) == 0x0020)
 			{
-				size = dsp56k_op_rnd(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_rnd(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* TST : .... .... 0010 F001 : A-218 */
 			else if ((op_byte & 0x00f7) == 0x0021)
 			{
-				size = dsp56k_op_tst(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_tst(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* INC : .... .... 0010 F010 : A-104 */
 			else if ((op_byte & 0x00f7) == 0x0022)
 			{
-				size = dsp56k_op_inc(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_inc(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* INC24 : .... .... 0010 F011 : A-106 */
 			else if ((op_byte & 0x00f7) == 0x0023)
 			{
-				size = dsp56k_op_inc24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_inc24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* OR : .... .... 0010 F1JJ : A-176 */
 			else if ((op_byte & 0x00f4) == 0x0024)
 			{
-				size = dsp56k_op_or(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_or(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
 			/* ASR : .... .... 0011 F000 : A-32 */
 			else if ((op_byte & 0x00f7) == 0x0030)
 			{
-				size = dsp56k_op_asr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_asr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* ASL : .... .... 0011 F001 : A-28 */
 			else if ((op_byte & 0x00f7) == 0x0031)
 			{
-				size = dsp56k_op_asl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_asl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* LSR : .... .... 0011 F010 : A-120 */
 			else if ((op_byte & 0x00f7) == 0x0032)
 			{
-				size = dsp56k_op_lsr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_lsr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* LSL : .... .... 0011 F011 : A-118 */
 			else if ((op_byte & 0x00f7) == 0x0033)
 			{
-				size = dsp56k_op_lsl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_lsl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* EOR : .... .... 0011 F1JJ : A-94 */
 			else if ((op_byte & 0x00f4) == 0x0034)
 			{
-				size = dsp56k_op_eor(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_eor(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
 			/* SUBL : .... .... 0100 F001 : A-204 */
 			else if ((op_byte & 0x00f7) == 0x0041)
 			{
-				size = dsp56k_op_subl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_subl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* SUB : .... .... 0100 FJJJ : A-202 */
 			else if ((op_byte & 0x00f0) == 0x0040)
 			{
-				size = dsp56k_op_sub(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_sub(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
 			/* CLR24 : .... .... 0101 F001 : A-62 */
 			else if ((op_byte & 0x00f7) == 0x0051)
 			{
-				size = dsp56k_op_clr24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_clr24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* SBC : .... .... 0101 F01J : A-198 */
 			else if ((op_byte & 0x00f6) == 0x0052)
 			{
-				size = dsp56k_op_sbc(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_sbc(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* CMP : .... .... 0101 FJJJ : A-64 */
 			else if ((op_byte & 0x00f0) == 0x0050)
 			{
-				size = dsp56k_op_cmp(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_cmp(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
 			/* NEG : .... .... 0110 F000 : A-166 */
 			else if ((op_byte & 0x00f7) == 0x0060)
 			{
-				size = dsp56k_op_neg(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_neg(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* NOT : .... .... 0110 F001 : A-174 */
 			else if ((op_byte & 0x00f7) == 0x0061)
 			{
-				size = dsp56k_op_not(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_not(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* DEC : .... .... 0110 F010 : A-72 */
 			else if ((op_byte & 0x00f7) == 0x0062)
 			{
-				size = dsp56k_op_dec(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_dec(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* DEC24 : .... .... 0110 F011 : A-74 */
 			else if ((op_byte & 0x00f7) == 0x0063)
 			{
-				size = dsp56k_op_dec24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_dec24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* AND : .... .... 0110 F1JJ : A-24 */
 			else if ((op_byte & 0x00f4) == 0x0064)
 			{
-				size = dsp56k_op_and(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_and(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
 			/* ABS : .... .... 0111 F001 : A-18 */
 			if ((op_byte & 0x00f7) == 0x0071)
 			{
-				size = dsp56k_op_abs(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_abs(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* ROR : .... .... 0111 F010 : A-192 */
 			else if ((op_byte & 0x00f7) == 0x0072)
 			{
-				size = dsp56k_op_ror(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_ror(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* ROL : .... .... 0111 F011 : A-190 */
 			else if ((op_byte & 0x00f7) == 0x0073)
 			{
-				size = dsp56k_op_rol(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_rol(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* CMPM : .... .... 0111 FJJJ : A-66 */
 			else if ((op_byte & 0x00f0) == 0x0070)
 			{
-				size = dsp56k_op_cmpm(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_cmpm(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
 			/* MPY : .... .... 1k00 FQQQ : A-160    -- CONFIRMED TYPO IN DOCS (HHHH vs HHHW) */
 			else if ((op_byte & 0x00b0) == 0x0080)
 			{
-				size = dsp56k_op_mpy(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_mpy(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* MPYR : .... .... 1k01 FQQQ : A-162 */
 			else if ((op_byte & 0x00b0) == 0x0090)
 			{
-				size = dsp56k_op_mpyr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_mpyr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* MAC : .... .... 1k10 FQQQ : A-122 */
 			else if ((op_byte & 0x00b0) == 0x00a0)
 			{
-				size = dsp56k_op_mac(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_mac(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 			/* MACR : .... .... 1k11 FQQQ : A-124   -- DRAMA - rr vs xx (805) */
 			else if ((op_byte & 0x00b0) == 0x00b0)
 			{
-				size = dsp56k_op_macr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
+				size = dsp56156_op_macr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count);
 			}
 
 
@@ -611,8 +611,8 @@ static void execute_one(dsp56k_core* cpustate)
 	{
 		PC += (uint16_t)size;
 
-		dsp56k_process_loop(cpustate);
-		dsp56k_process_rep(cpustate, size);
+		dsp56156_process_loop(cpustate);
+		dsp56156_process_rep(cpustate, size);
 
 		cpustate->icount -= 4;  /* Temporarily hard-coded at 4 clocks per opcode */ /* cycle_count */
 		return;
@@ -626,478 +626,478 @@ static void execute_one(dsp56k_core* cpustate)
 	/* ADC : 0001 0101 0000 F01J : A-20 */
 	if ((op & 0xfff6) == 0x1502)
 	{
-		size = dsp56k_op_adc(cpustate, op, &cycle_count);
+		size = dsp56156_op_adc(cpustate, op, &cycle_count);
 	}
 	/* ANDI : 0001 1EE0 iiii iiii : A-26 */
 	/* (MoveP sneaks in here if you don't check 0x0600) */
 	else if (((op & 0xf900) == 0x1800) & ((op & 0x0600) != 0x0000))
 	{
-		size = dsp56k_op_andi(cpustate, op, &cycle_count);
+		size = dsp56156_op_andi(cpustate, op, &cycle_count);
 	}
 	/* ASL4 : 0001 0101 0011 F001 : A-30 */
 	else if ((op & 0xfff7) == 0x1531)
 	{
-		size = dsp56k_op_asl4(cpustate, op, &cycle_count);
+		size = dsp56156_op_asl4(cpustate, op, &cycle_count);
 	}
 	/* ASR4 : 0001 0101 0011 F000 : A-34 */
 	else if ((op & 0xfff7) == 0x1530)
 	{
-		size = dsp56k_op_asr4(cpustate, op, &cycle_count);
+		size = dsp56156_op_asr4(cpustate, op, &cycle_count);
 	}
 	/* ASR16 : 0001 0101 0111 F000 : A-36 */
 	else if ((op & 0xfff7) == 0x1570)
 	{
-		size = dsp56k_op_asr16(cpustate, op, &cycle_count);
+		size = dsp56156_op_asr16(cpustate, op, &cycle_count);
 	}
 	/* BFCHG : 0001 0100 11Pp pppp BBB1 0010 iiii iiii : A-38 */
 	else if (((op & 0xffc0) == 0x14c0) && ((op2 & 0x1f00) == 0x1200))
 	{
-		size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop(cpustate, op, op2, &cycle_count);
 	}
 	/* BFCHG : 0001 0100 101- --RR BBB1 0010 iiii iiii : A-38 */
 	else if (((op & 0xffe0) == 0x14a0) && ((op2 & 0x1f00) == 0x1200))
 	{
-		size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_1(cpustate, op, op2, &cycle_count);
 	}
 	/* BFCHG : 0001 0100 100D DDDD BBB1 0010 iiii iiii : A-38 */
 	else if (((op & 0xffe0) == 0x1480) && ((op2 & 0x1f00) == 0x1200))
 	{
-		size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_2(cpustate, op, op2, &cycle_count);
 	}
 	/* BFCLR : 0001 0100 11Pp pppp BBB0 0100 iiii iiii : A-40 */
 	else if (((op & 0xffc0) == 0x14c0) && ((op2 & 0x1f00) == 0x0400))
 	{
-		size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop(cpustate, op, op2, &cycle_count);
 	}
 	/* BFCLR : 0001 0100 101- --RR BBB0 0100 iiii iiii : A-40 */
 	else if (((op & 0xffe0) == 0x14a0) && ((op2 & 0x1f00) == 0x0400))
 	{
-		size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_1(cpustate, op, op2, &cycle_count);
 	}
 	/* BFCLR : 0001 0100 100D DDDD BBB0 0100 iiii iiii : A-40 */
 	else if (((op & 0xffe0) == 0x1480) && ((op2 & 0x1f00) == 0x0400))
 	{
-		size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_2(cpustate, op, op2, &cycle_count);
 	}
 	/* BFSET : 0001 0100 11Pp pppp BBB1 1000 iiii iiii : A-42 */
 	else if (((op & 0xffc0) == 0x14c0) && ((op2 & 0x1f00) == 0x1800))
 	{
-		size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop(cpustate, op, op2, &cycle_count);
 	}
 	/* BFSET : 0001 0100 101- --RR BBB1 1000 iiii iiii : A-42 */
 	else if (((op & 0xffe0) == 0x14a0) && ((op2 & 0x1f00) == 0x1800))
 	{
-		size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_1(cpustate, op, op2, &cycle_count);
 	}
 	/* BFSET : 0001 0100 100D DDDD BBB1 1000 iiii iiii : A-42 */
 	else if (((op & 0xffe0) == 0x1480) && ((op2 & 0x1f00) == 0x1800))
 	{
-		size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_2(cpustate, op, op2, &cycle_count);
 	}
 	/* BFTSTH : 0001 0100 01Pp pppp BBB1 0000 iiii iiii : A-44 */
 	else if (((op & 0xffc0) == 0x1440) && ((op2 & 0x1f00) == 0x1000))
 	{
-		size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop(cpustate, op, op2, &cycle_count);
 	}
 	/* BFTSTH : 0001 0100 001- --RR BBB1 0000 iiii iiii : A-44 */
 	else if (((op & 0xffe0) == 0x1420) && ((op2 & 0x1f00) == 0x1000))
 	{
-		size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_1(cpustate, op, op2, &cycle_count);
 	}
 	/* BFTSTH : 0001 0100 000D DDDD BBB1 0000 iiii iiii : A-44 */
 	else if (((op & 0xffe0) == 0x1400) && ((op2 & 0x1f00) == 0x1000))
 	{
-		size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_2(cpustate, op, op2, &cycle_count);
 	}
 	/* BFTSTL : 0001 0100 01Pp pppp BBB0 0000 iiii iiii : A-46 */
 	else if (((op & 0xffc0) == 0x1440) && ((op2 & 0x1f00) == 0x0000))
 	{
-		size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop(cpustate, op, op2, &cycle_count);
 	}
 	/* BFTSTL : 0001 0100 001- --RR BBB0 0000 iiii iiii : A-46 */
 	else if (((op & 0xffe0) == 0x1420) && ((op2 & 0x1f00) == 0x0000))
 	{
-		size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_1(cpustate, op, op2, &cycle_count);
 	}
 	/* BFTSTL : 0001 0100 000D DDDD BBB0 0000 iiii iiii : A-46 */
 	else if (((op & 0xffe0) == 0x1400) && ((op2 & 0x1f00) == 0x0000))
 	{
-		size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bfop_2(cpustate, op, op2, &cycle_count);
 	}
 	/* Bcc : 0000 0111 --11 cccc xxxx xxxx xxxx xxxx : A-48 */
 	else if (((op & 0xff30) == 0x0730) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_bcc(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bcc(cpustate, op, op2, &cycle_count);
 	}
 	/* Bcc : 0010 11cc ccee eeee : A-48 */
 	else if ((op & 0xfc00) == 0x2c00)
 	{
-		size = dsp56k_op_bcc_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_bcc_1(cpustate, op, &cycle_count);
 	}
 	/* Bcc : 0000 0111 RR10 cccc : A-48 */
 	else if ((op & 0xff30) == 0x0720)
 	{
-		size = dsp56k_op_bcc_2(cpustate, op, &cycle_count);
+		size = dsp56156_op_bcc_2(cpustate, op, &cycle_count);
 	}
 	/* BRA : 0000 0001 0011 11-- xxxx xxxx xxxx xxxx : A-50 */
 	else if (((op & 0xfffc) == 0x013c) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_bra(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bra(cpustate, op, op2, &cycle_count);
 	}
 	/* BRA : 0000 1011 aaaa aaaa : A-50 */
 	else if ((op & 0xff00) == 0x0b00)
 	{
-		size = dsp56k_op_bra_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_bra_1(cpustate, op, &cycle_count);
 	}
 	/* BRA : 0000 0001 0010 11RR : A-50 */
 	else if ((op & 0xfffc) == 0x012c)
 	{
-		size = dsp56k_op_bra_2(cpustate, op, &cycle_count);
+		size = dsp56156_op_bra_2(cpustate, op, &cycle_count);
 	}
 	/* BRKc : 0000 0001 0001 cccc : A-52 */
 	else if ((op & 0xfff0) == 0x0110)
 	{
-		size = dsp56k_op_brkcc(cpustate, op, &cycle_count);
+		size = dsp56156_op_brkcc(cpustate, op, &cycle_count);
 	}
 	/* BScc : 0000 0111 --01 cccc xxxx xxxx xxxx xxxx : A-54 */
 	else if (((op & 0xff30) == 0x0710) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_bscc(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bscc(cpustate, op, op2, &cycle_count);
 	}
 	/* BScc : 0000 0111 RR00 cccc : A-54 */
 	else if ((op & 0xff30) == 0x0700)
 	{
-		size = dsp56k_op_bscc_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_bscc_1(cpustate, op, &cycle_count);
 	}
 	/* BSR : 0000 0001 0011 10-- xxxx xxxx xxxx xxxx : A-56 */
 	else if (((op & 0xfffc) == 0x0138) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_bsr(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_bsr(cpustate, op, op2, &cycle_count);
 	}
 	/* BSR : 0000 0001 0010 10RR : A-56 */
 	else if ((op & 0xfffc) == 0x0128)
 	{
-		size = dsp56k_op_bsr_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_bsr_1(cpustate, op, &cycle_count);
 	}
 	/* CHKAAU : 0000 0000 0000 0100 : A-58 */
 	else if ((op & 0xffff) == 0x0004)
 	{
-		size = dsp56k_op_chkaau(cpustate, op, &cycle_count);
+		size = dsp56156_op_chkaau(cpustate, op, &cycle_count);
 	}
 	/* DEBUG : 0000 0000 0000 0001 : A-68 */
 	else if ((op & 0xffff) == 0x0001)
 	{
-		size = dsp56k_op_debug(cpustate, op, &cycle_count);
+		size = dsp56156_op_debug(cpustate, op, &cycle_count);
 	}
 	/* DEBUGcc : 0000 0000 0101 cccc : A-70 */
 	else if ((op & 0xfff0) == 0x0050)
 	{
-		size = dsp56k_op_debugcc(cpustate, op, &cycle_count);
+		size = dsp56156_op_debugcc(cpustate, op, &cycle_count);
 	}
 	/* DIV : 0001 0101 0--0 F1DD : A-76 */
 	else if ((op & 0xff94) == 0x1504)
 	{
-		size = dsp56k_op_div(cpustate, op, &cycle_count);
+		size = dsp56156_op_div(cpustate, op, &cycle_count);
 	}
 	/* DMAC : 0001 0101 10s1 FsQQ : A-80 */
 	else if ((op & 0xffd0) == 0x1590)
 	{
-		size = dsp56k_op_dmac(cpustate, op, &cycle_count);
+		size = dsp56156_op_dmac(cpustate, op, &cycle_count);
 	}
 	/* DO : 0000 0000 110- --RR xxxx xxxx xxxx xxxx : A-82 */
 	else if (((op & 0xffe0) == 0x00c0) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_do(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_do(cpustate, op, op2, &cycle_count);
 	}
 	/* DO : 0000 1110 iiii iiii xxxx xxxx xxxx xxxx : A-82 */
 	else if (((op & 0xff00) == 0x0e00) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_do_1(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_do_1(cpustate, op, op2, &cycle_count);
 	}
 	/* DO : 0000 0100 000D DDDD xxxx xxxx xxxx xxxx : A-82 */
 	else if (((op & 0xffe0) == 0x0400) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_do_2(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_do_2(cpustate, op, op2, &cycle_count);
 	}
 	/* DO FOREVER : 0000 0000 0000 0010 xxxx xxxx xxxx xxxx : A-88 */
 	else if (((op & 0xffff) == 0x0002) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_doforever(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_doforever(cpustate, op, op2, &cycle_count);
 	}
 	/* ENDDO : 0000 0000 0000 1001 : A-92 */
 	else if ((op & 0xffff) == 0x0009)
 	{
-		size = dsp56k_op_enddo(cpustate, op, &cycle_count);
+		size = dsp56156_op_enddo(cpustate, op, &cycle_count);
 	}
 	/* EXT : 0001 0101 0101 F010 : A-96 */
 	else if ((op & 0xfff7) == 0x1552)
 	{
-		size = dsp56k_op_ext(cpustate, op, &cycle_count);
+		size = dsp56156_op_ext(cpustate, op, &cycle_count);
 	}
 	/* ILLEGAL : 0000 0000 0000 1111 : A-98 */
 	else if ((op & 0xffff) == 0x000f)
 	{
-		size = dsp56k_op_illegal(cpustate, op, &cycle_count);
+		size = dsp56156_op_illegal(cpustate, op, &cycle_count);
 	}
 	/* IMAC : 0001 0101 1010 FQQQ : A-100 */
 	else if ((op & 0xfff0) == 0x15a0)
 	{
-		size = dsp56k_op_imac(cpustate, op, &cycle_count);
+		size = dsp56156_op_imac(cpustate, op, &cycle_count);
 	}
 	/* IMPY : 0001 0101 1000 FQQQ : A-102 */
 	else if ((op & 0xfff0) == 0x1580)
 	{
-		size = dsp56k_op_impy(cpustate, op, &cycle_count);
+		size = dsp56156_op_impy(cpustate, op, &cycle_count);
 	}
 	/* Jcc : 0000 0110 --11 cccc xxxx xxxx xxxx xxxx : A-108 */
 	else if (((op & 0xff30) == 0x0630) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_jcc(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_jcc(cpustate, op, op2, &cycle_count);
 	}
 	/* Jcc : 0000 0110 RR10 cccc : A-108 */
 	else if ((op & 0xff30) == 0x0620 )
 	{
-		size = dsp56k_op_jcc_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_jcc_1(cpustate, op, &cycle_count);
 	}
 	/* JMP : 0000 0001 0011 01-- xxxx xxxx xxxx xxxx : A-110 */
 	else if (((op & 0xfffc) == 0x0134) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_jmp(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_jmp(cpustate, op, op2, &cycle_count);
 	}
 	/* JMP : 0000 0001 0010 01RR : A-110 */
 	else if ((op & 0xfffc) == 0x0124)
 	{
-		size = dsp56k_op_jmp_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_jmp_1(cpustate, op, &cycle_count);
 	}
 	/* JScc : 0000 0110 --01 cccc xxxx xxxx xxxx xxxx : A-112 */
 	else if (((op & 0xff30) == 0x0610) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_jscc(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_jscc(cpustate, op, op2, &cycle_count);
 	}
 	/* JScc : 0000 0110 RR00 cccc : A-112 */
 	else if ((op & 0xff30) == 0x0600)
 	{
-		size = dsp56k_op_jscc_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_jscc_1(cpustate, op, &cycle_count);
 	}
 	/* JSR : 0000 0001 0011 00-- xxxx xxxx xxxx xxxx : A-114 */
 	else if (((op & 0xfffc) == 0x0130) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_jsr(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_jsr(cpustate, op, op2, &cycle_count);
 	}
 	/* JSR : 0000 1010 AAAA AAAA : A-114 */
 	else if ((op & 0xff00) == 0x0a00)
 	{
-		size = dsp56k_op_jsr_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_jsr_1(cpustate, op, &cycle_count);
 	}
 	/* JSR : 0000 0001 0010 00RR : A-114 */
 	else if ((op & 0xfffc) == 0x0120)
 	{
-		size = dsp56k_op_jsr_2(cpustate, op, &cycle_count);
+		size = dsp56156_op_jsr_2(cpustate, op, &cycle_count);
 	}
 	/* LEA : 0000 0001 11TT MMRR : A-116 */
 	else if ((op & 0xffc0) == 0x01c0)
 	{
-		size = dsp56k_op_lea(cpustate, op, &cycle_count);
+		size = dsp56156_op_lea(cpustate, op, &cycle_count);
 	}
 	/* LEA : 0000 0001 10NN MMRR : A-116 */
 	else if ((op & 0xffc0) == 0x0180)
 	{
-		size = dsp56k_op_lea_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_lea_1(cpustate, op, &cycle_count);
 	}
 	/* MAC(su,uu) : 0001 0101 1110 FsQQ : A-126 */
 	else if ((op & 0xfff0) == 0x15e0)
 	{
-		size = dsp56k_op_macsuuu(cpustate, op, &cycle_count);
+		size = dsp56156_op_macsuuu(cpustate, op, &cycle_count);
 	}
 	/* MOVE : 0000 0101 BBBB BBBB ---- HHHW 0001 0001 : A-128 */
 	else if (((op & 0xff00) == 0x0500) && ((op2 & 0x00ff) == 0x0011))
 	{
-		size = dsp56k_op_move_2(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_move_2(cpustate, op, op2, &cycle_count);
 	}
 	/* MOVE(C) : 0011 1WDD DDD0 MMRR : A-144 */
 	else if ((op & 0xf810) == 0x3800)
 	{
-		size = dsp56k_op_movec(cpustate, op, &cycle_count);
+		size = dsp56156_op_movec(cpustate, op, &cycle_count);
 	}
 	/* MOVE(C) : 0011 1WDD DDD1 q0RR : A-144 */
 	else if ((op & 0xf814) == 0x3810)
 	{
-		size = dsp56k_op_movec_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_movec_1(cpustate, op, &cycle_count);
 	}
 	/* MOVE(C) : 0011 1WDD DDD1 Z11- : A-144 */
 	else if ((op & 0xf816) == 0x3816)
 	{
-		size = dsp56k_op_movec_2(cpustate, op, &cycle_count);
+		size = dsp56156_op_movec_2(cpustate, op, &cycle_count);
 	}
 	/* MOVE(C) : 0011 1WDD DDD1 t10- xxxx xxxx xxxx xxxx : A-144 */
 	else if (((op & 0xf816) == 0x3814) && ((op2 & 0x0000) == 0x0000))
 	{
-		size = dsp56k_op_movec_3(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_movec_3(cpustate, op, op2, &cycle_count);
 	}
 	/* MOVE(C) : 0010 10dd dddD DDDD : A-144 */
 	else if ((op & 0xfc00) == 0x2800)
 	{
-		size = dsp56k_op_movec_4(cpustate, op, &cycle_count);
+		size = dsp56156_op_movec_4(cpustate, op, &cycle_count);
 	}
 	/* MOVE(C) : 0000 0101 BBBB BBBB 0011 1WDD DDD0 ---- : A-144 */
 	else if (((op & 0xff00) == 0x0500) && ((op2 & 0xf810) == 0x3800))
 	{
-		size = dsp56k_op_movec_5(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_movec_5(cpustate, op, op2, &cycle_count);
 	}
 	/* MOVE(I) : 0010 00DD BBBB BBBB : A-150 */
 	else if ((op & 0xfc00) == 0x2000)
 	{
-		size = dsp56k_op_movei(cpustate, op, &cycle_count);
+		size = dsp56156_op_movei(cpustate, op, &cycle_count);
 	}
 	/* MOVE(M) : 0000 001W RR0M MHHH : A-152 */
 	else if ((op & 0xfe20) == 0x0200)
 	{
-		size = dsp56k_op_movem(cpustate, op, &cycle_count);
+		size = dsp56156_op_movem(cpustate, op, &cycle_count);
 	}
 	/* MOVE(M) : 0000 001W RR11 mmRR : A-152 */
 	else if ((op & 0xfe30) == 0x0230)
 	{
-		size = dsp56k_op_movem_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_movem_1(cpustate, op, &cycle_count);
 	}
 	/* MOVE(M) : 0000 0101 BBBB BBBB 0000 001W --0- -HHH : A-152 */
 	else if (((op & 0xff00) == 0x0500) && ((op2 & 0xfe20) == 0x0200))
 	{
-		size = dsp56k_op_movem_2(cpustate, op, op2, &cycle_count);
+		size = dsp56156_op_movem_2(cpustate, op, op2, &cycle_count);
 	}
 	/* MOVE(P) : 0001 100W HH1p pppp : A-156 */
 	else if ((op & 0xfe20) == 0x1820)
 	{
-		size = dsp56k_op_movep(cpustate, op, &cycle_count);
+		size = dsp56156_op_movep(cpustate, op, &cycle_count);
 	}
 	/* MOVE(P) : 0000 110W RRmp pppp : A-156 */
 	else if ((op & 0xfe00) == 0x0c00)
 	{
-		size = dsp56k_op_movep_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_movep_1(cpustate, op, &cycle_count);
 	}
 	/* MOVE(S) : 0001 100W HH0a aaaa : A-158 */
 	else if ((op & 0xfe20) == 0x1800)
 	{
-		size = dsp56k_op_moves(cpustate, op, &cycle_count);
+		size = dsp56156_op_moves(cpustate, op, &cycle_count);
 	}
 	/* MPY(su,uu) : 0001 0101 1100 FsQQ : A-164 */
 	else if ((op & 0xfff0) == 0x15c0)
 	{
-		size = dsp56k_op_mpysuuu(cpustate, op, &cycle_count);
+		size = dsp56156_op_mpysuuu(cpustate, op, &cycle_count);
 	}
 	/* NEGC : 0001 0101 0110 F000 : A-168 */
 	else if ((op & 0xfff7) == 0x1560)
 	{
-		size = dsp56k_op_negc(cpustate, op, &cycle_count);
+		size = dsp56156_op_negc(cpustate, op, &cycle_count);
 	}
 	/* NOP : 0000 0000 0000 0000 : A-170 */
 	else if ((op & 0xffff) == 0x0000)
 	{
-		size = dsp56k_op_nop(cpustate, op, &cycle_count);
+		size = dsp56156_op_nop(cpustate, op, &cycle_count);
 	}
 	/* NORM : 0001 0101 0010 F0RR : A-172 */
 	else if ((op & 0xfff4) == 0x1520)
 	{
-		size = dsp56k_op_norm(cpustate, op, &cycle_count);
+		size = dsp56156_op_norm(cpustate, op, &cycle_count);
 	}
 	/* ORI : 0001 1EE1 iiii iiii : A-178 */
 	else if ((op & 0xf900) == 0x1900)
 	{
-		size = dsp56k_op_ori(cpustate, op, &cycle_count);
+		size = dsp56156_op_ori(cpustate, op, &cycle_count);
 	}
 	/* REP : 0000 0000 111- --RR : A-180 */
 	else if ((op & 0xffe0) == 0x00e0)
 	{
-		size = dsp56k_op_rep(cpustate, op, &cycle_count);
+		size = dsp56156_op_rep(cpustate, op, &cycle_count);
 	}
 	/* REP : 0000 1111 iiii iiii : A-180 */
 	else if ((op & 0xff00) == 0x0f00)
 	{
-		size = dsp56k_op_rep_1(cpustate, op, &cycle_count);
+		size = dsp56156_op_rep_1(cpustate, op, &cycle_count);
 	}
 	/* REP : 0000 0100 001D DDDD : A-180 */
 	else if ((op & 0xffe0) == 0x0420)
 	{
-		size = dsp56k_op_rep_2(cpustate, op, &cycle_count);
+		size = dsp56156_op_rep_2(cpustate, op, &cycle_count);
 	}
 	/* REPcc : 0000 0001 0101 cccc : A-184 */
 	else if ((op & 0xfff0) == 0x0150)
 	{
-		size = dsp56k_op_repcc(cpustate, op, &cycle_count);
+		size = dsp56156_op_repcc(cpustate, op, &cycle_count);
 	}
 	/* RESET : 0000 0000 0000 1000 : A-186 */
 	else if ((op & 0xffff) == 0x0008)
 	{
-		size = dsp56k_op_reset(cpustate, op, &cycle_count);
+		size = dsp56156_op_reset(cpustate, op, &cycle_count);
 	}
 	/* RTI : 0000 0000 0000 0111 : A-194 */
 	else if ((op & 0xffff) == 0x0007)
 	{
-		size = dsp56k_op_rti(cpustate, op, &cycle_count);
+		size = dsp56156_op_rti(cpustate, op, &cycle_count);
 	}
 	/* RTS : 0000 0000 0000 0110 : A-196 */
 	else if ((op & 0xffff) == 0x0006)
 	{
-		size = dsp56k_op_rts(cpustate, op, &cycle_count);
+		size = dsp56156_op_rts(cpustate, op, &cycle_count);
 	}
 	/* STOP : 0000 0000 0000 1010 : A-200 */
 	else if ((op & 0xffff) == 0x000a)
 	{
-		size = dsp56k_op_stop(cpustate, op, &cycle_count);
+		size = dsp56156_op_stop(cpustate, op, &cycle_count);
 	}
 	/* SWAP : 0001 0101 0111 F001 : A-206 */
 	else if ((op & 0xfff7) == 0x1571)
 	{
-		size = dsp56k_op_swap(cpustate, op, &cycle_count);
+		size = dsp56156_op_swap(cpustate, op, &cycle_count);
 	}
 	/* SWI : 0000 0000 0000 0101 : A-208 */
 	else if ((op & 0xffff) == 0x0005)
 	{
-		size = dsp56k_op_swi(cpustate, op, &cycle_count);
+		size = dsp56156_op_swi(cpustate, op, &cycle_count);
 	}
 	/* Tcc : 0001 00cc ccTT Fh0h : A-210 */
 	else if ((op & 0xfc02) == 0x1000)
 	{
-		size = dsp56k_op_tcc(cpustate, op, &cycle_count);
+		size = dsp56156_op_tcc(cpustate, op, &cycle_count);
 	}
 	/* TFR(2) : 0001 0101 0000 F00J : A-214 */
 	else if ((op & 0xfff6) == 0x1500)
 	{
-		size = dsp56k_op_tfr2(cpustate, op, &cycle_count);
+		size = dsp56156_op_tfr2(cpustate, op, &cycle_count);
 	}
 	/* TFR(3) : 0010 01mW RRDD FHHH : A-216 */
 	else if ((op & 0xfc00) == 0x2400)
 	{
-		size = dsp56k_op_tfr3(cpustate, op, &cycle_count);
+		size = dsp56156_op_tfr3(cpustate, op, &cycle_count);
 	}
 	/* TST(2) : 0001 0101 0001 -1DD : A-220 */
 	else if ((op & 0xfff4) == 0x1514)
 	{
-		size = dsp56k_op_tst2(cpustate, op, &cycle_count);
+		size = dsp56156_op_tst2(cpustate, op, &cycle_count);
 	}
 	/* WAIT : 0000 0000 0000 1011 : A-222 */
 	else if ((op & 0xffff) == 0x000b)
 	{
-		size = dsp56k_op_wait(cpustate, op, &cycle_count);
+		size = dsp56156_op_wait(cpustate, op, &cycle_count);
 	}
 	/* ZERO : 0001 0101 0101 F000 : A-224 */
 	else if ((op & 0xfff7) == 0x1550)
 	{
-		size = dsp56k_op_zero(cpustate, op, &cycle_count);
+		size = dsp56156_op_zero(cpustate, op, &cycle_count);
 	}
 
 
 	/* Not recognized?  Nudge debugger onto the next word */
 	if (size == 0x1337)
 	{
-		cpustate->device->logerror("DSP56k: Unimplemented opcode at 0x%04x : %04x\n", PC, op);
+		cpustate->device->logerror("DSP56156: Unimplemented opcode at 0x%04x : %04x\n", PC, op);
 		size = 1 ;                      /* Just to get the debugger past the bad opcode */
 	}
 
 	/* Must have been a good opcode */
 	PC += (uint16_t)size;
 
-	dsp56k_process_loop(cpustate);
-	dsp56k_process_rep(cpustate, size);
+	dsp56156_process_loop(cpustate);
+	dsp56156_process_rep(cpustate, size);
 
 	cpustate->icount -= 4;  /* Temporarily hard-coded at 4 clocks per opcode */ /* cycle_count */
 }
@@ -1115,7 +1115,7 @@ static void execute_one(dsp56k_core* cpustate)
 
 /* ADD : 011m mKKK 0rru Fuuu : A-22 */
 /* SUB : 011m mKKK 0rru Fuuu : A-202 */
-static size_t dsp56k_op_addsub_2(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
+static size_t dsp56156_op_addsub_2(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
 {
 	uint64_t useVal = 0;
 	uint8_t op_type = OP_OTHER;
@@ -1157,15 +1157,15 @@ static size_t dsp56k_op_addsub_2(dsp56k_core* cpustate, const uint16_t op_byte,
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
 	/* TODO S, L, E, U, V, C */
-	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if (*((uint64_t*)D.addr) == 0)                  DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if (*((uint64_t*)D.addr) == 0)                  DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator cycles */
 	return 1;
 }
 
 /* MAC : 011m mKKK 1xx0 F1QQ : A-122 */
-static size_t dsp56k_op_mac_1(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
+static size_t dsp56156_op_mac_1(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
 {
 	int64_t opD = 0;
 	int64_t result = 0;
@@ -1208,15 +1208,15 @@ static size_t dsp56k_op_mac_1(dsp56k_core* cpustate, const uint16_t op_byte, typ
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
 	/* TODO: S, L, E, V */
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: +mv oscillator cycles */
 	return 1;
 }
 
 /* MACR: 011m mKKK 1--1 F1QQ : A-124 */
-static size_t dsp56k_op_macr_1(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
+static size_t dsp56156_op_macr_1(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
@@ -1224,7 +1224,7 @@ static size_t dsp56k_op_macr_1(dsp56k_core* cpustate, const uint16_t op_byte, ty
 }
 
 /* MOVE : 011m mKKK 0rr1 0000 : A-128 */
-static size_t dsp56k_op_move_1(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
+static size_t dsp56156_op_move_1(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - - - - - */
@@ -1232,7 +1232,7 @@ static size_t dsp56k_op_move_1(dsp56k_core* cpustate, const uint16_t op_byte, ty
 }
 
 /* MPY : 011m mKKK 1xx0 F0QQ : A-160 */
-static size_t dsp56k_op_mpy_1(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
+static size_t dsp56156_op_mpy_1(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
 {
 	int64_t result = 0;
 
@@ -1262,15 +1262,15 @@ static size_t dsp56k_op_mpy_1(dsp56k_core* cpustate, const uint16_t op_byte, typ
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
 	/* TODO: S, L, E, V */
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: +mv oscillator cycles */
 	return 1;
 }
 
 /* MPYR : 011m mKKK 1--1 F0QQ : A-162 */
-static size_t dsp56k_op_mpyr_1(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
+static size_t dsp56156_op_mpyr_1(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
@@ -1278,7 +1278,7 @@ static size_t dsp56k_op_mpyr_1(dsp56k_core* cpustate, const uint16_t op_byte, ty
 }
 
 /* TFR : 011m mKKK 0rr1 F0DD : A-212 */
-static size_t dsp56k_op_tfr_2(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
+static size_t dsp56156_op_tfr_2(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -1286,7 +1286,7 @@ static size_t dsp56k_op_tfr_2(dsp56k_core* cpustate, const uint16_t op_byte, typ
 }
 
 /* MPY : 0001 0110 RRDD FQQQ : A-160 */
-static size_t dsp56k_op_mpy_2(dsp56k_core* cpustate, const uint16_t op_byte, uint8_t* cycles)
+static size_t dsp56156_op_mpy_2(dsp56156_core* cpustate, const uint16_t op_byte, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
@@ -1294,7 +1294,7 @@ static size_t dsp56k_op_mpy_2(dsp56k_core* cpustate, const uint16_t op_byte, uin
 }
 
 /* MAC : 0001 0111 RRDD FQQQ : A-122 */
-static size_t dsp56k_op_mac_2(dsp56k_core* cpustate, const uint16_t op_byte, uint8_t* cycles)
+static size_t dsp56156_op_mac_2(dsp56156_core* cpustate, const uint16_t op_byte, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
@@ -1302,7 +1302,7 @@ static size_t dsp56k_op_mac_2(dsp56k_core* cpustate, const uint16_t op_byte, uin
 }
 
 /* CLR : .... .... 0000 F001 : A-60 */
-static size_t dsp56k_op_clr(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_clr(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_LONG_WORD};
 	typed_pointer clear = {nullptr, DT_LONG_WORD};
@@ -1322,18 +1322,18 @@ static size_t dsp56k_op_clr(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * 0 - */
 	/* TODO - S, L */
-	DSP56K_E_CLEAR();
-	DSP56K_U_SET();
-	DSP56K_N_CLEAR();
-	DSP56K_Z_SET();
-	DSP56K_V_CLEAR();
+	DSP56156_E_CLEAR();
+	DSP56156_U_SET();
+	DSP56156_N_CLEAR();
+	DSP56156_Z_SET();
+	DSP56156_V_CLEAR();
 
 	cycles += 2;    /* TODO: + mv oscillator clock cycles */
 	return 1;
 }
 
 /* ADD : .... .... 0000 FJJJ : A-22 */
-static size_t dsp56k_op_add(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_add(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	uint64_t addVal = 0;
 
@@ -1363,15 +1363,15 @@ static size_t dsp56k_op_add(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
 	/* TODO S, L, E, U, V, C */
-	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if (*((uint64_t*)D.addr) == 0)                  DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if (*((uint64_t*)D.addr) == 0)                  DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator cycles */
 	return 1;
 }
 
 /* MOVE : .... .... 0001 0001 : A-128 */
-static size_t dsp56k_op_move(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_move(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* Equivalent to a nop with a parallel move */
 	/* These can't be used later.  Hopefully compilers would pick this up. */
@@ -1387,7 +1387,7 @@ static size_t dsp56k_op_move(dsp56k_core* cpustate, const uint16_t op_byte, type
 }
 
 /* TFR : .... .... 0001 FJJJ : A-212 */
-static size_t dsp56k_op_tfr(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_tfr(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer S = {nullptr, DT_BYTE};
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -1409,7 +1409,7 @@ static size_t dsp56k_op_tfr(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* RND : .... .... 0010 F000 : A-188 */
-static size_t dsp56k_op_rnd(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_rnd(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_BYTE};
 
@@ -1429,15 +1429,15 @@ static size_t dsp56k_op_rnd(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
 	/* TODO: S, L, E, U, V */
-	if ((*((uint64_t*)D.addr)) & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr)) == 0)                  DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ((*((uint64_t*)D.addr)) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr)) == 0)                  DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator clock cycles */
 	return 1;
 }
 
 /* TST : .... .... 0010 F001 : A-218 */
-static size_t dsp56k_op_tst(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_tst(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_LONG_WORD};
 
@@ -1451,17 +1451,17 @@ static size_t dsp56k_op_tst(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* 0 * * * * * 0 0 */
 	/* TODO: S, L, E, U */
-	if ((*((uint64_t*)D.addr)) & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr)) == 0)                  DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
-	DSP56K_C_CLEAR();
+	if ((*((uint64_t*)D.addr)) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr)) == 0)                  DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
+	DSP56156_C_CLEAR();
 
 	cycles += 2;    /* TODO: + mv oscillator clock cycles */
 	return 1;
 }
 
 /* INC : .... .... 0010 F010 : A-104 */
-static size_t dsp56k_op_inc(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_inc(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_BYTE};
 	decode_F_table(cpustate, BITS(op_byte,0x0008), &D);
@@ -1481,17 +1481,17 @@ static size_t dsp56k_op_inc(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
 	/* TODO: S, L, E, U */
-	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0xffffff0000000000U) != 0) DSP56K_V_SET(); else DSP56K_V_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0xffffff0000000000U) != 0) DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0xffffff0000000000U) != 0) DSP56156_V_SET(); else DSP56156_V_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0xffffff0000000000U) != 0) DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;    /* TODO: +mv oscillator cycles */
 	return 1;
 }
 
 /* INC24 : .... .... 0010 F011 : A-106 */
-static size_t dsp56k_op_inc24(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_inc24(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	uint32_t workBits24;
 
@@ -1516,17 +1516,17 @@ static size_t dsp56k_op_inc24(dsp56k_core* cpustate, const uint16_t op_byte, typ
 	/* S L E U N Z V C */
 	/* * * * * * ? * * */
 	/* TODO: S, L, E, U */
-	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	if ((workBits24 & 0xff000000) != 0) DSP56K_V_SET(); else DSP56K_V_CLEAR();
-	if ((workBits24 & 0xff000000) != 0) DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	if ((workBits24 & 0xff000000) != 0) DSP56156_V_SET(); else DSP56156_V_CLEAR();
+	if ((workBits24 & 0xff000000) != 0) DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator clock cycles */
 	return 1;
 }
 
 /* OR : .... .... 0010 F1JJ : A-176 */
-static size_t dsp56k_op_or(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_or(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer S = {nullptr, DT_BYTE};
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -1545,16 +1545,16 @@ static size_t dsp56k_op_or(dsp56k_core* cpustate, const uint16_t op_byte, typed_
 	/* S L E U N Z V C */
 	/* * * - - ? ? 0 - */
 	/* TODO: S, L */
-	if ( *((uint64_t*)D.addr) & 0x0000000080000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0x00000000ffff0000U) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
+	if ( *((uint64_t*)D.addr) & 0x0000000080000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0x00000000ffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator cycles */
 	return 1;
 }
 
 /* ASR : .... .... 0011 F000 : A-32 */
-static size_t dsp56k_op_asr(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_asr(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_BYTE};
 	decode_F_table(cpustate, BITS(op_byte,0x0008), &D);
@@ -1576,17 +1576,17 @@ static size_t dsp56k_op_asr(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * 0 ? */
 	/* TODO: S, L, E, U */
-	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if (*((uint64_t*)D.addr) == 0)                  DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
-	if (*p_accum & 0x0000000000000001U)           DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if (*((uint64_t*)D.addr) == 0)                  DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
+	if (*p_accum & 0x0000000000000001U)           DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator cycles */
 	return 1;
 }
 
 /* ASL : .... .... 0011 F001 : A-28 */
-static size_t dsp56k_op_asl(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_asl(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * ? ? */
@@ -1597,7 +1597,7 @@ static size_t dsp56k_op_asl(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* LSR : .... .... 0011 F010 : A-120 */
-static size_t dsp56k_op_lsr(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_lsr(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_BYTE};
 	decode_F_table(cpustate, BITS(op_byte,0x0008), &D);
@@ -1616,17 +1616,17 @@ static size_t dsp56k_op_lsr(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * - - ? ? 0 ? */
 	/* TODO: S, L */
-	DSP56K_N_CLEAR();
-	if (((PAIR64*)D.addr)->w.h == 0)    DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
-	if (*p_accum & 0x0000000000010000U) DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	DSP56156_N_CLEAR();
+	if (((PAIR64*)D.addr)->w.h == 0)    DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
+	if (*p_accum & 0x0000000000010000U) DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator cycles */
 	return 1;
 }
 
 /* LSL : .... .... 0011 F011 : A-118 */
-static size_t dsp56k_op_lsl(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_lsl(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - ? ? 0 ? */
@@ -1637,7 +1637,7 @@ static size_t dsp56k_op_lsl(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* EOR : .... .... 0011 F1JJ : A-94 */
-static size_t dsp56k_op_eor(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_eor(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - ? ? 0 - */
@@ -1647,7 +1647,7 @@ static size_t dsp56k_op_eor(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* SUBL : .... .... 0100 F001 : A-204 */
-static size_t dsp56k_op_subl(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_subl(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * ? * */
@@ -1657,7 +1657,7 @@ static size_t dsp56k_op_subl(dsp56k_core* cpustate, const uint16_t op_byte, type
 }
 
 /* SUB : .... .... 0100 FJJJ : A-202 */
-static size_t dsp56k_op_sub(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_sub(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	uint64_t useVal = 0;
 	typed_pointer S = {nullptr, DT_BYTE};
@@ -1690,17 +1690,17 @@ static size_t dsp56k_op_sub(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
 	/* TODO S, L, E, U */
-	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)        DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ( *((uint64_t*)D.addr) == 0)                         DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0xffffff0000000000U) != 0)  DSP56K_V_SET(); else DSP56K_V_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0xffffff0000000000U) != 0)  DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)        DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ( *((uint64_t*)D.addr) == 0)                         DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0xffffff0000000000U) != 0)  DSP56156_V_SET(); else DSP56156_V_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0xffffff0000000000U) != 0)  DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator cycles */
 	return 1;
 }
 
 /* CLR24 : .... .... 0101 F001 : A-62 */
-static size_t dsp56k_op_clr24(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_clr24(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * ? 0 - */
@@ -1709,7 +1709,7 @@ static size_t dsp56k_op_clr24(dsp56k_core* cpustate, const uint16_t op_byte, typ
 }
 
 /* SBC : .... .... 0101 F01J : A-198 */
-static size_t dsp56k_op_sbc(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_sbc(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
@@ -1717,7 +1717,7 @@ static size_t dsp56k_op_sbc(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* CMP : .... .... 0101 FJJJ : A-64 */
-static size_t dsp56k_op_cmp(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_cmp(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	uint64_t cmpVal = 0;
 	uint64_t result = 0;
@@ -1753,10 +1753,10 @@ static size_t dsp56k_op_cmp(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
 	/* TODO: S, L, E, U */
-	if ( result & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ( result == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	if ((result & 0xffffff0000000000U) != 0) DSP56K_V_SET(); else DSP56K_V_CLEAR();
-	if ((result & 0xffffff0000000000U) != 0) DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if ( result & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ( result == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	if ((result & 0xffffff0000000000U) != 0) DSP56156_V_SET(); else DSP56156_V_CLEAR();
+	if ((result & 0xffffff0000000000U) != 0) DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 
 	cycles += 2;        /* TODO: + mv oscillator clock cycles */
@@ -1764,7 +1764,7 @@ static size_t dsp56k_op_cmp(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* NEG : .... .... 0110 F000 : A-166 */
-static size_t dsp56k_op_neg(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_neg(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
@@ -1772,7 +1772,7 @@ static size_t dsp56k_op_neg(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* NOT : .... .... 0110 F001 : A-174 */
-static size_t dsp56k_op_not(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_not(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_BYTE};
 	decode_F_table(cpustate, BITS(op_byte,0x0008), &D);
@@ -1788,16 +1788,16 @@ static size_t dsp56k_op_not(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * - - ? ? 0 - */
 	/* TODO: S?, L */
-	if ( *((uint64_t*)D.addr) & 0x0000000080000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0x00000000ffff0000U) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
+	if ( *((uint64_t*)D.addr) & 0x0000000080000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0x00000000ffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator cycles */
 	return 1;
 }
 
 /* DEC : .... .... 0110 F010 : A-72 */
-static size_t dsp56k_op_dec(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_dec(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
@@ -1805,7 +1805,7 @@ static size_t dsp56k_op_dec(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* DEC24 : .... .... 0110 F011 : A-74 */
-static size_t dsp56k_op_dec24(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_dec24(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	uint32_t workBits24;
 
@@ -1830,15 +1830,15 @@ static size_t dsp56k_op_dec24(dsp56k_core* cpustate, const uint16_t op_byte, typ
 	/* S L E U N Z V C */
 	/* * * * * * ? * * */
 	/* TODO: S, L, E, U, V, C */
-	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator clock cycles */
 	return 1;
 }
 
 /* AND : .... .... 0110 F1JJ : A-24 */
-static size_t dsp56k_op_and(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_and(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	typed_pointer S = {nullptr, DT_BYTE};
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -1857,16 +1857,16 @@ static size_t dsp56k_op_and(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * - - ? ? 0 - */
 	/* TODO: S, L */
-	if ( *((uint64_t*)D.addr) & 0x0000000080000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0x00000000ffff0000U) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
+	if ( *((uint64_t*)D.addr) & 0x0000000080000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0x00000000ffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
 
 	cycles += 2;        /* TODO: + mv oscillator cycles */
 	return 1;
 }
 
 /* ABS : .... .... 0111 F001 : A-18 */
-static size_t dsp56k_op_abs(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_abs(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	int64_t opD = 0;
 	typed_pointer D = {nullptr, DT_LONG_WORD};
@@ -1896,16 +1896,16 @@ static size_t dsp56k_op_abs(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
 	/* TODO: S, L, E, U */
-	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D.addr) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	if ((*p_accum)         == 0x0000008000000000U)       DSP56K_V_SET(); else DSP56K_V_CLEAR();
+	if ( *((uint64_t*)D.addr) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D.addr) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	if ((*p_accum)         == 0x0000008000000000U)       DSP56156_V_SET(); else DSP56156_V_CLEAR();
 
 	cycles += 2;            /* TODO: + mv oscillator clock cycles */
 	return 1;
 }
 
 /* ROR : .... .... 0111 F010 : A-192 */
-static size_t dsp56k_op_ror(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_ror(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - ? ? 0 ? */
@@ -1916,7 +1916,7 @@ static size_t dsp56k_op_ror(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* ROL : .... .... 0111 F011 : A-190 */
-static size_t dsp56k_op_rol(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_rol(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - ? ? 0 ? */
@@ -1927,7 +1927,7 @@ static size_t dsp56k_op_rol(dsp56k_core* cpustate, const uint16_t op_byte, typed
 }
 
 /* CMPM : .... .... 0111 FJJJ : A-66 */
-static size_t dsp56k_op_cmpm(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_cmpm(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	int64_t absS;
 	int64_t absD;
@@ -1979,17 +1979,17 @@ static size_t dsp56k_op_cmpm(dsp56k_core* cpustate, const uint16_t op_byte, type
 	/* S L E U N Z V C */
 	/* * * * * * * * * */
 	/* TODO: S, L, E, U */
-	if ( (absResult) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if (((absResult) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	if ( (absResult  & 0xffffff0000000000U) != 0)  DSP56K_V_SET(); else DSP56K_V_CLEAR();
-	if ( (absResult  & 0xffffff0000000000U) != 0)  DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if ( (absResult) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if (((absResult) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	if ( (absResult  & 0xffffff0000000000U) != 0)  DSP56156_V_SET(); else DSP56156_V_CLEAR();
+	if ( (absResult  & 0xffffff0000000000U) != 0)  DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;        /* TODO: +mv oscillator cycles */
 	return 1;
 }
 
 /* MPY : .... .... 1k00 FQQQ : A-160    -- CONFIRMED TYPO IN DOCS (HHHH vs HHHW) */
-static size_t dsp56k_op_mpy(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_mpy(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	uint16_t k = 0;
 	int64_t result = 0;
@@ -2021,15 +2021,15 @@ static size_t dsp56k_op_mpy(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
 	/* TODO: S, L, E, V */
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: +mv oscillator cycles */
 	return 1;
 }
 
 /* MPYR : .... .... 1k01 FQQQ : A-162 */
-static size_t dsp56k_op_mpyr(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_mpyr(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
@@ -2037,7 +2037,7 @@ static size_t dsp56k_op_mpyr(dsp56k_core* cpustate, const uint16_t op_byte, type
 }
 
 /* MAC : .... .... 1k10 FQQQ : A-122 */
-static size_t dsp56k_op_mac(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_mac(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	uint16_t k = 0;
 	int64_t opD = 0;
@@ -2087,15 +2087,15 @@ static size_t dsp56k_op_mac(dsp56k_core* cpustate, const uint16_t op_byte, typed
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
 	/* TODO: S, L, E, V */
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: +mv oscillator cycles */
 	return 1;
 }
 
 /* MACR : .... .... 1k11 FQQQ : A-124   -- DRAMA - rr vs xx (805) */
-static size_t dsp56k_op_macr(dsp56k_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
+static size_t dsp56156_op_macr(dsp56156_core* cpustate, const uint16_t op_byte, typed_pointer* d_register, uint64_t* p_accum, uint8_t* cycles)
 {
 	uint16_t k = 0;
 	int64_t opD = 0;
@@ -2153,8 +2153,8 @@ static size_t dsp56k_op_macr(dsp56k_core* cpustate, const uint16_t op_byte, type
 	/* S L E U N Z V C */
 	/* * * * * * * * - */
 	/* TODO: S, L, E, V */
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;        /* TODO: +mv oscillator cycles */
 	return 1;
@@ -2166,7 +2166,7 @@ static size_t dsp56k_op_macr(dsp56k_core* cpustate, const uint16_t op_byte, type
 /******************************/
 
 /* ADC : 0001 0101 0000 F01J : A-20 */
-static size_t dsp56k_op_adc(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_adc(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - * * * * * * * */
@@ -2174,7 +2174,7 @@ static size_t dsp56k_op_adc(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* ANDI : 0001 1EE0 iiii iiii : A-26 */
-static size_t dsp56k_op_andi(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_andi(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint16_t immediate = BITS(op,0x00ff);
 
@@ -2194,7 +2194,7 @@ static size_t dsp56k_op_andi(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 			break;
 
 		default:
-			fatalerror("DSP56k - BAD EE value in andi operation\n") ;
+			fatalerror("DSP56156 - BAD EE value in andi operation\n") ;
 	}
 
 	/* S L E U N Z V C */
@@ -2206,7 +2206,7 @@ static size_t dsp56k_op_andi(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* ASL4 : 0001 0101 0011 F001 : A-30 */
-static size_t dsp56k_op_asl4(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_asl4(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint64_t p_accum = 0;
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -2223,17 +2223,17 @@ static size_t dsp56k_op_asl4(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 	/* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if bit 35 through 39 are
 	       not the same. */
 	/* C - Set if bit 36 of source operand is set. Cleared otherwise. */
-	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if (*((uint64_t*)D.addr) == 0)                  DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	if ( (*((uint64_t*)D.addr) & 0x000000ff00000000U) != (p_accum & 0x000000ff00000000U) ) DSP56K_V_SET(); else DSP56K_V_CLEAR();
-	if (p_accum & 0x0000001000000000U)              DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if (*((uint64_t*)D.addr) == 0)                  DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	if ( (*((uint64_t*)D.addr) & 0x000000ff00000000U) != (p_accum & 0x000000ff00000000U) ) DSP56156_V_SET(); else DSP56156_V_CLEAR();
+	if (p_accum & 0x0000001000000000U)              DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;
 	return 1;
 }
 
 /* ASR4 : 0001 0101 0011 F000 : A-34 */
-static size_t dsp56k_op_asr4(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_asr4(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint64_t p_accum = 0;
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -2254,17 +2254,17 @@ static size_t dsp56k_op_asr4(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 	/* - * * * * * 0 ? */
 	/* TODO: E, U  */
 	/* C - Set if bit 3 of source operand is set. Cleared otherwise. */
-	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if (*((uint64_t*)D.addr) == 0)                  DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
-	if (p_accum & 0x0000000000000008U)              DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if (*((uint64_t*)D.addr) == 0)                  DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
+	if (p_accum & 0x0000000000000008U)              DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;
 	return 1;
 }
 
 /* ASR16 : 0001 0101 0111 F000 : A-36 */
-static size_t dsp56k_op_asr16(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_asr16(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint64_t backupVal;
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -2283,10 +2283,10 @@ static size_t dsp56k_op_asr16(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 	/* S L E U N Z V C */
 	/* - * * * * * 0 ? */
 	/* TODO: E, U */
-	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if (*((uint64_t*)D.addr) == 0)                  DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
-	if (backupVal & 0x0000000000008000U)            DSP56K_C_SET(); else DSP56K_C_CLEAR();
+	if (*((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if (*((uint64_t*)D.addr) == 0)                  DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
+	if (backupVal & 0x0000000000008000U)            DSP56156_C_SET(); else DSP56156_C_CLEAR();
 
 	cycles += 2;
 	return 1;
@@ -2297,7 +2297,7 @@ static size_t dsp56k_op_asr16(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 /* BFSET  : 0001 0100 11Pp pppp BBB1 1000 iiii iiii : A-42 */
 /* BFTSTH : 0001 0100 01Pp pppp BBB1 0000 iiii iiii : A-44 */
 /* BFTSTL : 0001 0100 01Pp pppp BBB0 0000 iiii iiii : A-46 */
-static size_t dsp56k_op_bfop(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_bfop(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	uint16_t workAddr = 0x0000;
 	uint16_t workingWord = 0x0000;
@@ -2340,15 +2340,15 @@ static size_t dsp56k_op_bfop(dsp56k_core* cpustate, const uint16_t op, const uin
 	switch(BITS(op2, 0x1f00))
 	{
 		case 0x12:  /* BFCHG */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x04:  /* BFCLR */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x18:  /* BFSET */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x10:  /* BFTSTH */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x00:  /* BFTSTL */
-			if ((iVal & previousValue) == 0x0000) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 	}
 
 	cycles += 4;    /* TODO: + mvb oscillator clock cycles */
@@ -2360,7 +2360,7 @@ static size_t dsp56k_op_bfop(dsp56k_core* cpustate, const uint16_t op, const uin
 /* BFSET  : 0001 0100 101- --RR BBB1 1000 iiii iiii : A-42 */
 /* BFTSTH : 0001 0100 001- --RR BBB1 0000 iiii iiii : A-44 */
 /* BFTSTL : 0001 0100 001- --RR BBB0 0000 iiii iiii : A-46 */
-static size_t dsp56k_op_bfop_1(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_bfop_1(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	uint16_t workAddr = 0x0000;
 	uint16_t workingWord = 0x0000;
@@ -2406,15 +2406,15 @@ static size_t dsp56k_op_bfop_1(dsp56k_core* cpustate, const uint16_t op, const u
 	switch(BITS(op2, 0x1f00))
 	{
 		case 0x12:  /* BFCHG */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x04:  /* BFCLR */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x18:  /* BFSET */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x10:  /* BFTSTH */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x00:  /* BFTSTL */
-			if ((iVal & previousValue) == 0x0000) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 	}
 
 	cycles += 4;    /* TODO: + mvb oscillator clock cycles */
@@ -2426,7 +2426,7 @@ static size_t dsp56k_op_bfop_1(dsp56k_core* cpustate, const uint16_t op, const u
 /* BFSET  : 0001 0100 100D DDDD BBB1 1000 iiii iiii : A-42 */
 /* BFTSTH : 0001 0100 000D DDDD BBB1 0000 iiii iiii : A-44 */
 /* BFTSTL : 0001 0100 000D DDDD BBB0 0000 iiii iiii : A-46 */
-static size_t dsp56k_op_bfop_2(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_bfop_2(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	uint16_t workingWord = 0x0000;
 	uint16_t previousValue = 0x0000;
@@ -2476,15 +2476,15 @@ static size_t dsp56k_op_bfop_2(dsp56k_core* cpustate, const uint16_t op, const u
 	switch(BITS(op2, 0x1f00))
 	{
 		case 0x12:  /* BFCHG */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x04:  /* BFCLR */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x18:  /* BFSET */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x10:  /* BFTSTH */
-			if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 		case 0x00:  /* BFTSTL */
-			if ((iVal & previousValue) == 0x0000) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
+			if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
 	}
 
 	cycles += 4;    /* TODO: + mvb oscillator clock cycles */
@@ -2492,7 +2492,7 @@ static size_t dsp56k_op_bfop_2(dsp56k_core* cpustate, const uint16_t op, const u
 }
 
 /* Bcc : 0000 0111 --11 cccc xxxx xxxx xxxx xxxx : A-48 */
-static size_t dsp56k_op_bcc(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_bcc(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	int shouldBranch = decode_cccc_table(cpustate, BITS(op,0x000f));
 
@@ -2517,7 +2517,7 @@ static size_t dsp56k_op_bcc(dsp56k_core* cpustate, const uint16_t op, const uint
 }
 
 /* Bcc : 0010 11cc ccee eeee : A-48 */
-static size_t dsp56k_op_bcc_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_bcc_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	int shouldBranch = decode_cccc_table(cpustate, BITS(op,0x03c0));
 
@@ -2542,7 +2542,7 @@ static size_t dsp56k_op_bcc_1(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* Bcc : 0000 0111 RR10 cccc : A-48 */
-static size_t dsp56k_op_bcc_2(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_bcc_2(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2550,7 +2550,7 @@ static size_t dsp56k_op_bcc_2(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* BRA : 0000 0001 0011 11-- xxxx xxxx xxxx xxxx : A-50 */
-static size_t dsp56k_op_bra(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_bra(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2558,7 +2558,7 @@ static size_t dsp56k_op_bra(dsp56k_core* cpustate, const uint16_t op, const uint
 }
 
 /* BRA : 0000 1011 aaaa aaaa : A-50 */
-static size_t dsp56k_op_bra_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_bra_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* 8 bit immediate, relative offset */
 	int8_t branchOffset = (int8_t)BITS(op,0x00ff);
@@ -2576,7 +2576,7 @@ static size_t dsp56k_op_bra_1(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* BRA : 0000 0001 0010 11RR : A-50 */
-static size_t dsp56k_op_bra_2(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_bra_2(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2584,7 +2584,7 @@ static size_t dsp56k_op_bra_2(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* BRKcc : 0000 0001 0001 cccc : A-52 */
-static size_t dsp56k_op_brkcc(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_brkcc(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	int shouldBreak = decode_cccc_table(cpustate, BITS(op,0x000f));
 
@@ -2615,7 +2615,7 @@ static size_t dsp56k_op_brkcc(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* BScc : 0000 0111 --01 cccc xxxx xxxx xxxx xxxx : A-54 */
-static size_t dsp56k_op_bscc(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_bscc(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	int shouldBranch = decode_cccc_table(cpustate, BITS(op,0x000f));
 
@@ -2645,7 +2645,7 @@ static size_t dsp56k_op_bscc(dsp56k_core* cpustate, const uint16_t op, const uin
 }
 
 /* BScc : 0000 0111 RR00 cccc : A-54 */
-static size_t dsp56k_op_bscc_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_bscc_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2653,7 +2653,7 @@ static size_t dsp56k_op_bscc_1(dsp56k_core* cpustate, const uint16_t op, uint8_t
 }
 
 /* BSR : 0000 0001 0011 10-- xxxx xxxx xxxx xxxx : A-56 */
-static size_t dsp56k_op_bsr(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_bsr(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	/* The PC Contains the address of the next instruction */
 	PC += 2;
@@ -2673,7 +2673,7 @@ static size_t dsp56k_op_bsr(dsp56k_core* cpustate, const uint16_t op, const uint
 }
 
 /* BSR : 0000 0001 0010 10RR : A-56 */
-static size_t dsp56k_op_bsr_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_bsr_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2681,7 +2681,7 @@ static size_t dsp56k_op_bsr_1(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* CHKAAU : 0000 0000 0000 0100 : A-58 */
-static size_t dsp56k_op_chkaau(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_chkaau(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - ? ? ? - */
@@ -2695,7 +2695,7 @@ static size_t dsp56k_op_chkaau(dsp56k_core* cpustate, const uint16_t op, uint8_t
 }
 
 /* DEBUG : 0000 0000 0000 0001 : A-68 */
-static size_t dsp56k_op_debug(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_debug(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2703,7 +2703,7 @@ static size_t dsp56k_op_debug(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* DEBUGcc : 0000 0000 0101 cccc : A-70 */
-static size_t dsp56k_op_debugcc(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_debugcc(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2712,7 +2712,7 @@ static size_t dsp56k_op_debugcc(dsp56k_core* cpustate, const uint16_t op, uint8_
 
 /* DIV : 0001 0101 0--0 F1DD : A-76 */
 /* WARNING : DOCS SAY THERE IS A PARALLEL MOVE HERE !!! */
-static size_t dsp56k_op_div(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_div(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* WARNING : THIS DOES NOT WORK.  IT DOESN'T EVEN TRY !!! */
 	typed_pointer S = {nullptr, DT_BYTE};
@@ -2730,7 +2730,7 @@ static size_t dsp56k_op_div(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* DMAC : 0001 0101 10s1 FsQQ : A-80 */
-static size_t dsp56k_op_dmac(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_dmac(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint8_t ss = 0;
 	int64_t result = 0;
@@ -2774,15 +2774,15 @@ static size_t dsp56k_op_dmac(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 	/* S L E U N Z V C */
 	/* - * * * * * * - */
 	/* TODO: L, E, U, V */
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;
 	return 1;
 }
 
 /* DO : 0000 0000 110- --RR xxxx xxxx xxxx xxxx : A-82 */
-static size_t dsp56k_op_do(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_do(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - * - - - - - - */
@@ -2790,7 +2790,7 @@ static size_t dsp56k_op_do(dsp56k_core* cpustate, const uint16_t op, const uint1
 }
 
 /* DO : 0000 1110 iiii iiii xxxx xxxx xxxx xxxx : A-82 */
-static size_t dsp56k_op_do_1(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_do_1(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	uint8_t retSize = 0;
 	uint8_t iValue = BITS(op,0x00ff);
@@ -2839,7 +2839,7 @@ static size_t dsp56k_op_do_1(dsp56k_core* cpustate, const uint16_t op, const uin
 }
 
 /* DO : 0000 0100 000D DDDD xxxx xxxx xxxx xxxx : A-82 */
-static size_t dsp56k_op_do_2(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_do_2(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	uint8_t retSize = 0;
 	uint16_t lValue = 0x0000;
@@ -2855,17 +2855,17 @@ static size_t dsp56k_op_do_2(dsp56k_core* cpustate, const uint16_t op, const uin
 	/* HACK */
 	if (lValue >= 0xfff0)
 	{
-		cpustate->device->logerror("Dsp56k : DO_2 operation changed %04x to 0000.\n", lValue);
+		cpustate->device->logerror("Dsp56156 : DO_2 operation changed %04x to 0000.\n", lValue);
 		lValue = 0x0000;
 	}
 
 	/* TODO: Fix for special cased SP S */
 	if (S.addr == &SP)
-		cpustate->device->logerror("DSP56k: do with SP as the source not properly implemented yet.\n");
+		cpustate->device->logerror("DSP56156: do with SP as the source not properly implemented yet.\n");
 
 	/* TODO: Fix for special cased SSSL S */
 	if (S.addr == &SSL)
-		cpustate->device->logerror("DSP56k: do with SP as the source not properly implemented yet.\n");
+		cpustate->device->logerror("DSP56156: do with SP as the source not properly implemented yet.\n");
 
 	/* Don't execute if the loop counter == 0 */
 	if (lValue != 0x00)
@@ -2908,7 +2908,7 @@ static size_t dsp56k_op_do_2(dsp56k_core* cpustate, const uint16_t op, const uin
 }
 
 /* DO FOREVER : 0000 0000 0000 0010 xxxx xxxx xxxx xxxx : A-88 */
-static size_t dsp56k_op_doforever(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_doforever(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	/* First instruction cycle */
 	SP++;
@@ -2932,7 +2932,7 @@ static size_t dsp56k_op_doforever(dsp56k_core* cpustate, const uint16_t op, cons
 }
 
 /* ENDDO : 0000 0000 0000 1001 : A-92 */
-static size_t dsp56k_op_enddo(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_enddo(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2940,7 +2940,7 @@ static size_t dsp56k_op_enddo(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* EXT : 0001 0101 0101 F010 : A-96 */
-static size_t dsp56k_op_ext(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_ext(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - * * * * * * - */
@@ -2948,7 +2948,7 @@ static size_t dsp56k_op_ext(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* ILLEGAL : 0000 0000 0000 1111 : A-98 */
-static size_t dsp56k_op_illegal(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_illegal(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -2956,7 +2956,7 @@ static size_t dsp56k_op_illegal(dsp56k_core* cpustate, const uint16_t op, uint8_
 }
 
 /* IMAC : 0001 0101 1010 FQQQ : A-100 */
-static size_t dsp56k_op_imac(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_imac(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	int64_t opD = 0;
 	int64_t result = 0;
@@ -2999,16 +2999,16 @@ static size_t dsp56k_op_imac(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 	/* - * ? ? * ? ? - */
 	/* TODO: L */
 	/* U,E - Will not be set correctly by this instruction*/
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffff0000U) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	DSP56K_V_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	DSP56156_V_CLEAR();
 
 	cycles += 2;
 	return 1;
 }
 
 /* IMPY : 0001 0101 1000 FQQQ : A-102 */
-static size_t dsp56k_op_impy(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_impy(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - * ? ? * ? ? - */
@@ -3019,7 +3019,7 @@ static size_t dsp56k_op_impy(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* Jcc : 0000 0110 --11 cccc xxxx xxxx xxxx xxxx : A-108 */
-static size_t dsp56k_op_jcc(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_jcc(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3027,7 +3027,7 @@ static size_t dsp56k_op_jcc(dsp56k_core* cpustate, const uint16_t op, const uint
 }
 
 /* Jcc : 0000 0110 RR10 cccc : A-108 */
-static size_t dsp56k_op_jcc_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_jcc_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3035,7 +3035,7 @@ static size_t dsp56k_op_jcc_1(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* JMP : 0000 0001 0011 01-- xxxx xxxx xxxx xxxx : A-110 */
-static size_t dsp56k_op_jmp(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_jmp(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	PC = op2;
 
@@ -3047,7 +3047,7 @@ static size_t dsp56k_op_jmp(dsp56k_core* cpustate, const uint16_t op, const uint
 }
 
 /* JMP : 0000 0001 0010 01RR : A-110 */
-static size_t dsp56k_op_jmp_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_jmp_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	typed_pointer R = { nullptr, DT_BYTE };
 	decode_RR_table(cpustate, BITS(op,0x0003), &R);
@@ -3062,7 +3062,7 @@ static size_t dsp56k_op_jmp_1(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* JScc : 0000 0110 --01 cccc xxxx xxxx xxxx xxxx : A-112 */
-static size_t dsp56k_op_jscc(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_jscc(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	int shouldJump = decode_cccc_table(cpustate, BITS(op,0x000f));
 
@@ -3095,7 +3095,7 @@ static size_t dsp56k_op_jscc(dsp56k_core* cpustate, const uint16_t op, const uin
 }
 
 /* JScc : 0000 0110 RR00 cccc : A-112 */
-static size_t dsp56k_op_jscc_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_jscc_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3103,7 +3103,7 @@ static size_t dsp56k_op_jscc_1(dsp56k_core* cpustate, const uint16_t op, uint8_t
 }
 
 /* JSR : 0000 0001 0011 00-- xxxx xxxx xxxx xxxx : A-114 */
-static size_t dsp56k_op_jsr(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_jsr(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	/* TODO: It says "signed" absolute offset.  Weird. */
 	uint16_t branchOffset = op2;
@@ -3138,7 +3138,7 @@ static size_t dsp56k_op_jsr(dsp56k_core* cpustate, const uint16_t op, const uint
 }
 
 /* JSR : 0000 1010 AAAA AAAA : A-114 */
-static size_t dsp56k_op_jsr_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_jsr_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3146,7 +3146,7 @@ static size_t dsp56k_op_jsr_1(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* JSR : 0000 0001 0010 00RR : A-114 */
-static size_t dsp56k_op_jsr_2(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_jsr_2(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3154,7 +3154,7 @@ static size_t dsp56k_op_jsr_2(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* LEA : 0000 0001 11TT MMRR : A-116 */
-static size_t dsp56k_op_lea(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_lea(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint16_t ea = 0;
 	uint16_t *rX = nullptr;
@@ -3190,7 +3190,7 @@ static size_t dsp56k_op_lea(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* LEA : 0000 0001 10NN MMRR : A-116 */
-static size_t dsp56k_op_lea_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_lea_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3198,7 +3198,7 @@ static size_t dsp56k_op_lea_1(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* MAC(su,uu) : 0001 0101 1110 FsQQ : A-126 */
-static size_t dsp56k_op_macsuuu(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_macsuuu(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint8_t s = 0;
 	int64_t result = 0;
@@ -3236,15 +3236,15 @@ static size_t dsp56k_op_macsuuu(dsp56k_core* cpustate, const uint16_t op, uint8_
 	/* S L E U N Z V C */
 	/* - * * * * * * - */
 	/* TODO: L, E, U, V */
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;
 	return 1;
 }
 
 /* MOVE : 0000 0101 BBBB BBBB ---- HHHW 0001 0001 : A-128 */
-static size_t dsp56k_op_move_2(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_move_2(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - - - - - */
@@ -3252,7 +3252,7 @@ static size_t dsp56k_op_move_2(dsp56k_core* cpustate, const uint16_t op, const u
 }
 
 /* MOVE(C) : 0011 1WDD DDD0 MMRR : A-144 */
-static size_t dsp56k_op_movec(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movec(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint8_t W;
 	typed_pointer R = { nullptr, DT_BYTE };
@@ -3294,7 +3294,7 @@ static size_t dsp56k_op_movec(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* MOVE(C) : 0011 1WDD DDD1 q0RR : A-144 */
-static size_t dsp56k_op_movec_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movec_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint8_t W;
 	uint16_t memOffset;
@@ -3335,7 +3335,7 @@ static size_t dsp56k_op_movec_1(dsp56k_core* cpustate, const uint16_t op, uint8_
 }
 
 /* MOVE(C) : 0011 1WDD DDD1 Z11- : A-144 */
-static size_t dsp56k_op_movec_2(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movec_2(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint8_t W;
 	uint16_t memOffset;
@@ -3380,7 +3380,7 @@ static size_t dsp56k_op_movec_2(dsp56k_core* cpustate, const uint16_t op, uint8_
 }
 
 /* MOVE(C) : 0011 1WDD DDD1 t10- xxxx xxxx xxxx xxxx : A-144 */
-static size_t dsp56k_op_movec_3(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_movec_3(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	uint8_t W;
 	uint8_t t;
@@ -3413,7 +3413,7 @@ static size_t dsp56k_op_movec_3(dsp56k_core* cpustate, const uint16_t op, const
 		if (t)
 		{
 			/* 16-bit long data */
-			cpustate->device->logerror("DSP56k: Movec - I don't think this exists?");
+			cpustate->device->logerror("DSP56156: Movec - I don't think this exists?");
 		}
 		else
 		{
@@ -3438,7 +3438,7 @@ static size_t dsp56k_op_movec_3(dsp56k_core* cpustate, const uint16_t op, const
 }
 
 /* MOVE(C) : 0010 10dd dddD DDDD : A-144 */
-static size_t dsp56k_op_movec_4(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movec_4(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	typed_pointer S = {nullptr, DT_BYTE};
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -3464,7 +3464,7 @@ static size_t dsp56k_op_movec_4(dsp56k_core* cpustate, const uint16_t op, uint8_
 }
 
 /* MOVE(C) : 0000 0101 BBBB BBBB 0011 1WDD DDD0 ---- : A-144 */
-static size_t dsp56k_op_movec_5(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_movec_5(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	int8_t xx;
 	uint8_t W;
@@ -3508,7 +3508,7 @@ static size_t dsp56k_op_movec_5(dsp56k_core* cpustate, const uint16_t op, const
 }
 
 /* MOVE(I) : 0010 00DD BBBB BBBB : A-150 */
-static size_t dsp56k_op_movei(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movei(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_BYTE};
 	typed_pointer immTP = {nullptr, DT_BYTE};
@@ -3529,7 +3529,7 @@ static size_t dsp56k_op_movei(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* MOVE(M) : 0000 001W RR0M MHHH : A-152 */
-static size_t dsp56k_op_movem(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movem(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint8_t W;
 	typed_pointer R = { nullptr, DT_BYTE };
@@ -3565,7 +3565,7 @@ static size_t dsp56k_op_movem(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* MOVE(M) : 0000 001W RR11 mmRR : A-152 */
-static size_t dsp56k_op_movem_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movem_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - - - - - */
@@ -3573,7 +3573,7 @@ static size_t dsp56k_op_movem_1(dsp56k_core* cpustate, const uint16_t op, uint8_
 }
 
 /* MOVE(M) : 0000 0101 BBBB BBBB 0000 001W --0- -HHH : A-152 */
-static size_t dsp56k_op_movem_2(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
+static size_t dsp56156_op_movem_2(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - - - - - */
@@ -3581,7 +3581,7 @@ static size_t dsp56k_op_movem_2(dsp56k_core* cpustate, const uint16_t op, const
 }
 
 /* MOVE(P) : 0001 100W HH1p pppp : A-156 */
-static size_t dsp56k_op_movep(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movep(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint16_t W;
 	uint16_t pp;
@@ -3619,7 +3619,7 @@ static size_t dsp56k_op_movep(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* MOVE(P) : 0000 110W RRmp pppp : A-156 */
-static size_t dsp56k_op_movep_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_movep_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* X:<Rx> and X:<pp> */
 	uint16_t W;
@@ -3647,7 +3647,7 @@ static size_t dsp56k_op_movep_1(dsp56k_core* cpustate, const uint16_t op, uint8_
 	else
 	{
 		/* TODO */
-		fatalerror("dsp56k : move(p) NOTHING HERE (yet)\n") ;
+		fatalerror("dsp56156 : move(p) NOTHING HERE (yet)\n") ;
 	}
 
 	/* Postincrement */
@@ -3661,7 +3661,7 @@ static size_t dsp56k_op_movep_1(dsp56k_core* cpustate, const uint16_t op, uint8_
 }
 
 /* MOVE(S) : 0001 100W HH0a aaaa : A-158 */
-static size_t dsp56k_op_moves(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_moves(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - - - - - */
@@ -3669,7 +3669,7 @@ static size_t dsp56k_op_moves(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* MPY(su,uu) : 0001 0101 1100 FsQQ : A-164 */
-static size_t dsp56k_op_mpysuuu(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_mpysuuu(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	uint8_t s = 0;
 	int64_t result = 0;
@@ -3707,15 +3707,15 @@ static size_t dsp56k_op_mpysuuu(dsp56k_core* cpustate, const uint16_t op, uint8_
 	/* S L E U N Z V C */
 	/* - * * * * * * - */
 	/* TODO: L, E, U, V */
-	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
+	if ( *((uint64_t*)D) & 0x0000008000000000U)       DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint64_t*)D) & 0x000000ffffffffffU) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
 
 	cycles += 2;
 	return 1;
 }
 
 /* NEGC : 0001 0101 0110 F000 : A-168 */
-static size_t dsp56k_op_negc(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_negc(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - * * * * * * * */
@@ -3723,7 +3723,7 @@ static size_t dsp56k_op_negc(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* NOP : 0000 0000 0000 0000 : A-170 */
-static size_t dsp56k_op_nop(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_nop(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3731,7 +3731,7 @@ static size_t dsp56k_op_nop(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* NORM : 0001 0101 0010 F0RR : A-172 */
-static size_t dsp56k_op_norm(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_norm(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - * * * * * ? - */
@@ -3741,7 +3741,7 @@ static size_t dsp56k_op_norm(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* ORI : 0001 1EE1 iiii iiii : A-178 */
-static size_t dsp56k_op_ori(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_ori(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - ? ? ? ? ? ? ? */
@@ -3751,7 +3751,7 @@ static size_t dsp56k_op_ori(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* REP : 0000 0000 111- --RR : A-180 */
-static size_t dsp56k_op_rep(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_rep(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - * - - - - - - */
@@ -3759,7 +3759,7 @@ static size_t dsp56k_op_rep(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* REP : 0000 1111 iiii iiii : A-180 */
-static size_t dsp56k_op_rep_1(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_rep_1(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* TODO: This is non-interruptable, probably have to turn off interrupts here */
 	uint16_t iVal = op & 0x00ff;
@@ -3787,7 +3787,7 @@ static size_t dsp56k_op_rep_1(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* REP : 0000 0100 001D DDDD : A-180 */
-static size_t dsp56k_op_rep_2(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_rep_2(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* TODO: This is non-interruptable, probably have to turn off interrupts here */
 	uint16_t repValue;
@@ -3796,7 +3796,7 @@ static size_t dsp56k_op_rep_2(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 
 	/* TODO: handle special A&B source cases */
 	if (D.addr == &A || D.addr == &B)
-		cpustate->device->logerror("DSP56k ERROR : Rep with A or B instruction not implemented yet!\n");
+		cpustate->device->logerror("DSP56156 ERROR : Rep with A or B instruction not implemented yet!\n");
 
 	repValue = *((uint16_t*)D.addr);
 
@@ -3822,7 +3822,7 @@ static size_t dsp56k_op_rep_2(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* REPcc : 0000 0001 0101 cccc : A-184 */
-static size_t dsp56k_op_repcc(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_repcc(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3830,7 +3830,7 @@ static size_t dsp56k_op_repcc(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* RESET : 0000 0000 0000 1000 : A-186 */
-static size_t dsp56k_op_reset(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_reset(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3838,12 +3838,12 @@ static size_t dsp56k_op_reset(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* RTI : 0000 0000 0000 0111 : A-194 */
-static size_t dsp56k_op_rti(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_rti(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* WARNING : THERE SHOULD BE A MORE GENERAL HANDLING OF STACK ERRORS. */
 	if (SP == 0)
 	{
-		dsp56k_add_pending_interrupt(cpustate, "Stack Error");
+		dsp56156_add_pending_interrupt(cpustate, "Stack Error");
 		return 0;
 	}
 
@@ -3860,7 +3860,7 @@ static size_t dsp56k_op_rti(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* RTS : 0000 0000 0000 0110 : A-196 */
-static size_t dsp56k_op_rts(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_rts(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* Pop */
 	PC = SSH;
@@ -3876,7 +3876,7 @@ static size_t dsp56k_op_rts(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* STOP : 0000 0000 0000 1010 : A-200 */
-static size_t dsp56k_op_stop(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_stop(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3884,7 +3884,7 @@ static size_t dsp56k_op_stop(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* SWAP : 0001 0101 0111 F001 : A-206 */
-static size_t dsp56k_op_swap(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_swap(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3892,7 +3892,7 @@ static size_t dsp56k_op_swap(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* SWI : 0000 0000 0000 0101 : A-208 */
-static size_t dsp56k_op_swi(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_swi(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3900,7 +3900,7 @@ static size_t dsp56k_op_swi(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* Tcc : 0001 00cc ccTT Fh0h : A-210 */
-static size_t dsp56k_op_tcc(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_tcc(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	int shouldTransfer = decode_cccc_table(cpustate, BITS(op,0x03c0));
 
@@ -3926,7 +3926,7 @@ static size_t dsp56k_op_tcc(dsp56k_core* cpustate, const uint16_t op, uint8_t* c
 }
 
 /* TFR(2) : 0001 0101 0000 F00J : A-214 */
-static size_t dsp56k_op_tfr2(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_tfr2(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	typed_pointer S = {nullptr, DT_BYTE};
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -3943,7 +3943,7 @@ static size_t dsp56k_op_tfr2(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* TFR(3) : 0010 01mW RRDD FHHH : A-216 */
-static size_t dsp56k_op_tfr3(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_tfr3(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* * * - - - - - - */
@@ -3951,7 +3951,7 @@ static size_t dsp56k_op_tfr3(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* TST(2) : 0001 0101 0001 -1DD : A-220 */
-static size_t dsp56k_op_tst2(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_tst2(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	typed_pointer D = {nullptr, DT_BYTE};
 	decode_DD_table(cpustate, BITS(op,0x0003), &D);
@@ -3959,20 +3959,20 @@ static size_t dsp56k_op_tst2(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 	/* S L E U N Z V C */
 	/* - * * * * * 0 0 */
 	/* (L,E,U should be set to 0) */
-	DSP56K_L_CLEAR();
-	DSP56K_E_CLEAR();
+	DSP56156_L_CLEAR();
+	DSP56156_E_CLEAR();
 	/* U_CLEAR(); */ /* TODO: Conflicting opinions?  "Set if unnormalized."  Documentation is weird (A&B?) */
-	if ((*((uint16_t*)D.addr)) &  0x8000) DSP56K_N_SET(); else DSP56K_N_CLEAR();
-	if ((*((uint16_t*)D.addr)) == 0x0000) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
-	/* DSP56K_V_CLEAR(); */ /* Unaffected */
-	DSP56K_C_CLEAR();
+	if ((*((uint16_t*)D.addr)) &  0x8000) DSP56156_N_SET(); else DSP56156_N_CLEAR();
+	if ((*((uint16_t*)D.addr)) == 0x0000) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
+	/* DSP56156_V_CLEAR(); */ /* Unaffected */
+	DSP56156_C_CLEAR();
 
 	cycles += 2;
 	return 1;
 }
 
 /* WAIT : 0000 0000 0000 1011 : A-222 */
-static size_t dsp56k_op_wait(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_wait(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - - - - - - - - */
@@ -3980,7 +3980,7 @@ static size_t dsp56k_op_wait(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 }
 
 /* ZERO : 0001 0101 0101 F000 : A-224 */
-static size_t dsp56k_op_zero(dsp56k_core* cpustate, const uint16_t op, uint8_t* cycles)
+static size_t dsp56156_op_zero(dsp56156_core* cpustate, const uint16_t op, uint8_t* cycles)
 {
 	/* S L E U N Z V C */
 	/* - * * * * * * - */
@@ -3992,7 +3992,7 @@ static size_t dsp56k_op_zero(dsp56k_core* cpustate, const uint16_t op, uint8_t*
 /***************************************************************************
     Table decoding
 ***************************************************************************/
-static uint16_t decode_BBB_bitmask(dsp56k_core* cpustate, uint16_t BBB, uint16_t *iVal)
+static uint16_t decode_BBB_bitmask(dsp56156_core* cpustate, uint16_t BBB, uint16_t *iVal)
 {
 	uint16_t retVal = 0x0000;
 
@@ -4006,7 +4006,7 @@ static uint16_t decode_BBB_bitmask(dsp56k_core* cpustate, uint16_t BBB, uint16_t
 	return retVal;
 }
 
-static int decode_cccc_table(dsp56k_core* cpustate, uint16_t cccc)
+static int decode_cccc_table(dsp56156_core* cpustate, uint16_t cccc)
 {
 	int retVal = 0;
 
@@ -4035,7 +4035,7 @@ static int decode_cccc_table(dsp56k_core* cpustate, uint16_t cccc)
 	return retVal;
 }
 
-static void decode_DDDDD_table(dsp56k_core* cpustate, uint16_t DDDDD, typed_pointer* ret)
+static void decode_DDDDD_table(dsp56156_core* cpustate, uint16_t DDDDD, typed_pointer* ret)
 {
 	switch(DDDDD)
 	{
@@ -4075,7 +4075,7 @@ static void decode_DDDDD_table(dsp56k_core* cpustate, uint16_t DDDDD, typed_poin
 	}
 }
 
-static void decode_DD_table(dsp56k_core* cpustate, uint16_t DD, typed_pointer* ret)
+static void decode_DD_table(dsp56156_core* cpustate, uint16_t DD, typed_pointer* ret)
 {
 	switch(DD)
 	{
@@ -4086,7 +4086,7 @@ static void decode_DD_table(dsp56k_core* cpustate, uint16_t DD, typed_pointer* r
 	}
 }
 
-static void decode_DDF_table(dsp56k_core* cpustate, uint16_t DD, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
+static void decode_DDF_table(dsp56156_core* cpustate, uint16_t DD, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
 {
 	uint16_t switchVal = (DD << 1) | F;
 
@@ -4103,7 +4103,7 @@ static void decode_DDF_table(dsp56k_core* cpustate, uint16_t DD, uint16_t F, typ
 	}
 }
 
-static void decode_F_table(dsp56k_core* cpustate, uint16_t F, typed_pointer* ret)
+static void decode_F_table(dsp56156_core* cpustate, uint16_t F, typed_pointer* ret)
 {
 	switch(F)
 	{
@@ -4112,7 +4112,7 @@ static void decode_F_table(dsp56k_core* cpustate, uint16_t F, typed_pointer* ret
 	}
 }
 
-static void decode_h0hF_table(dsp56k_core* cpustate, uint16_t h0h, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
+static void decode_h0hF_table(dsp56156_core* cpustate, uint16_t h0h, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
 {
 	uint16_t switchVal = (h0h << 1) | F ;
 
@@ -4129,7 +4129,7 @@ static void decode_h0hF_table(dsp56k_core* cpustate, uint16_t h0h, uint16_t F, t
 	}
 }
 
-static void decode_HH_table(dsp56k_core* cpustate, uint16_t HH, typed_pointer* ret)
+static void decode_HH_table(dsp56156_core* cpustate, uint16_t HH, typed_pointer* ret)
 {
 	switch(HH)
 	{
@@ -4140,7 +4140,7 @@ static void decode_HH_table(dsp56k_core* cpustate, uint16_t HH, typed_pointer* r
 	}
 }
 
-static void decode_HHH_table(dsp56k_core* cpustate, uint16_t HHH, typed_pointer* ret)
+static void decode_HHH_table(dsp56156_core* cpustate, uint16_t HHH, typed_pointer* ret)
 {
 	switch(HHH)
 	{
@@ -4155,7 +4155,7 @@ static void decode_HHH_table(dsp56k_core* cpustate, uint16_t HHH, typed_pointer*
 	}
 }
 
-static void decode_IIII_table(dsp56k_core* cpustate, uint16_t IIII, typed_pointer* src_ret, typed_pointer* dst_ret, void *working)
+static void decode_IIII_table(dsp56156_core* cpustate, uint16_t IIII, typed_pointer* src_ret, typed_pointer* dst_ret, void *working)
 {
 	void *opposite = nullptr ;
 
@@ -4181,7 +4181,7 @@ static void decode_IIII_table(dsp56k_core* cpustate, uint16_t IIII, typed_pointe
 	}
 }
 
-static void decode_JJJF_table(dsp56k_core* cpustate, uint16_t JJJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
+static void decode_JJJF_table(dsp56156_core* cpustate, uint16_t JJJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
 {
 	uint16_t switchVal = (JJJ << 1) | F ;
 
@@ -4204,7 +4204,7 @@ static void decode_JJJF_table(dsp56k_core* cpustate, uint16_t JJJ, uint16_t F, t
 	}
 }
 
-static void decode_JJF_table(dsp56k_core* cpustate, uint16_t JJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
+static void decode_JJF_table(dsp56156_core* cpustate, uint16_t JJ, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
 {
 	uint16_t switchVal = (JJ << 1) | F ;
 
@@ -4221,7 +4221,7 @@ static void decode_JJF_table(dsp56k_core* cpustate, uint16_t JJ, uint16_t F, typ
 	}
 }
 
-static void decode_JF_table(dsp56k_core* cpustate, uint16_t J, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
+static void decode_JF_table(dsp56156_core* cpustate, uint16_t J, uint16_t F, typed_pointer* src_ret, typed_pointer* dst_ret)
 {
 	uint16_t switchVal = (J << 1) | F ;
 
@@ -4234,7 +4234,7 @@ static void decode_JF_table(dsp56k_core* cpustate, uint16_t J, uint16_t F, typed
 	}
 }
 
-static void decode_KKK_table(dsp56k_core* cpustate, uint16_t KKK, typed_pointer* dst_ret1, typed_pointer* dst_ret2, void* working)
+static void decode_KKK_table(dsp56156_core* cpustate, uint16_t KKK, typed_pointer* dst_ret1, typed_pointer* dst_ret2, void* working)
 {
 	void *opposite = nullptr ;
 
@@ -4254,7 +4254,7 @@ static void decode_KKK_table(dsp56k_core* cpustate, uint16_t KKK, typed_pointer*
 	}
 }
 
-static void decode_QQF_table(dsp56k_core* cpustate, uint16_t QQ, uint16_t F, void **S1, void **S2, void **D)
+static void decode_QQF_table(dsp56156_core* cpustate, uint16_t QQ, uint16_t F, void **S1, void **S2, void **D)
 {
 	uint16_t switchVal = (QQ << 1) | F ;
 
@@ -4271,7 +4271,7 @@ static void decode_QQF_table(dsp56k_core* cpustate, uint16_t QQ, uint16_t F, voi
 	}
 }
 
-static void decode_QQF_special_table(dsp56k_core* cpustate, uint16_t QQ, uint16_t F, void **S1, void **S2, void **D)
+static void decode_QQF_special_table(dsp56156_core* cpustate, uint16_t QQ, uint16_t F, void **S1, void **S2, void **D)
 {
 	uint16_t switchVal = (QQ << 1) | F ;
 
@@ -4288,7 +4288,7 @@ static void decode_QQF_special_table(dsp56k_core* cpustate, uint16_t QQ, uint16_
 	}
 }
 
-static void decode_QQQF_table(dsp56k_core* cpustate, uint16_t QQQ, uint16_t F, void **S1, void **S2, void **D)
+static void decode_QQQF_table(dsp56156_core* cpustate, uint16_t QQQ, uint16_t F, void **S1, void **S2, void **D)
 {
 	uint16_t switchVal = (QQQ << 1) | F;
 
@@ -4313,7 +4313,7 @@ static void decode_QQQF_table(dsp56k_core* cpustate, uint16_t QQQ, uint16_t F, v
 	}
 }
 
-static void decode_RR_table(dsp56k_core* cpustate, uint16_t RR, typed_pointer* ret)
+static void decode_RR_table(dsp56156_core* cpustate, uint16_t RR, typed_pointer* ret)
 {
 	switch(RR)
 	{
@@ -4324,7 +4324,7 @@ static void decode_RR_table(dsp56k_core* cpustate, uint16_t RR, typed_pointer* r
 	}
 }
 
-static void decode_TT_table(dsp56k_core* cpustate, uint16_t TT, typed_pointer* ret)
+static void decode_TT_table(dsp56156_core* cpustate, uint16_t TT, typed_pointer* ret)
 {
 	switch(TT)
 	{
@@ -4336,7 +4336,7 @@ static void decode_TT_table(dsp56k_core* cpustate, uint16_t TT, typed_pointer* r
 }
 
 
-static void decode_uuuuF_table(dsp56k_core* cpustate, uint16_t uuuu, uint16_t F, uint8_t add_sub_other, typed_pointer* src_ret, typed_pointer* dst_ret)
+static void decode_uuuuF_table(dsp56156_core* cpustate, uint16_t uuuu, uint16_t F, uint8_t add_sub_other, typed_pointer* src_ret, typed_pointer* dst_ret)
 {
 	uint16_t switchVal = (uuuu << 1) | F;
 
@@ -4410,7 +4410,7 @@ static void decode_uuuuF_table(dsp56k_core* cpustate, uint16_t uuuu, uint16_t F,
 	}
 }
 
-static void decode_Z_table(dsp56k_core* cpustate, uint16_t Z, typed_pointer* ret)
+static void decode_Z_table(dsp56156_core* cpustate, uint16_t Z, typed_pointer* ret)
 {
 	switch(Z)
 	{
@@ -4420,7 +4420,7 @@ static void decode_Z_table(dsp56k_core* cpustate, uint16_t Z, typed_pointer* ret
 	}
 }
 
-static void execute_m_table(dsp56k_core* cpustate, int x, uint16_t m)
+static void execute_m_table(dsp56156_core* cpustate, int x, uint16_t m)
 {
 	uint16_t *rX = nullptr ;
 	uint16_t *nX = nullptr ;
@@ -4440,7 +4440,7 @@ static void execute_m_table(dsp56k_core* cpustate, int x, uint16_t m)
 	}
 }
 
-static void execute_mm_table(dsp56k_core* cpustate, uint16_t rnum, uint16_t mm)
+static void execute_mm_table(dsp56156_core* cpustate, uint16_t rnum, uint16_t mm)
 {
 	uint16_t *rX = nullptr;
 	uint16_t *nX = nullptr;
@@ -4450,7 +4450,7 @@ static void execute_mm_table(dsp56k_core* cpustate, uint16_t rnum, uint16_t mm)
 		case 0x0: rX = &R0;  nX = &N0;  break;
 		case 0x1: rX = &R1;  nX = &N1;  break;
 		case 0x2: rX = &R2;  nX = &N2;  break;
-		case 0x3: fatalerror("Dsp56k: Error. execute_mm_table specified R3 as its first source!\n");  break;
+		case 0x3: fatalerror("Dsp56156: Error. execute_mm_table specified R3 as its first source!\n");  break;
 	}
 
 	switch(mm)
@@ -4462,7 +4462,7 @@ static void execute_mm_table(dsp56k_core* cpustate, uint16_t rnum, uint16_t mm)
 	}
 }
 
-static void execute_MM_table(dsp56k_core* cpustate, uint16_t rnum, uint16_t MM)
+static void execute_MM_table(dsp56156_core* cpustate, uint16_t rnum, uint16_t MM)
 {
 	uint16_t *rX = nullptr ;
 	uint16_t *nX = nullptr ;
@@ -4485,7 +4485,7 @@ static void execute_MM_table(dsp56k_core* cpustate, uint16_t rnum, uint16_t MM)
 }
 
 /* Returns R value */
-static uint16_t execute_q_table(dsp56k_core* cpustate, int RR, uint16_t q)
+static uint16_t execute_q_table(dsp56156_core* cpustate, int RR, uint16_t q)
 {
 	uint16_t *rX = nullptr;
 	uint16_t *nX = nullptr;
@@ -4505,11 +4505,11 @@ static uint16_t execute_q_table(dsp56k_core* cpustate, int RR, uint16_t q)
 	}
 
 	/* Should not get here */
-	fatalerror("dsp56k: execute_q_table did something impossible!\n");
+	fatalerror("dsp56156: execute_q_table did something impossible!\n");
 	return 0;
 }
 
-static void execute_z_table(dsp56k_core* cpustate, int RR, uint16_t z)
+static void execute_z_table(dsp56156_core* cpustate, int RR, uint16_t z)
 {
 	uint16_t *rX = nullptr;
 	uint16_t *nX = nullptr;
@@ -4529,7 +4529,7 @@ static void execute_z_table(dsp56k_core* cpustate, int RR, uint16_t z)
 	}
 }
 
-static uint16_t assemble_address_from_Pppppp_table(dsp56k_core* cpustate, uint16_t P, uint16_t ppppp)
+static uint16_t assemble_address_from_Pppppp_table(dsp56156_core* cpustate, uint16_t P, uint16_t ppppp)
 {
 	uint16_t destAddr = 0x00 ;
 
@@ -4542,14 +4542,14 @@ static uint16_t assemble_address_from_Pppppp_table(dsp56k_core* cpustate, uint16
 	return destAddr ;
 }
 
-static uint16_t assemble_address_from_IO_short_address(dsp56k_core* cpustate, uint16_t pp)
+static uint16_t assemble_address_from_IO_short_address(dsp56156_core* cpustate, uint16_t pp)
 {
 	uint16_t fullAddy = 0xffe0;
 	fullAddy |= pp;
 	return fullAddy;
 }
 
-static uint16_t assemble_address_from_6bit_signed_relative_short_address(dsp56k_core* cpustate, uint16_t srs)
+static uint16_t assemble_address_from_6bit_signed_relative_short_address(dsp56156_core* cpustate, uint16_t srs)
 {
 	uint16_t fullAddy = srs ;
 	if (fullAddy & 0x0020)
@@ -4558,7 +4558,7 @@ static uint16_t assemble_address_from_6bit_signed_relative_short_address(dsp56k_
 	return fullAddy ;
 }
 
-static void dsp56k_process_loop(dsp56k_core* cpustate)
+static void dsp56156_process_loop(dsp56156_core* cpustate)
 {
 	/* TODO: This might not work for dos nested in doForevers */
 	if (LF_bit(cpustate) && FV_bit(cpustate))
@@ -4595,7 +4595,7 @@ static void dsp56k_process_loop(dsp56k_core* cpustate)
 	}
 }
 
-static void dsp56k_process_rep(dsp56k_core* cpustate, size_t repSize)
+static void dsp56156_process_rep(dsp56156_core* cpustate, size_t repSize)
 {
 	if (cpustate->repFlag)
 	{
@@ -4622,7 +4622,7 @@ static void dsp56k_process_rep(dsp56k_core* cpustate, size_t repSize)
     Parallel Memory Ops
 ***************************************************************************/
 /* Register to Register Data Move : 0100 IIII .... .... : A-132 */
-static void execute_register_to_register_data_move(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value)
+static void execute_register_to_register_data_move(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value)
 {
 	typed_pointer S = {nullptr, DT_BYTE};
 	typed_pointer D = {nullptr, DT_BYTE};
@@ -4644,13 +4644,13 @@ static void execute_register_to_register_data_move(dsp56k_core* cpustate, const
 }
 
 /* Address Register Update : 0011 0zRR .... .... : A-135 */
-static void execute_address_register_update(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value)
+static void execute_address_register_update(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value)
 {
 	execute_z_table(cpustate, BITS(op,0x0300), BITS(op,0x0400));
 }
 
 /* X Memory Data Move : 1mRR HHHW .... .... : A-137 */
-static void execute_x_memory_data_move(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value)
+static void execute_x_memory_data_move(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register, uint64_t* prev_accum_value)
 {
 	uint16_t W;
 	typed_pointer R = {nullptr, DT_BYTE};
@@ -4694,7 +4694,7 @@ static void execute_x_memory_data_move(dsp56k_core* cpustate, const uint16_t op,
 
 /* X Memory Data Move : 0101 HHHW .... .... : A-137 */
 /* NOTE: previous accumulator value is not needed since ^F1 is always the opposite accumulator */
-static void execute_x_memory_data_move2(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register)
+static void execute_x_memory_data_move2(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register)
 {
 	uint16_t W;
 	uint16_t* mem_offset = nullptr;
@@ -4723,7 +4723,7 @@ static void execute_x_memory_data_move2(dsp56k_core* cpustate, const uint16_t op
 }
 
 /* X Memory Data Move With Short Displacement : 0000 0101 BBBB BBBB ---- HHHW .... .... : A-139 */
-static void execute_x_memory_data_move_with_short_displacement(dsp56k_core* cpustate, const uint16_t op, const uint16_t op2)
+static void execute_x_memory_data_move_with_short_displacement(dsp56156_core* cpustate, const uint16_t op, const uint16_t op2)
 {
 	int8_t xx;
 	uint8_t W;
@@ -4753,7 +4753,7 @@ static void execute_x_memory_data_move_with_short_displacement(dsp56k_core* cpus
 }
 
 /* Dual X Memory Data Read : 011m mKKK .rr. .... : A-142*/
-static void execute_dual_x_memory_data_read(dsp56k_core* cpustate, const uint16_t op, typed_pointer* d_register)
+static void execute_dual_x_memory_data_read(dsp56156_core* cpustate, const uint16_t op, typed_pointer* d_register)
 {
 	typed_pointer tempV;
 	uint16_t srcVal1 = 0x0000;
@@ -4767,12 +4767,12 @@ static void execute_dual_x_memory_data_read(dsp56k_core* cpustate, const uint16_
 
 	/* Can't do an R3 for S1 */
 	if (R.addr == &R3)
-		fatalerror("Dsp56k: Error. Dual x memory data read specified R3 as its first source!\n");
+		fatalerror("Dsp56156: Error. Dual x memory data read specified R3 as its first source!\n");
 
 	/* The note on A-142 is very interesting.
 	   You can effectively access external memory in the last 64 bytes of X data memory! */
 	if (*((uint16_t*)D2.addr) >= 0xffc0)
-		fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read.\n");
+		fatalerror("Dsp56156: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read.\n");
 
 	/* First memmove */
 	srcVal1 = cpustate->data->read_word(*((uint16_t*)R.addr));
@@ -4793,7 +4793,7 @@ static void execute_dual_x_memory_data_read(dsp56k_core* cpustate, const uint16_
 /***************************************************************************
     Helper Functions
 ***************************************************************************/
-static uint16_t Dsp56kOpMask(uint16_t cur, uint16_t mask)
+static uint16_t Dsp56156OpMask(uint16_t cur, uint16_t mask)
 {
 	int i ;
 
@@ -4873,7 +4873,7 @@ static void SetDestinationValue(typed_pointer source, typed_pointer dest)
 }
 
 /* TODO: Wait-state timings! */
-static void SetDataMemoryValue(dsp56k_core* cpustate, typed_pointer source, uint32_t destinationAddr)
+static void SetDataMemoryValue(dsp56156_core* cpustate, typed_pointer source, uint32_t destinationAddr)
 {
 	switch(source.data_type)
 	{
@@ -4888,7 +4888,7 @@ static void SetDataMemoryValue(dsp56k_core* cpustate, typed_pointer source, uint
 }
 
 /* TODO: Wait-state timings! */
-static void SetProgramMemoryValue(dsp56k_core* cpustate, typed_pointer source, uint32_t destinationAddr)
+static void SetProgramMemoryValue(dsp56156_core* cpustate, typed_pointer source, uint32_t destinationAddr)
 {
 	switch(source.data_type)
 	{
diff --git a/src/devices/cpu/dsp56k/dsp56pcu.cpp b/src/devices/cpu/dsp56156/dsp56pcu.cpp
similarity index 58%
rename from src/devices/cpu/dsp56k/dsp56pcu.cpp
rename to src/devices/cpu/dsp56156/dsp56pcu.cpp
index 529c623a506..94ca3b1caae 100644
--- a/src/devices/cpu/dsp56k/dsp56pcu.cpp
+++ b/src/devices/cpu/dsp56156/dsp56pcu.cpp
@@ -4,7 +4,7 @@
 #include "dsp56pcu.h"
 #include "dsp56mem.h"
 
-namespace DSP56K
+namespace DSP_56156
 {
 /* ************************************************************************* */
 /*                            Status Register                                */
@@ -15,34 +15,34 @@ namespace DSP56K
 /* |-------------------------------------| |-------------------------------| */
 /*                                                                           */
 /* ************************************************************************* */
-uint8_t LF_bit(const dsp56k_core* cpustate) { return (SR & 0x8000) >> 15; }
-uint8_t FV_bit(const dsp56k_core* cpustate) { return (SR & 0x4000) >> 14; }
-// uint8_t S_bits(const dsp56k_core* cpustate) { return (SR & 0x0c00) >> 10; }
-uint8_t I_bits(const dsp56k_core* cpustate) { return (SR & 0x0300) >> 8;  }
-uint8_t S_bit (const dsp56k_core* cpustate) { return (SR & 0x0080) >> 7;  }
-uint8_t L_bit (const dsp56k_core* cpustate) { return (SR & 0x0040) >> 6;  }
-uint8_t E_bit (const dsp56k_core* cpustate) { return (SR & 0x0020) >> 5;  }
-uint8_t U_bit (const dsp56k_core* cpustate) { return (SR & 0x0010) >> 4;  }
-uint8_t N_bit (const dsp56k_core* cpustate) { return (SR & 0x0008) >> 3;  }
-uint8_t Z_bit (const dsp56k_core* cpustate) { return (SR & 0x0004) >> 2;  }
-uint8_t V_bit (const dsp56k_core* cpustate) { return (SR & 0x0002) >> 1;  }
-uint8_t C_bit (const dsp56k_core* cpustate) { return (SR & 0x0001) >> 0;  }
+uint8_t LF_bit(const dsp56156_core* cpustate) { return (SR & 0x8000) >> 15; }
+uint8_t FV_bit(const dsp56156_core* cpustate) { return (SR & 0x4000) >> 14; }
+// uint8_t S_bits(const dsp56156_core* cpustate) { return (SR & 0x0c00) >> 10; }
+uint8_t I_bits(const dsp56156_core* cpustate) { return (SR & 0x0300) >> 8;  }
+uint8_t S_bit (const dsp56156_core* cpustate) { return (SR & 0x0080) >> 7;  }
+uint8_t L_bit (const dsp56156_core* cpustate) { return (SR & 0x0040) >> 6;  }
+uint8_t E_bit (const dsp56156_core* cpustate) { return (SR & 0x0020) >> 5;  }
+uint8_t U_bit (const dsp56156_core* cpustate) { return (SR & 0x0010) >> 4;  }
+uint8_t N_bit (const dsp56156_core* cpustate) { return (SR & 0x0008) >> 3;  }
+uint8_t Z_bit (const dsp56156_core* cpustate) { return (SR & 0x0004) >> 2;  }
+uint8_t V_bit (const dsp56156_core* cpustate) { return (SR & 0x0002) >> 1;  }
+uint8_t C_bit (const dsp56156_core* cpustate) { return (SR & 0x0001) >> 0;  }
 
 /* MR setters */
-void LF_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); }
-void FV_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); }
-void S_bits_set(dsp56k_core* cpustate, uint8_t value) { value = value & 0x03;  SR &= ~(0x0c00);  SR |= (value << 10); }
-void I_bits_set(dsp56k_core* cpustate, uint8_t value) { value = value & 0x03;  SR &= ~(0x0300);  SR |= (value <<  8); }
+void LF_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); }
+void FV_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); }
+void S_bits_set(dsp56156_core* cpustate, uint8_t value) { value = value & 0x03;  SR &= ~(0x0c00);  SR |= (value << 10); }
+void I_bits_set(dsp56156_core* cpustate, uint8_t value) { value = value & 0x03;  SR &= ~(0x0300);  SR |= (value <<  8); }
 
 /* CCR setters */
-void S_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); }
-void L_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); }
-void E_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); }
-void U_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); }
-void N_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); }
-void Z_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); }
-void V_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); }
-void C_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); }
+void S_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); }
+void L_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); }
+void E_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); }
+void U_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); }
+void N_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); }
+void Z_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); }
+void V_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); }
+void C_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); }
 
 
 
@@ -55,23 +55,23 @@ void C_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0001)
 /*  |---------------------------------------------------------------------|  */
 /*                                                                           */
 /* ************************************************************************* */
-// uint8_t CD_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0080) != 0); }
-// uint8_t SD_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0040) != 0); }
-// uint8_t  R_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0020) != 0); }
-// uint8_t SA_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0010) != 0); }
-// uint8_t MC_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); }
-uint8_t MB_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); }
-uint8_t MA_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); }
+// uint8_t CD_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0080) != 0); }
+// uint8_t SD_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0040) != 0); }
+// uint8_t  R_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0020) != 0); }
+// uint8_t SA_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0010) != 0); }
+// uint8_t MC_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0004) != 0); }
+uint8_t MB_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0002) != 0); }
+uint8_t MA_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0001) != 0); }
 
-void CD_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); }
-void SD_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); }
-void  R_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); }
-void SA_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); }
-void MC_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); }
-void MB_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); }
-void MA_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); }
+void CD_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); }
+void SD_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); }
+void  R_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); }
+void SA_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); }
+void MC_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); }
+void MB_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); }
+void MA_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); }
 
-uint8_t dsp56k_operating_mode(const dsp56k_core* cpustate)
+uint8_t dsp56156_operating_mode(const dsp56156_core* cpustate)
 {
 	return ((MB_bit(cpustate) << 1) | MA_bit(cpustate));
 }
@@ -87,23 +87,23 @@ uint8_t dsp56k_operating_mode(const dsp56k_core* cpustate)
 /*  |---------------------------------------------------------------------|  */
 /*                                                                           */
 /* ************************************************************************* */
-uint8_t UF_bit(const dsp56k_core* cpustate) { return ((SP & 0x0020) != 0); }
-uint8_t SE_bit(const dsp56k_core* cpustate) { return ((SP & 0x0010) != 0); }
+uint8_t UF_bit(const dsp56156_core* cpustate) { return ((SP & 0x0020) != 0); }
+uint8_t SE_bit(const dsp56156_core* cpustate) { return ((SP & 0x0010) != 0); }
 
-//void UF_bit_set(dsp56k_core* cpustate, uint8_t value) {};
-//void SE_bit_set(dsp56k_core* cpustate, uint8_t value) {};
+//void UF_bit_set(dsp56156_core* cpustate, uint8_t value) {};
+//void SE_bit_set(dsp56156_core* cpustate, uint8_t value) {};
 
 
 
 /***************************************************************************
     INITIALIZATION AND RESET
 ***************************************************************************/
-void pcu_init(dsp56k_core* cpustate, device_t *device)
+void pcu_init(dsp56156_core* cpustate, device_t *device)
 {
 	/* Init the irq table */
-	dsp56k_irq_table_init();
+	dsp56156_irq_table_init();
 
-	/* save states - dsp56k_pcu members */
+	/* save states - dsp56156_pcu members */
 	device->save_item(NAME(cpustate->PCU.pc));
 	device->save_item(NAME(cpustate->PCU.la));
 	device->save_item(NAME(cpustate->PCU.lc));
@@ -115,7 +115,7 @@ void pcu_init(dsp56k_core* cpustate, device_t *device)
 	device->save_item(NAME(cpustate->PCU.reset_vector));
 }
 
-void pcu_reset(dsp56k_core* cpustate)
+void pcu_reset(dsp56156_core* cpustate)
 {
 	int i;
 
@@ -125,10 +125,10 @@ void pcu_reset(dsp56k_core* cpustate)
 	MC_bit_set(cpustate, cpustate->modC_state);
 
 	/* Reset based on the operating mode. */
-	switch(dsp56k_operating_mode(cpustate))
+	switch(dsp56156_operating_mode(cpustate))
 	{
 		case 0x00:
-			cpustate->device->logerror("Dsp56k in Special Bootstrap Mode 1\n");
+			cpustate->device->logerror("Dsp56156 in Special Bootstrap Mode 1\n");
 
 			/* HACK - We don't need to put the bootstrap mode on here since */
 			/*        we'll simulate it entirely in this function */
@@ -161,7 +161,7 @@ void pcu_reset(dsp56k_core* cpustate)
 			break;
 
 		case 0x01:
-			cpustate->device->logerror("Dsp56k in Special Bootstrap Mode 2\n");
+			cpustate->device->logerror("Dsp56156 in Special Bootstrap Mode 2\n");
 
 			/* HACK - Turn bootstrap mode on.  This hijacks the CPU execute loop and lets */
 			/*        Either the host interface or the SSIO interface suck in all the data */
@@ -171,12 +171,12 @@ void pcu_reset(dsp56k_core* cpustate)
 			if (cpustate->program->read_word(0xc000<<1) & 0x8000)
 			{
 				cpustate->bootstrap_mode = BOOTSTRAP_SSIX;
-				cpustate->device->logerror("DSP56k : Currently in (hacked) bootstrap mode - reading from SSIx.\n");
+				cpustate->device->logerror("DSP56156 : Currently in (hacked) bootstrap mode - reading from SSIx.\n");
 			}
 			else
 			{
 				cpustate->bootstrap_mode = BOOTSTRAP_HI;
-				cpustate->device->logerror("DSP56k : Currently in (hacked) bootstrap mode - reading from Host Interface.\n");
+				cpustate->device->logerror("DSP56156 : Currently in (hacked) bootstrap mode - reading from Host Interface.\n");
 			}
 
 			/* HACK - Set the PC to 0x0000 as per the boot ROM. */
@@ -189,13 +189,13 @@ void pcu_reset(dsp56k_core* cpustate)
 			break;
 
 		case 0x02:
-			cpustate->device->logerror("Dsp56k in Normal Expanded Mode\n");
+			cpustate->device->logerror("Dsp56156 in Normal Expanded Mode\n");
 			PC = 0xe000;
 			cpustate->PCU.reset_vector = 0xe000;
 			break;
 
 		case 0x03:
-			cpustate->device->logerror("Dsp56k in Development Expanded Mode\n");
+			cpustate->device->logerror("Dsp56156 in Development Expanded Mode\n");
 			/* TODO: Disable internal ROM, etc.  Likely a tricky thing for MAME? */
 			PC = 0x0000;
 			cpustate->PCU.reset_vector = 0x0000;
@@ -232,33 +232,33 @@ void pcu_reset(dsp56k_core* cpustate)
 	CD_bit_set(cpustate, 0);
 
 	/* Clear out the pending interrupt list */
-	dsp56k_clear_pending_interrupts(cpustate);
+	dsp56156_clear_pending_interrupts(cpustate);
 }
 
 /***************************************************************************
     INTERRUPT HANDLING
 ***************************************************************************/
-struct dsp56k_irq_data
+struct dsp56156_irq_data
 {
 	uint16_t irq_vector;
 	char   irq_source[128];
 };
 
-dsp56k_irq_data dsp56k_interrupt_sources[32];
+dsp56156_irq_data dsp56156_interrupt_sources[32];
 
 /* TODO: Figure out how to switch on level versus edge-triggered. */
-void pcu_service_interrupts(dsp56k_core* cpustate)
+void pcu_service_interrupts(dsp56156_core* cpustate)
 {
 	int i;
 
 	/* Count list of pending interrupts */
-	int num_servicable = dsp56k_count_pending_interrupts(cpustate);
+	int num_servicable = dsp56156_count_pending_interrupts(cpustate);
 
 	if (num_servicable == 0)
 		return;
 
 	/* Sort list according to priority */
-	dsp56k_sort_pending_interrupts(cpustate, num_servicable);
+	dsp56156_sort_pending_interrupts(cpustate, num_servicable);
 
 	/* Service each interrupt in order */
 	/* TODO: This just *can't* be right :) */
@@ -267,7 +267,7 @@ void pcu_service_interrupts(dsp56k_core* cpustate)
 		const int interrupt_index = cpustate->PCU.pending_interrupts[i];
 
 		/* Get the priority of the interrupt - a return value of -1 means disabled! */
-		int8_t priority = dsp56k_get_irq_priority(cpustate, interrupt_index);
+		int8_t priority = dsp56156_get_irq_priority(cpustate, interrupt_index);
 
 		/* 1-12 Make sure you're not masked out against the Interrupt Mask Bits (disabled is handled for free here) */
 		if (priority >= I_bits(cpustate))
@@ -279,7 +279,7 @@ void pcu_service_interrupts(dsp56k_core* cpustate)
 			if (interrupt_index != 22)
 			{
 				/* Execute a normal interrupt */
-				PC = dsp56k_interrupt_sources[interrupt_index].irq_vector;
+				PC = dsp56156_interrupt_sources[interrupt_index].irq_vector;
 			}
 			else
 			{
@@ -294,15 +294,15 @@ void pcu_service_interrupts(dsp56k_core* cpustate)
 		}
 	}
 
-	dsp56k_clear_pending_interrupts(cpustate);
+	dsp56156_clear_pending_interrupts(cpustate);
 }
 
 
 /* Register an interrupt  */
-void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name)
+void dsp56156_add_pending_interrupt(dsp56156_core* cpustate, const char* name)
 {
 	int i;
-	int irq_index = dsp56k_get_irq_index_by_tag(name);
+	int irq_index = dsp56156_get_irq_index_by_tag(name);
 
 	for (i = 0; i < 32; i++)
 	{
@@ -315,54 +315,54 @@ void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name)
 }
 
 /* Utility function to construct IRQ table */
-void dsp56k_set_irq_source(uint8_t irq_num, uint16_t iv, const char* source)
+void dsp56156_set_irq_source(uint8_t irq_num, uint16_t iv, const char* source)
 {
-	dsp56k_interrupt_sources[irq_num].irq_vector = iv;
-	strcpy(dsp56k_interrupt_sources[irq_num].irq_source, source);
+	dsp56156_interrupt_sources[irq_num].irq_vector = iv;
+	strcpy(dsp56156_interrupt_sources[irq_num].irq_source, source);
 }
 
 /* Construct a table containing pertient IRQ information */
-void dsp56k_irq_table_init(void)
+void dsp56156_irq_table_init(void)
 {
 	/* 1-14 + 1-18 */
 	/* TODO: Cull host command stuff appropriately */
 	/* array index . vector . token */
-	dsp56k_set_irq_source(0,  0x0000, "Hardware RESET");
-	dsp56k_set_irq_source(1,  0x0002, "Illegal Instruction");
-	dsp56k_set_irq_source(2,  0x0004, "Stack Error");
-	dsp56k_set_irq_source(3,  0x0006, "Reserved");
-	dsp56k_set_irq_source(4,  0x0008, "SWI");
-	dsp56k_set_irq_source(5,  0x000a, "IRQA");
-	dsp56k_set_irq_source(6,  0x000c, "IRQB");
-	dsp56k_set_irq_source(7,  0x000e, "Reserved");
-	dsp56k_set_irq_source(8,  0x0010, "SSI0 Receive Data with Exception");
-	dsp56k_set_irq_source(9,  0x0012, "SSI0 Receive Data");
-	dsp56k_set_irq_source(10, 0x0014, "SSI0 Transmit Data with Exception");
-	dsp56k_set_irq_source(11, 0x0016, "SSI0 Transmit Data");
-	dsp56k_set_irq_source(12, 0x0018, "SSI1 Receive Data with Exception");
-	dsp56k_set_irq_source(13, 0x001a, "SSI1 Receive Data");
-	dsp56k_set_irq_source(14, 0x001c, "SSI1 Transmit Data with Exception");
-	dsp56k_set_irq_source(15, 0x001e, "SSI1 Transmit Data");
-	dsp56k_set_irq_source(16, 0x0020, "Timer Overflow");
-	dsp56k_set_irq_source(17, 0x0022, "Timer Compare");
-	dsp56k_set_irq_source(18, 0x0024, "Host DMA Receive Data");
-	dsp56k_set_irq_source(19, 0x0026, "Host DMA Transmit Data");
-	dsp56k_set_irq_source(20, 0x0028, "Host Receive Data");
-	dsp56k_set_irq_source(21, 0x002a, "Host Transmit Data");
-	dsp56k_set_irq_source(22, 0x002c, "Host Command");              /* Default vector for the host command */
-	dsp56k_set_irq_source(23, 0x002e, "Codec Receive/Transmit");
-	dsp56k_set_irq_source(24, 0x0030, "Host Command 1");
-	dsp56k_set_irq_source(25, 0x0032, "Host Command 2");
-	dsp56k_set_irq_source(26, 0x0034, "Host Command 3");
-	dsp56k_set_irq_source(27, 0x0036, "Host Command 4");
-	dsp56k_set_irq_source(28, 0x0038, "Host Command 5");
-	dsp56k_set_irq_source(29, 0x003a, "Host Command 6");
-	dsp56k_set_irq_source(30, 0x003c, "Host Command 7");
-	dsp56k_set_irq_source(31, 0x003e, "Host Command 8");
+	dsp56156_set_irq_source(0,  0x0000, "Hardware RESET");
+	dsp56156_set_irq_source(1,  0x0002, "Illegal Instruction");
+	dsp56156_set_irq_source(2,  0x0004, "Stack Error");
+	dsp56156_set_irq_source(3,  0x0006, "Reserved");
+	dsp56156_set_irq_source(4,  0x0008, "SWI");
+	dsp56156_set_irq_source(5,  0x000a, "IRQA");
+	dsp56156_set_irq_source(6,  0x000c, "IRQB");
+	dsp56156_set_irq_source(7,  0x000e, "Reserved");
+	dsp56156_set_irq_source(8,  0x0010, "SSI0 Receive Data with Exception");
+	dsp56156_set_irq_source(9,  0x0012, "SSI0 Receive Data");
+	dsp56156_set_irq_source(10, 0x0014, "SSI0 Transmit Data with Exception");
+	dsp56156_set_irq_source(11, 0x0016, "SSI0 Transmit Data");
+	dsp56156_set_irq_source(12, 0x0018, "SSI1 Receive Data with Exception");
+	dsp56156_set_irq_source(13, 0x001a, "SSI1 Receive Data");
+	dsp56156_set_irq_source(14, 0x001c, "SSI1 Transmit Data with Exception");
+	dsp56156_set_irq_source(15, 0x001e, "SSI1 Transmit Data");
+	dsp56156_set_irq_source(16, 0x0020, "Timer Overflow");
+	dsp56156_set_irq_source(17, 0x0022, "Timer Compare");
+	dsp56156_set_irq_source(18, 0x0024, "Host DMA Receive Data");
+	dsp56156_set_irq_source(19, 0x0026, "Host DMA Transmit Data");
+	dsp56156_set_irq_source(20, 0x0028, "Host Receive Data");
+	dsp56156_set_irq_source(21, 0x002a, "Host Transmit Data");
+	dsp56156_set_irq_source(22, 0x002c, "Host Command");              /* Default vector for the host command */
+	dsp56156_set_irq_source(23, 0x002e, "Codec Receive/Transmit");
+	dsp56156_set_irq_source(24, 0x0030, "Host Command 1");
+	dsp56156_set_irq_source(25, 0x0032, "Host Command 2");
+	dsp56156_set_irq_source(26, 0x0034, "Host Command 3");
+	dsp56156_set_irq_source(27, 0x0036, "Host Command 4");
+	dsp56156_set_irq_source(28, 0x0038, "Host Command 5");
+	dsp56156_set_irq_source(29, 0x003a, "Host Command 6");
+	dsp56156_set_irq_source(30, 0x003c, "Host Command 7");
+	dsp56156_set_irq_source(31, 0x003e, "Host Command 8");
 }
 
 /* Clear all entries from the pending table */
-void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate)
+void dsp56156_clear_pending_interrupts(dsp56156_core* cpustate)
 {
 	int i;
 	for (i = 0; i < 32; i++)
@@ -372,7 +372,7 @@ void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate)
 }
 
 /* Recover number of pending irqs */
-int dsp56k_count_pending_interrupts(dsp56k_core* cpustate)
+int dsp56156_count_pending_interrupts(dsp56156_core* cpustate)
 {
 	int numI = 0;
 	while (cpustate->PCU.pending_interrupts[numI] != -1)
@@ -384,7 +384,7 @@ int dsp56k_count_pending_interrupts(dsp56k_core* cpustate)
 }
 
 /* Sort the pending irqs by priority */
-void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num)
+void dsp56156_sort_pending_interrupts(dsp56156_core* cpustate, int num)
 {
 	int i, j;
 
@@ -392,7 +392,7 @@ void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num)
 	int priority_list[32];
 	for (i = 0; i < num; i++)
 	{
-		priority_list[i] = dsp56k_get_irq_priority(cpustate, cpustate->PCU.pending_interrupts[i]);
+		priority_list[i] = dsp56156_get_irq_priority(cpustate, cpustate->PCU.pending_interrupts[i]);
 	}
 
 	/* Bubble sort should be good enough for us */
@@ -421,7 +421,7 @@ void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num)
 }
 
 /* Given an index into the irq table, return the interrupt's current priority */
-int8_t dsp56k_get_irq_priority(dsp56k_core* cpustate, int index)
+int8_t dsp56156_get_irq_priority(dsp56156_core* cpustate, int index)
 {
 	/* 1-12 */
 	switch (index)
@@ -469,20 +469,20 @@ int8_t dsp56k_get_irq_priority(dsp56k_core* cpustate, int index)
 }
 
 /* Given an IRQ name, return its index in the irq table */
-int dsp56k_get_irq_index_by_tag(const char* tag)
+int dsp56156_get_irq_index_by_tag(const char* tag)
 {
 	int i;
 	for (i = 0; i < 32; i++)
 	{
-		if (strcmp(tag, dsp56k_interrupt_sources[i].irq_source) == 0)
+		if (strcmp(tag, dsp56156_interrupt_sources[i].irq_source) == 0)
 		{
 			return i;
 		}
 	}
 
-	fatalerror("DSP56K ERROR : IRQ TAG specified incorrectly (get_vector_by_tag) : %s.\n", tag);
+	fatalerror("DSP56156 ERROR : IRQ TAG specified incorrectly (get_vector_by_tag) : %s.\n", tag);
 	// never executed
 	//return -1;
 }
 
-} // namespace DSP56K
+} // namespace DSP_56156
diff --git a/src/devices/cpu/dsp56156/dsp56pcu.h b/src/devices/cpu/dsp56156/dsp56pcu.h
new file mode 100644
index 00000000000..a04f7bf1f26
--- /dev/null
+++ b/src/devices/cpu/dsp56156/dsp56pcu.h
@@ -0,0 +1,150 @@
+// license:BSD-3-Clause
+// copyright-holders:Andrew Gardner
+#ifndef DSP56156_PCU_H
+#define DSP56156_PCU_H
+
+#include "dsp56156.h"
+
+namespace DSP_56156
+{
+/***************************************************************************
+    PCU
+***************************************************************************/
+void pcu_reset(dsp56156_core* cpustate);
+void pcu_init(dsp56156_core* cpustate, device_t *device);
+#define PC  (cpustate->PCU.pc)
+#define LA  (cpustate->PCU.la)
+#define LC  (cpustate->PCU.lc)
+#define SR  (cpustate->PCU.sr)
+#define OMR (cpustate->PCU.omr)
+#define SP  (cpustate->PCU.sp)
+#define SS  (cpustate->PCU.ss)
+
+#define SSH (SS[SP].w.h)
+#define SSL (SS[SP].w.l)
+
+#define ST0     (SS[0].d)
+#define ST1     (SS[1].d)
+#define ST2     (SS[2].d)
+#define ST3     (SS[3].d)
+#define ST4     (SS[4].d)
+#define ST5     (SS[5].d)
+#define ST6     (SS[6].d)
+#define ST7     (SS[7].d)
+#define ST8     (SS[8].d)
+#define ST9     (SS[9].d)
+#define ST10    (SS[10].d)
+#define ST11    (SS[11].d)
+#define ST12    (SS[12].d)
+#define ST13    (SS[13].d)
+#define ST14    (SS[14].d)
+#define ST15    (SS[15].d)
+
+/* STATUS REGISTER (SR) BITS (1-25) */
+/* MR */
+uint8_t LF_bit(const dsp56156_core* cpustate);
+uint8_t FV_bit(const dsp56156_core* cpustate);
+//uint8_t S_bits(const dsp56156_core* cpustate);
+uint8_t I_bits(const dsp56156_core* cpustate);
+
+/* CCR - with macros for easy access */
+#define S() (S_bit(cpustate))
+uint8_t S_bit(const dsp56156_core* cpustate);
+#define L() (L_bit(cpustate))
+uint8_t L_bit(const dsp56156_core* cpustate);
+#define E() (E_bit(cpustate))
+uint8_t E_bit(const dsp56156_core* cpustate);
+#define U() (U_bit(cpustate))
+uint8_t U_bit(const dsp56156_core* cpustate);
+#define N() (N_bit(cpustate))
+uint8_t N_bit(const dsp56156_core* cpustate);
+#define Z() (Z_bit(cpustate))
+uint8_t Z_bit(const dsp56156_core* cpustate);
+#define V() (V_bit(cpustate))
+uint8_t V_bit(const dsp56156_core* cpustate);
+#define C() (C_bit(cpustate))
+uint8_t C_bit(const dsp56156_core* cpustate);
+
+/* MR setters */
+void LF_bit_set(dsp56156_core* cpustate, uint8_t value);
+void FV_bit_set(dsp56156_core* cpustate, uint8_t value);
+void S_bits_set(dsp56156_core* cpustate, uint8_t value);
+void I_bits_set(dsp56156_core* cpustate, uint8_t value);
+
+/* CCR setters - with macros for easy access */
+#define DSP56156_S_SET() (S_bit_set(cpustate, 1))
+#define DSP56156_S_CLEAR() (S_bit_set(cpustate, 0))
+void S_bit_set(dsp56156_core* cpustate, uint8_t value);
+#define DSP56156_L_SET() (L_bit_set(cpustate, 1))
+#define DSP56156_L_CLEAR() (L_bit_set(cpustate, 0))
+void L_bit_set(dsp56156_core* cpustate, uint8_t value);
+#define DSP56156_E_SET() (E_bit_set(cpustate, 1))
+#define DSP56156_E_CLEAR() (E_bit_set(cpustate, 0))
+void E_bit_set(dsp56156_core* cpustate, uint8_t value);
+#define DSP56156_U_SET() (U_bit_set(cpustate, 1))
+#define DSP56156_U_CLEAR() (U_bit_set(cpustate, 0))
+void U_bit_set(dsp56156_core* cpustate, uint8_t value);
+#define DSP56156_N_SET() (N_bit_set(cpustate, 1))
+#define DSP56156_N_CLEAR() (N_bit_set(cpustate, 0))
+void N_bit_set(dsp56156_core* cpustate, uint8_t value);
+#define DSP56156_Z_SET() (Z_bit_set(cpustate, 1))
+#define DSP56156_Z_CLEAR() (Z_bit_set(cpustate, 0))
+void Z_bit_set(dsp56156_core* cpustate, uint8_t value);
+#define DSP56156_V_SET() (V_bit_set(cpustate, 1))
+#define DSP56156_V_CLEAR() (V_bit_set(cpustate, 0))
+void V_bit_set(dsp56156_core* cpustate, uint8_t value);
+#define DSP56156_C_SET() (C_bit_set(cpustate, 1))
+#define DSP56156_C_CLEAR() (C_bit_set(cpustate, 0))
+void C_bit_set(dsp56156_core* cpustate, uint8_t value);
+
+// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here?
+
+
+/* 1-28 OPERATING MODE REGISTER (OMR) BITS */
+//uint8_t CD_bit(const dsp56156_core* cpustate);
+//uint8_t SD_bit(const dsp56156_core* cpustate);
+//uint8_t R_bit(const dsp56156_core* cpustate);
+//uint8_t SA_bit(const dsp56156_core* cpustate);
+//uint8_t MC_bit(const dsp56156_core* cpustate);
+uint8_t MB_bit(const dsp56156_core* cpustate);
+uint8_t MA_bit(const dsp56156_core* cpustate);
+
+void CD_bit_set(dsp56156_core* cpustate, uint8_t value);
+void SD_bit_set(dsp56156_core* cpustate, uint8_t value);
+void R_bit_set(dsp56156_core* cpustate, uint8_t value);
+void SA_bit_set(dsp56156_core* cpustate, uint8_t value);
+void MC_bit_set(dsp56156_core* cpustate, uint8_t value);
+void MB_bit_set(dsp56156_core* cpustate, uint8_t value);
+void MA_bit_set(dsp56156_core* cpustate, uint8_t value);
+
+/* 1-27 STACK POINTER (SP) BITS */
+uint8_t UF_bit(const dsp56156_core* cpustate);
+uint8_t SE_bit(const dsp56156_core* cpustate);
+
+//void UF_bit_set(dsp56156_core* cpustate, uint8_t value) {};
+//void SE_bit_set(dsp56156_core* cpustate, uint8_t value) {};
+
+
+// HACK - Bootstrap modes
+#define BOOTSTRAP_OFF (0)
+#define BOOTSTRAP_SSIX (1)
+#define BOOTSTRAP_HI (2)
+
+
+/* PCU IRQ goodies */
+void pcu_service_interrupts(dsp56156_core* cpustate);
+
+void dsp56156_irq_table_init(void);
+void dsp56156_set_irq_source(uint8_t irq_num, uint16_t iv, const char* source);
+int dsp56156_get_irq_index_by_tag(const char* tag);
+
+void dsp56156_add_pending_interrupt(dsp56156_core* cpustate, const char* name);     // Call me to add an interrupt to the queue
+
+void dsp56156_clear_pending_interrupts(dsp56156_core* cpustate);
+int dsp56156_count_pending_interrupts(dsp56156_core* cpustate);
+void dsp56156_sort_pending_interrupts(dsp56156_core* cpustate, int num);
+int8_t dsp56156_get_irq_priority(dsp56156_core* cpustate, int index);
+
+} // namespace DSP_56156
+
+#endif
diff --git a/src/devices/cpu/dsp56k/inst.cpp b/src/devices/cpu/dsp56156/inst.cpp
similarity index 99%
rename from src/devices/cpu/dsp56k/inst.cpp
rename to src/devices/cpu/dsp56156/inst.cpp
index d7c99777338..339156aa35e 100644
--- a/src/devices/cpu/dsp56k/inst.cpp
+++ b/src/devices/cpu/dsp56156/inst.cpp
@@ -4,7 +4,7 @@
 #include "inst.h"
 #include "emu.h"
 
-namespace DSP56K
+namespace DSP_56156
 {
 // Factory
 std::unique_ptr<Instruction> Instruction::decodeInstruction(const Opcode* opc,
diff --git a/src/devices/cpu/dsp56k/inst.h b/src/devices/cpu/dsp56156/inst.h
similarity index 94%
rename from src/devices/cpu/dsp56k/inst.h
rename to src/devices/cpu/dsp56156/inst.h
index d2db2a013e9..c471b492ecf 100644
--- a/src/devices/cpu/dsp56k/inst.h
+++ b/src/devices/cpu/dsp56156/inst.h
@@ -1,19 +1,19 @@
 // license:BSD-3-Clause
 // copyright-holders:Andrew Gardner
-#ifndef __DSP56K_INSTRUCTION_H__
-#define __DSP56K_INSTRUCTION_H__
+#ifndef DSP56156_INSTRUCTION_H
+#define DSP56156_INSTRUCTION_H
 
 #include "opcode.h"
 #include "tables.h"
 
-#include "dsp56k.h"
+#include "dsp56156.h"
 #include "dsp56def.h"
 #include "dsp56pcu.h"
 
 //
 // An Instruction is the base class all regular ops inherit from.
 //
-namespace DSP56K
+namespace DSP_56156
 {
 #define UNIMPLEMENTED_OPCODE() osd_printf_error("Unimplemented opcode:  PC=%04x | %s;\n", PC, __PRETTY_FUNCTION__);
 
@@ -31,7 +31,7 @@ public:
 
 	virtual bool decode(const uint16_t word0, const uint16_t word1) = 0;
 	virtual void disassemble(std::string& retString) const = 0;
-	virtual void evaluate(dsp56k_core* cpustate) = 0;
+	virtual void evaluate(dsp56156_core* cpustate) = 0;
 
 	virtual size_t size() const = 0;
 	virtual size_t evalSize() const { return size(); }
@@ -82,7 +82,7 @@ public:
 	{
 		retString = "abs " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -105,7 +105,7 @@ public:
 	{
 		retString = "adc " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -128,7 +128,7 @@ public:
 	{
 		retString = "add " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -155,7 +155,7 @@ public:
 	{
 		retString = m_opcode + " " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -182,7 +182,7 @@ public:
 	{
 		retString = "and " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -209,7 +209,7 @@ public:
 		retString = "andi " + std::string(temp);
 		// NEW // sprintf(opcode_str, "and(i)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -234,7 +234,7 @@ public:
 	{
 		retString = "asl " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -256,7 +256,7 @@ public:
 	{
 		retString = "asl4 " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -278,7 +278,7 @@ public:
 	{
 		retString = "asr " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -300,7 +300,7 @@ public:
 	{
 		retString = "asr4 " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -322,7 +322,7 @@ public:
 	{
 		retString = "asr16 " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -379,7 +379,7 @@ public:
 		retString = m_opcode + " " + std::string(temp) + "," + dString;
 		// NEW // sprintf(temp, "#$%04x", iVal);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 private:
@@ -445,7 +445,7 @@ public:
 		retString = m_opcode + " " + source + "," + destination;
 		// NEW // sprintf(temp, "#$%04x", m_iVal);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -508,7 +508,7 @@ public:
 		retString = m_opcode + " " + source + "," + regIdAsString(m_destination);
 		// NEW // sprintf(temp, "#$%04x", m_iVal);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -543,7 +543,7 @@ public:
 		// NEW // sprintf(temp, "$%04x (%d)", pc + 2 + (int16_t)word1, (int16_t)word1);
 		retString = opcode + " " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -580,7 +580,7 @@ public:
 
 		retString = opcode + " " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -610,7 +610,7 @@ public:
 		retString = opcode + " " + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "b.%s", M);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -639,7 +639,7 @@ public:
 		// NEW // sprintf(temp, "$%04x (%d)", pc + 2 + word1, (int16_t)word1);
 		retString = "bra " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -669,7 +669,7 @@ public:
 		// NEW // sprintf(temp, "$%04x (%d)", pc + 1 + iVal, iVal);
 		retString = "bra " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -694,7 +694,7 @@ public:
 	{
 		retString = "bra " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -719,7 +719,7 @@ public:
 		retString = opcode;
 		// NEW // sprintf(opcode_str, "brk.%s", M);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -755,7 +755,7 @@ public:
 		// NEW // sprintf(temp, "$%04x (%d)", pc + 2 + (int16_t)word1, (int16_t)word1);
 		retString = opcode + " " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -786,7 +786,7 @@ public:
 		retString = opcode + " " + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "bs.%s", M);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -817,7 +817,7 @@ public:
 		// NEW // sprintf(temp, "$%04x (%d)", pc + 2 + (int16_t)word1, (int16_t)word1);
 		retString = "bsr " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -843,7 +843,7 @@ public:
 	{
 		retString = "bsr " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -865,7 +865,7 @@ public:
 	{
 		retString = "chkaau";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -887,7 +887,7 @@ public:
 	{
 		retString = "clr " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -909,7 +909,7 @@ public:
 	{
 		retString = "clr24 " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -934,7 +934,7 @@ public:
 	{
 		retString = "cmp " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_NONE; }
 };
@@ -959,7 +959,7 @@ public:
 	{
 		retString = "cmpm " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_NONE; }
 };
@@ -980,7 +980,7 @@ public:
 	{
 		retString = "debug";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -1005,7 +1005,7 @@ public:
 		retString = opcode;
 		// NEW // sprintf(opcode_str, "debug.%s", M);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1030,7 +1030,7 @@ public:
 	{
 		retString = "dec " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -1052,7 +1052,7 @@ public:
 	{
 		retString = "dec24 " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -1075,7 +1075,7 @@ public:
 	{
 		retString = "div " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -1108,7 +1108,7 @@ public:
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "dmac(%s)", A);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1144,7 +1144,7 @@ public:
 
 		retString = "do " + source + "," + destination;
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1175,7 +1175,7 @@ public:
 		// NEW // sprintf(temp, "#$%02x,$%04x", BITSn(word0,0x00ff), pc + 2 + word1);
 		retString = "do " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1209,7 +1209,7 @@ public:
 		// NEW // sprintf(temp, "%s,$%04x", S1, pc + 2 + word1);
 		retString = "do " + regIdAsString(m_source) + "," + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1239,7 +1239,7 @@ public:
 		// NEW // sprintf(temp, "$%04x", pc + 2 + word1);
 		retString = "do forever, " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1263,7 +1263,7 @@ public:
 	{
 		retString = "enddo";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -1286,7 +1286,7 @@ public:
 	{
 		retString = "eor " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -1308,7 +1308,7 @@ public:
 	{
 		retString = "ext " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -1329,7 +1329,7 @@ public:
 	{
 		retString = "illegal";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -1355,7 +1355,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1384,7 +1384,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1409,7 +1409,7 @@ public:
 	{
 		retString = "inc " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -1431,7 +1431,7 @@ public:
 	{
 		retString = "inc24 " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -1462,7 +1462,7 @@ public:
 		// NEW // sprintf(temp, "$%04x", word1);
 		retString = opcode + " " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1492,7 +1492,7 @@ public:
 		retString = opcode + " " + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "j.%s", M);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1521,7 +1521,7 @@ public:
 		// NEW // sprintf(temp, "$%04x", word1);
 		retString = "jmp " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override
+	void evaluate(dsp56156_core* cpustate) override
 	{
 		PC = m_displacement;
 
@@ -1553,7 +1553,7 @@ public:
 	{
 		retString = "jmp " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override
+	void evaluate(dsp56156_core* cpustate) override
 	{
 		PC = regValue16(cpustate, m_destination);
 
@@ -1593,7 +1593,7 @@ public:
 		// NEW // sprintf(temp, "$%04x", word1);
 		retString = opcode + " " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -1624,7 +1624,7 @@ public:
 		retString = opcode + " " + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "js.%s", M);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -1654,7 +1654,7 @@ public:
 		// NEW // sprintf(temp, "$%04x", word1);
 		retString = "jsr " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -1684,7 +1684,7 @@ public:
 		// NEW // sprintf(temp, "#$%02x", BITSn(word0,0x00ff));
 		retString = "jsr " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -1710,7 +1710,7 @@ public:
 	{
 		retString = "jsr " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OVER; }
@@ -1741,7 +1741,7 @@ public:
 		// HACK
 		retString = "lea " + m_ea + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1773,7 +1773,7 @@ public:
 		// HACK
 		retString = "lea " + m_ea + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1798,7 +1798,7 @@ public:
 	{
 		retString = "lsl " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -1820,7 +1820,7 @@ public:
 	{
 		retString = "lsr " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -1852,7 +1852,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1882,7 +1882,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1911,7 +1911,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1946,7 +1946,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -1976,7 +1976,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2012,7 +2012,7 @@ public:
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "mac(%s)", A);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2055,7 +2055,7 @@ public:
 		else
 			retString = "move";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_NONE; }
 
@@ -2086,7 +2086,7 @@ public:
 	{
 		retString = "move";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -2116,7 +2116,7 @@ public:
 		assemble_reg_from_W_table(m_W, 'X', m_SD, m_b, source, destination);
 		retString = "move " + source + "," + destination;
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2155,7 +2155,7 @@ public:
 		retString = "move " + source + "," + destination;
 		// NEW // sprintf(opcode_str, "move(c)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2194,7 +2194,7 @@ public:
 		retString = "move " + source + "," + destination;
 		// NEW // sprintf(opcode_str, "move(c)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2232,7 +2232,7 @@ public:
 		retString = "move " + source + "," + destination;
 		// NEW // sprintf(opcode_str, "move(c)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2278,7 +2278,7 @@ public:
 		else     retString += regIdAsString(m_sd) + "," + ea;
 		// NEW // sprintf(opcode_str, "move(c)");
 	}
-	void evaluate(dsp56k_core* cpustate) override
+	void evaluate(dsp56156_core* cpustate) override
 	{
 		if (m_W)
 		{
@@ -2343,7 +2343,7 @@ public:
 		retString = "move " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "move(c)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -2375,7 +2375,7 @@ public:
 		retString = "move " + source + "," + destination;
 		// NEW // opcode = "move(c)";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2412,7 +2412,7 @@ public:
 			std::string(temp) + "," + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "move(i)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2448,7 +2448,7 @@ public:
 		retString = "move " + source + "," + destination;
 		// NEW // sprintf(opcode_str, "move(m)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2492,7 +2492,7 @@ public:
 		retString = "move " + source + "," + destination;
 		// NEW // sprintf(opcode_str, "move(m)*");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2528,7 +2528,7 @@ public:
 		retString = "move " + source + "," + destination;
 		// NEW // opcode = "move(m)";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 2; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2568,7 +2568,7 @@ public:
 		retString = "movep " + source + "," + destination;
 		// NEW // sprintf(opcode_str, "move(p)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2611,7 +2611,7 @@ public:
 		retString = "movep " + source + "," + destination;
 		// NEW // sprintf(opcode_str, "move(p)*");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2651,7 +2651,7 @@ public:
 		retString = "moves " + source + "," + destination;
 		// NEW // sprintf(opcode_str, "move(s)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2690,7 +2690,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2720,7 +2720,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2749,7 +2749,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2786,7 +2786,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2816,7 +2816,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2851,7 +2851,7 @@ public:
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "mpy(%s)", A);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -2877,7 +2877,7 @@ public:
 	{
 		retString = "neg " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -2899,7 +2899,7 @@ public:
 	{
 		retString = "negc " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -2920,7 +2920,7 @@ public:
 	{
 		retString = "nop";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -2944,7 +2944,7 @@ public:
 	{
 		retString = "norm " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -2966,7 +2966,7 @@ public:
 	{
 		retString = "not " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -2989,7 +2989,7 @@ public:
 	{
 		retString = "or " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -3017,7 +3017,7 @@ public:
 		retString = "ori " + std::string(temp) + "," + regIdAsString(m_destination);
 		// NEW // sprintf(opcode_str, "or(i)");
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -3044,7 +3044,7 @@ public:
 		sprintf(temp, "X:(%s)", regIdAsString(m_source).c_str());
 		retString = "rep " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3070,7 +3070,7 @@ public:
 		// NEW // sprintf(temp, "#$%02x (%d)", BITSn(word0,0x00ff), BITSn(word0,0x00ff));
 		retString = "rep " + std::string(temp);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -3096,7 +3096,7 @@ public:
 	{
 		retString = "rep " + regIdAsString(m_source);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3121,7 +3121,7 @@ public:
 		retString = opcode;
 		// NEW // sprintf(opcode_str, "rep.%s", M);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -3145,7 +3145,7 @@ public:
 	{
 		retString = "reset";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3167,7 +3167,7 @@ public:
 	{
 		retString = "rnd " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3189,7 +3189,7 @@ public:
 	{
 		retString = "rol " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -3211,7 +3211,7 @@ public:
 	{
 		retString = "ror " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE; }
 };
@@ -3232,7 +3232,7 @@ public:
 	{
 		retString = "rti";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OUT; }
@@ -3254,7 +3254,7 @@ public:
 	{
 		retString = "rts";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 	size_t flags() const override { return util::disasm_interface::STEP_OUT; }
@@ -3278,7 +3278,7 @@ public:
 	{
 		retString = "sbc " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3299,7 +3299,7 @@ public:
 	{
 		retString = "stop";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3322,7 +3322,7 @@ public:
 	{
 		retString = "sub " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3348,7 +3348,7 @@ public:
 	{
 		retString = m_opcode + " " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -3383,7 +3383,7 @@ public:
 	{
 		retString = "subl " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3405,7 +3405,7 @@ public:
 	{
 		retString = "swap " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3426,7 +3426,7 @@ public:
 	{
 		retString = "swi";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3468,7 +3468,7 @@ public:
 		if (m_destination2 != iR0)
 			retString += std::string(" R0,") + regIdAsString(m_destination2);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -3495,7 +3495,7 @@ public:
 	{
 		retString = "tfr " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3518,7 +3518,7 @@ public:
 	{
 		retString = "tfr " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3541,7 +3541,7 @@ public:
 	{
 		retString = "tfr2 " + regIdAsString(m_source) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3583,7 +3583,7 @@ public:
 					regIdAsString(m_source) + "," + regIdAsString(m_destination) + " " +
 					source2 + "," + destination2;
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -3612,7 +3612,7 @@ public:
 	{
 		retString = "tst " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_NONE; }
 };
@@ -3634,7 +3634,7 @@ public:
 	{
 		retString = "tst2 " + regIdAsString(m_source);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3655,7 +3655,7 @@ public:
 	{
 		retString = "wait";
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3677,7 +3677,7 @@ public:
 	{
 		retString = "zero " + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 };
@@ -3718,7 +3718,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
@@ -3762,7 +3762,7 @@ public:
 					regIdAsString(m_source) + "," +
 					regIdAsString(m_source2) + "," + regIdAsString(m_destination);
 	}
-	void evaluate(dsp56k_core* cpustate) override {}
+	void evaluate(dsp56156_core* cpustate) override {}
 	size_t size() const override { return 1; }
 	size_t accumulatorBitsModified() const override { return BM_HIGH | BM_MIDDLE | BM_LOW; }
 
diff --git a/src/devices/cpu/dsp56k/opcode.cpp b/src/devices/cpu/dsp56156/opcode.cpp
similarity index 96%
rename from src/devices/cpu/dsp56k/opcode.cpp
rename to src/devices/cpu/dsp56156/opcode.cpp
index efd1ce6156e..15b305fa09e 100644
--- a/src/devices/cpu/dsp56k/opcode.cpp
+++ b/src/devices/cpu/dsp56156/opcode.cpp
@@ -5,7 +5,7 @@
 
 #include "opcode.h"
 
-namespace DSP56K
+namespace DSP_56156
 {
 Opcode::Opcode(uint16_t w0, uint16_t w1) : m_word0(w0)/*, m_word1(w1)*/
 {
@@ -41,7 +41,7 @@ std::string Opcode::disassemble() const
 }
 
 
-void Opcode::evaluate(dsp56k_core* cpustate) const
+void Opcode::evaluate(dsp56156_core* cpustate) const
 {
 	if (m_instruction) m_instruction->evaluate(cpustate);
 	if (m_parallelMove) m_parallelMove->evaluate();
diff --git a/src/devices/cpu/dsp56k/opcode.h b/src/devices/cpu/dsp56156/opcode.h
similarity index 83%
rename from src/devices/cpu/dsp56k/opcode.h
rename to src/devices/cpu/dsp56156/opcode.h
index 704602d17f3..1044af8f188 100644
--- a/src/devices/cpu/dsp56k/opcode.h
+++ b/src/devices/cpu/dsp56156/opcode.h
@@ -1,17 +1,17 @@
 // license:BSD-3-Clause
 // copyright-holders:Andrew Gardner
-#ifndef __DSP56K_OPCODE_H__
-#define __DSP56K_OPCODE_H__
+#ifndef DSP56156_OPCODE_H
+#define DSP56156_OPCODE_H
 
 #include "inst.h"
 #include "pmove.h"
 
-#include "dsp56k.h"
+#include "dsp56156.h"
 
 //
 // An Opcode contains an instruction and a parallel move operation.
 //
-namespace DSP56K
+namespace DSP_56156
 {
 class Instruction;
 class ParallelMove;
@@ -23,7 +23,7 @@ public:
 	virtual ~Opcode();
 
 	std::string disassemble() const;
-	void evaluate(dsp56k_core* cpustate) const;
+	void evaluate(dsp56156_core* cpustate) const;
 	size_t size() const;
 	size_t evalSize() const;
 
diff --git a/src/devices/cpu/dsp56k/pmove.cpp b/src/devices/cpu/dsp56156/pmove.cpp
similarity index 99%
rename from src/devices/cpu/dsp56k/pmove.cpp
rename to src/devices/cpu/dsp56156/pmove.cpp
index 15a13eb9ecf..514ed2de972 100644
--- a/src/devices/cpu/dsp56k/pmove.cpp
+++ b/src/devices/cpu/dsp56156/pmove.cpp
@@ -3,7 +3,7 @@
 #include "emu.h"
 #include "pmove.h"
 
-namespace DSP56K
+namespace DSP_56156
 {
 const reg_id& ParallelMove::opSource() const { return m_oco->instSource(); }
 const reg_id& ParallelMove::opDestination() const { return m_oco->instDestination(); }
diff --git a/src/devices/cpu/dsp56k/pmove.h b/src/devices/cpu/dsp56156/pmove.h
similarity index 98%
rename from src/devices/cpu/dsp56k/pmove.h
rename to src/devices/cpu/dsp56156/pmove.h
index 86d0932cf2f..bf5cb2ec34a 100644
--- a/src/devices/cpu/dsp56k/pmove.h
+++ b/src/devices/cpu/dsp56156/pmove.h
@@ -1,7 +1,7 @@
 // license:BSD-3-Clause
 // copyright-holders:Andrew Gardner
-#ifndef __DSP56K_PARALLEL_MOVE_H__
-#define __DSP56K_PARALLEL_MOVE_H__
+#ifndef DSP56156_PMOVE_H
+#define DSP56156_PMOVE_H
 
 #include "opcode.h"
 #include "tables.h"
@@ -9,7 +9,7 @@
 //
 // A ParallelMove Object is what all parallel move classes inherit from.
 //
-namespace DSP56K
+namespace DSP_56156
 {
 class Opcode;
 
diff --git a/src/devices/cpu/dsp56k/tables.cpp b/src/devices/cpu/dsp56156/tables.cpp
similarity index 99%
rename from src/devices/cpu/dsp56k/tables.cpp
rename to src/devices/cpu/dsp56156/tables.cpp
index fac697f8fa8..93f591b3a5c 100644
--- a/src/devices/cpu/dsp56k/tables.cpp
+++ b/src/devices/cpu/dsp56156/tables.cpp
@@ -8,7 +8,7 @@
 #include "tables.h"
 #include "dsp56def.h"
 
-namespace DSP56K
+namespace DSP_56156
 {
 /******************/
 /* Table decoding */
@@ -655,7 +655,7 @@ int8_t get_6_bit_signed_value(uint16_t bits)
 /* HELPER FUNCTIONS */
 /********************/
 
-uint16_t dsp56k_op_maskn(uint16_t cur, uint16_t mask)
+uint16_t dsp56156_op_maskn(uint16_t cur, uint16_t mask)
 {
 	int i;
 
@@ -695,7 +695,7 @@ bool registerOverlap(const reg_id& r0, const size_t bmd, const reg_id& r1)
 	return false;
 }
 
-uint16_t regValue16(dsp56k_core* cpustate, const reg_id& reg)
+uint16_t regValue16(dsp56156_core* cpustate, const reg_id& reg)
 {
 	if (reg == iX0) return X0;
 	if (reg == iX1) return X1;
@@ -726,7 +726,7 @@ uint16_t regValue16(dsp56k_core* cpustate, const reg_id& reg)
 	return 0xdead;
 }
 
-void setReg16(dsp56k_core* cpustate, const uint16_t& value, const reg_id& reg)
+void setReg16(dsp56156_core* cpustate, const uint16_t& value, const reg_id& reg)
 {
 	if (reg == iX0) X0 = value;
 	if (reg == iX1) X1 = value;
diff --git a/src/devices/cpu/dsp56k/tables.h b/src/devices/cpu/dsp56156/tables.h
similarity index 91%
rename from src/devices/cpu/dsp56k/tables.h
rename to src/devices/cpu/dsp56156/tables.h
index 05c11db908b..9ef1dc76b32 100644
--- a/src/devices/cpu/dsp56k/tables.h
+++ b/src/devices/cpu/dsp56156/tables.h
@@ -1,16 +1,16 @@
 // license:BSD-3-Clause
 // copyright-holders:Andrew Gardner
-#ifndef __DSP56K_OPS_H__
-#define __DSP56K_OPS_H__
+#ifndef DSP56156_TABLES_H
+#define DSP56156_TABLES_H
 
 #include <stdio.h>
 #include <stdlib.h>
 
-#include "dsp56k.h"
+#include "dsp56156.h"
 
-namespace DSP56K
+namespace DSP_56156
 {
-#define BITSn(CUR,MASK) (dsp56k_op_maskn(CUR,MASK))
+#define BITSn(CUR,MASK) (dsp56156_op_maskn(CUR,MASK))
 
 enum bitsModified {BM_NONE = 0x0, BM_LOW = 0x1, BM_MIDDLE = 0x2, BM_HIGH = 0x4};
 
@@ -76,12 +76,12 @@ void assemble_address_from_IO_short_address(uint16_t pp, std::string& ea);
 int8_t get_6_bit_signed_value(uint16_t bits);
 
 // Helpers
-uint16_t dsp56k_op_maskn(uint16_t cur, uint16_t mask);
+uint16_t dsp56156_op_maskn(uint16_t cur, uint16_t mask);
 
 bool registerOverlap(const reg_id& r0, const size_t bmd, const reg_id& r1);
 
-uint16_t regValue16(dsp56k_core* cpustate, const reg_id& reg);
-void setReg16(dsp56k_core* cpustate, const uint16_t& value, const reg_id& reg);
+uint16_t regValue16(dsp56156_core* cpustate, const reg_id& reg);
+void setReg16(dsp56156_core* cpustate, const uint16_t& value, const reg_id& reg);
 
 std::string regIdAsString(const reg_id& regId);
 std::string opMnemonicAsString(const op_mnem& mnem);
diff --git a/src/devices/cpu/dsp56k/dsp56k.cpp b/src/devices/cpu/dsp56k/dsp56k.cpp
deleted file mode 100644
index c4da3de678a..00000000000
--- a/src/devices/cpu/dsp56k/dsp56k.cpp
+++ /dev/null
@@ -1,515 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Andrew Gardner
-/***************************************************************************
-
-    dsp56k.c
-    Core implementation for the portable DSP56k emulator.
-    Written by Andrew Gardner
-
-****************************************************************************
-
-    Note:
-    This CPU emulator is very much a work-in-progress.
-
-    DONE:
-    1:  1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
-       11,  ,  ,  ,  ,  ,  ,18,  ,   ,
-
-    TODO:
-    X 1-6 Explore CORE naming scheme.
-    - 1-9 paragraph 1 : memory access timings
-    - 1-9 Data ALU arithmetic operations generally use fractional two's complement arithmetic
-          (Unsigned numbers are only supported by the multiply and multiply-accumulate instruction)
-    - 1-9 For fractional arithmetic, the 31-bit product is added to the 40-bit contents of A or B.  No pipeline!
-    - 1-10 Two types of rounding: convergent rounding and two's complement rounding.  See status register bit R.
-    - 1-10 Logic unit is 16-bits wide and works on MSP portion of accum register
-    - 1-10 The AGU can implement three types of arithmetic: linear, modulo, and reverse carry.
-    - 1-12 "Two external interrupt pins!!!"
-    - 1-12 Take care of all interrupt priority (IPR) stuff!
-    - 1-19 Memory WAIT states
-    - 1-20 The timer's interesting!
-    - 1-21 Vectored exception requests on the Host Interface!
-***************************************************************************/
-
-#include "emu.h"
-#include "dsp56k.h"
-#include "dsp56dsm.h"
-
-#include "opcode.h"
-
-#include "debugger.h"
-
-#include "dsp56def.h"
-
-/***************************************************************************
-    COMPONENT FUNCTIONALITY
-***************************************************************************/
-/* 1-9 ALU */
-// #include "dsp56alu.h"
-
-/* 1-10 Address Generation Unit (AGU) */
-// #include "dsp56agu.h"
-
-/* 1-11 Program Control Unit (PCU) */
-#include "dsp56pcu.h"
-
-/* 5-1 Host Interface (HI) */
-//#include "dsp56hi.h"
-
-/* 4-8 Memory handlers for on-chip peripheral memory. */
-#include "dsp56mem.h"
-
-
-DEFINE_DEVICE_TYPE_NS(DSP56156, DSP56K, dsp56k_device, "dsp56156", "Motorola DSP56156")
-
-
-namespace DSP56K {
-
-enum
-{
-	// PCU
-	DSP56K_PC=1,
-	DSP56K_SR,
-	DSP56K_LC,
-	DSP56K_LA,
-	DSP56K_SP,
-	DSP56K_OMR,
-
-	// ALU
-	DSP56K_X, DSP56K_Y,
-	DSP56K_A, DSP56K_B,
-
-	// AGU
-	DSP56K_R0,DSP56K_R1,DSP56K_R2,DSP56K_R3,
-	DSP56K_N0,DSP56K_N1,DSP56K_N2,DSP56K_N3,
-	DSP56K_M0,DSP56K_M1,DSP56K_M2,DSP56K_M3,
-	DSP56K_TEMP,
-	DSP56K_STATUS,
-
-	// CPU STACK
-	DSP56K_ST0,
-	DSP56K_ST1,
-	DSP56K_ST2,
-	DSP56K_ST3,
-	DSP56K_ST4,
-	DSP56K_ST5,
-	DSP56K_ST6,
-	DSP56K_ST7,
-	DSP56K_ST8,
-	DSP56K_ST9,
-	DSP56K_ST10,
-	DSP56K_ST11,
-	DSP56K_ST12,
-	DSP56K_ST13,
-	DSP56K_ST14,
-	DSP56K_ST15
-};
-
-
-/****************************************************************************
- *  Internal Memory Maps
- ****************************************************************************/
-void dsp56k_device::dsp56156_program_map(address_map &map)
-{
-	map(0x0000, 0x07ff).ram().share("dsk56k_program_ram");   /* 1-5 */
-//  AM_RANGE(0x2f00,0x2fff) AM_ROM                              /* 1-5 PROM reserved memory.  Is this the right spot for it? */
-}
-
-void dsp56k_device::dsp56156_x_data_map(address_map &map)
-{
-	map(0x0000, 0x07ff).ram();                              /* 1-5 */
-	map(0xffc0, 0xffff).rw(FUNC(dsp56k_device::peripheral_register_r), FUNC(dsp56k_device::peripheral_register_w));   /* 1-5 On-chip peripheral registers memory mapped in data space */
-}
-
-
-dsp56k_device::dsp56k_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
-	: cpu_device(mconfig, DSP56156, tag, owner, clock)
-	, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56k_device::dsp56156_program_map), this))
-	, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56k_device::dsp56156_x_data_map), this))
-	, m_program_ram(*this, "dsk56k_program_ram")
-{
-}
-
-device_memory_interface::space_config_vector dsp56k_device::memory_space_config() const
-{
-	return space_config_vector {
-		std::make_pair(AS_PROGRAM, &m_program_config),
-		std::make_pair(AS_DATA,    &m_data_config)
-	};
-}
-
-/***************************************************************************
-    MEMORY ACCESSORS
-***************************************************************************/
-#define ROPCODE(pc)   cpustate->cache->read_word(pc)
-
-
-/***************************************************************************
-    IRQ HANDLING
-***************************************************************************/
-void dsp56k_device::execute_set_input(int irqline, int state)
-{
-	//logerror("DSP56k set irq line %d %d\n", irqline, state);
-
-	switch(irqline)
-	{
-		case DSP56K_IRQ_MODA:
-			// TODO: 1-12 Get this triggering right
-			if (irqa_trigger(&m_dsp56k_core))
-				logerror("DSP56k IRQA is set to fire on the \"Negative Edge\".\n");
-
-			if (state != CLEAR_LINE)
-				m_dsp56k_core.modA_state = true;
-			else
-				m_dsp56k_core.modA_state = false;
-
-			if (m_dsp56k_core.reset_state != true)
-				dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQA");
-			break;
-
-		case DSP56K_IRQ_MODB:
-			// TODO: 1-12 Get this triggering right
-			if (irqb_trigger(&m_dsp56k_core))
-				logerror("DSP56k IRQB is set to fire on the \"Negative Edge\".\n");
-
-			if (state != CLEAR_LINE)
-				m_dsp56k_core.modB_state = true;
-			else
-				m_dsp56k_core.modB_state = false;
-
-			if (m_dsp56k_core.reset_state != true)
-				dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQB");
-			break;
-
-		case DSP56K_IRQ_MODC:
-			if (state != CLEAR_LINE)
-				m_dsp56k_core.modC_state = true;
-			else
-				m_dsp56k_core.modC_state = false;
-
-			// TODO : Set bus mode or whatever
-			break;
-
-		case DSP56K_IRQ_RESET:
-			if (state != CLEAR_LINE)
-				m_dsp56k_core.reset_state = true;
-			else
-			{
-				/* If it changes state from asserted to cleared.  Call the reset function. */
-				if (m_dsp56k_core.reset_state == true)
-					device_reset();
-
-				m_dsp56k_core.reset_state = false;
-			}
-
-			// dsp56k_add_pending_interrupt("Hardware RESET");
-			break;
-
-		default:
-			logerror("DSP56k setting some weird irq line : %d", irqline);
-			break;
-	}
-
-	/* If the reset line isn't asserted, service interrupts */
-	// TODO: Is it right to immediately service interrupts?
-	//if (cpustate->reset_state != true)
-	//  pcu_service_interrupts();
-}
-
-
-/***************************************************************************
-    INITIALIZATION AND SHUTDOWN
-***************************************************************************/
-void dsp56k_device::agu_init()
-{
-	/* save states - dsp56k_agu members */
-	save_item(NAME(m_dsp56k_core.AGU.r0));
-	save_item(NAME(m_dsp56k_core.AGU.r1));
-	save_item(NAME(m_dsp56k_core.AGU.r2));
-	save_item(NAME(m_dsp56k_core.AGU.r3));
-	save_item(NAME(m_dsp56k_core.AGU.n0));
-	save_item(NAME(m_dsp56k_core.AGU.n1));
-	save_item(NAME(m_dsp56k_core.AGU.n2));
-	save_item(NAME(m_dsp56k_core.AGU.n3));
-	save_item(NAME(m_dsp56k_core.AGU.m0));
-	save_item(NAME(m_dsp56k_core.AGU.m1));
-	save_item(NAME(m_dsp56k_core.AGU.m2));
-	save_item(NAME(m_dsp56k_core.AGU.m3));
-	save_item(NAME(m_dsp56k_core.AGU.temp));
-}
-
-void dsp56k_device::alu_init()
-{
-	/* save states - dsp56k_alu members */
-	save_item(NAME(m_dsp56k_core.ALU.x));
-	save_item(NAME(m_dsp56k_core.ALU.y));
-	save_item(NAME(m_dsp56k_core.ALU.a));
-	save_item(NAME(m_dsp56k_core.ALU.b));
-}
-
-void dsp56k_device::device_start()
-{
-	memset(&m_dsp56k_core, 0, sizeof(m_dsp56k_core));
-
-	m_dsp56k_core.device = this;
-	m_dsp56k_core.program_ram = m_program_ram;
-
-	/* Call specific module inits */
-	pcu_init(&m_dsp56k_core, this);
-	agu_init();
-	alu_init();
-
-	/* HACK - You're not in bootstrap mode upon bootup */
-	m_dsp56k_core.bootstrap_mode = BOOTSTRAP_OFF;
-
-	/* Clear the irq states */
-	m_dsp56k_core.modA_state = false;
-	m_dsp56k_core.modB_state = false;
-	m_dsp56k_core.modC_state = false;
-	m_dsp56k_core.reset_state = false;
-
-	/* save states - dsp56k_core members */
-	save_item(NAME(m_dsp56k_core.modA_state));
-	save_item(NAME(m_dsp56k_core.modB_state));
-	save_item(NAME(m_dsp56k_core.modC_state));
-	save_item(NAME(m_dsp56k_core.reset_state));
-	save_item(NAME(m_dsp56k_core.bootstrap_mode));
-	save_item(NAME(m_dsp56k_core.repFlag));
-	save_item(NAME(m_dsp56k_core.repAddr));
-	save_item(NAME(m_dsp56k_core.ppc));
-	save_item(NAME(m_dsp56k_core.op));
-	save_item(NAME(m_dsp56k_core.interrupt_cycles));
-
-	/* save states - dsp56k_host_interface members */
-	save_item(NAME(m_dsp56k_core.HI.icr));
-	save_item(NAME(m_dsp56k_core.HI.cvr));
-	save_item(NAME(m_dsp56k_core.HI.isr));
-	save_item(NAME(m_dsp56k_core.HI.ivr));
-	save_item(NAME(m_dsp56k_core.HI.trxh));
-	save_item(NAME(m_dsp56k_core.HI.trxl));
-	save_item(NAME(m_dsp56k_core.HI.bootstrap_offset));
-
-	save_item(NAME(m_dsp56k_core.peripheral_ram));
-
-	m_dsp56k_core.program = &space(AS_PROGRAM);
-	m_dsp56k_core.cache = m_dsp56k_core.program->cache<1, -1, ENDIANNESS_LITTLE>();
-	m_dsp56k_core.data = &space(AS_DATA);
-
-	state_add(DSP56K_PC,     "PC", m_dsp56k_core.PCU.pc).formatstr("%04X");
-	state_add(DSP56K_SR,     "SR", m_dsp56k_core.PCU.sr).formatstr("%04X");
-	state_add(DSP56K_LC,     "LC", m_dsp56k_core.PCU.lc).formatstr("%04X");
-	state_add(DSP56K_LA,     "LA", m_dsp56k_core.PCU.la).formatstr("%04X");
-	state_add(DSP56K_SP,     "SP", m_dsp56k_core.PCU.sp).formatstr("%02X");
-	state_add(DSP56K_OMR,    "OMR", m_dsp56k_core.PCU.omr).formatstr("%02X");
-
-	state_add(DSP56K_X,      "X", m_dsp56k_core.ALU.x.d).mask(0xffffffff).formatstr("%9s");
-	state_add(DSP56K_Y,      "Y", m_dsp56k_core.ALU.y.d).mask(0xffffffff).formatstr("%9s");
-
-	state_add(DSP56K_A,      "A", m_dsp56k_core.ALU.a.q).mask(u64(0xffffffffffffffffU)).formatstr("%12s"); /* could benefit from a better mask? */
-	state_add(DSP56K_B,      "B", m_dsp56k_core.ALU.b.q).mask(u64(0xffffffffffffffffU)).formatstr("%12s"); /* could benefit from a better mask? */
-
-	state_add(DSP56K_R0,     "R0", m_dsp56k_core.AGU.r0).formatstr("%04X");
-	state_add(DSP56K_R1,     "R1", m_dsp56k_core.AGU.r1).formatstr("%04X");
-	state_add(DSP56K_R2,     "R2", m_dsp56k_core.AGU.r2).formatstr("%04X");
-	state_add(DSP56K_R3,     "R3", m_dsp56k_core.AGU.r3).formatstr("%04X");
-
-	state_add(DSP56K_N0,     "N0", m_dsp56k_core.AGU.n0).formatstr("%04X");
-	state_add(DSP56K_N1,     "N1", m_dsp56k_core.AGU.n1).formatstr("%04X");
-	state_add(DSP56K_N2,     "N2", m_dsp56k_core.AGU.n2).formatstr("%04X");
-	state_add(DSP56K_N3,     "N3", m_dsp56k_core.AGU.n3).formatstr("%04X");
-
-	state_add(DSP56K_M0,     "M0", m_dsp56k_core.AGU.m0).formatstr("%04X");
-	state_add(DSP56K_M1,     "M1", m_dsp56k_core.AGU.m1).formatstr("%04X");
-	state_add(DSP56K_M2,     "M2", m_dsp56k_core.AGU.m2).formatstr("%04X");
-	state_add(DSP56K_M3,     "M3", m_dsp56k_core.AGU.m3).formatstr("%04X");
-
-	state_add(DSP56K_TEMP,   "TMP", m_dsp56k_core.AGU.temp).formatstr("%04X").noshow();
-	//state_add(DSP56K_STATUS, "STS", STATUS).formatstr("%02X");
-
-	state_add(DSP56K_ST0,    "ST0", m_dsp56k_core.PCU.ss[0].d).formatstr("%08X");
-	state_add(DSP56K_ST1,    "ST1", m_dsp56k_core.PCU.ss[1].d).formatstr("%08X");
-	state_add(DSP56K_ST2,    "ST2", m_dsp56k_core.PCU.ss[2].d).formatstr("%08X");
-	state_add(DSP56K_ST3,    "ST3", m_dsp56k_core.PCU.ss[3].d).formatstr("%08X");
-	state_add(DSP56K_ST4,    "ST4", m_dsp56k_core.PCU.ss[4].d).formatstr("%08X");
-	state_add(DSP56K_ST5,    "ST5", m_dsp56k_core.PCU.ss[5].d).formatstr("%08X");
-	state_add(DSP56K_ST6,    "ST6", m_dsp56k_core.PCU.ss[6].d).formatstr("%08X");
-	state_add(DSP56K_ST7,    "ST7", m_dsp56k_core.PCU.ss[7].d).formatstr("%08X");
-	state_add(DSP56K_ST8,    "ST8", m_dsp56k_core.PCU.ss[8].d).formatstr("%08X");
-	state_add(DSP56K_ST9,    "ST9", m_dsp56k_core.PCU.ss[9].d).formatstr("%08X");
-	state_add(DSP56K_ST10,   "ST10", m_dsp56k_core.PCU.ss[10].d).formatstr("%08X");
-	state_add(DSP56K_ST11,   "ST11", m_dsp56k_core.PCU.ss[11].d).formatstr("%08X");
-	state_add(DSP56K_ST12,   "ST12", m_dsp56k_core.PCU.ss[12].d).formatstr("%08X");
-	state_add(DSP56K_ST13,   "ST13", m_dsp56k_core.PCU.ss[13].d).formatstr("%08X");
-	state_add(DSP56K_ST14,   "ST14", m_dsp56k_core.PCU.ss[14].d).formatstr("%08X");
-	state_add(DSP56K_ST15,   "ST15", m_dsp56k_core.PCU.ss[15].d).formatstr("%08X");
-
-	state_add(STATE_GENPC, "GENPC", m_dsp56k_core.PCU.pc).noshow();
-	state_add(STATE_GENPCBASE, "CURPC", m_dsp56k_core.ppc).noshow();
-	state_add(STATE_GENSP, "GENSP", m_dsp56k_core.PCU.sp).noshow();
-	state_add(STATE_GENFLAGS, "GENFLAGS", m_dsp56k_core.PCU.sr).formatstr("%14s").noshow();
-
-	set_icountptr(m_dsp56k_core.icount);
-}
-
-
-void dsp56k_device::state_string_export(const device_state_entry &entry, std::string &str) const
-{
-	const dsp56k_core *cpustate = &m_dsp56k_core;
-
-	switch (entry.index())
-	{
-		case STATE_GENFLAGS:
-			str = string_format("%s%s %s%s%s%s%s%s%s%s %s%s",
-				/* Status Register */
-				LF_bit(cpustate) ? "L" : ".",
-				FV_bit(cpustate) ? "F" : ".",
-
-				S_bit(cpustate) ? "S" : ".",
-				L_bit(cpustate) ? "L" : ".",
-				E_bit(cpustate) ? "E" : ".",
-				U_bit(cpustate) ? "U" : ".",
-				N_bit(cpustate) ? "N" : ".",
-				Z_bit(cpustate) ? "Z" : ".",
-				V_bit(cpustate) ? "V" : ".",
-				C_bit(cpustate) ? "C" : ".",
-
-				/* Stack Pointer */
-				UF_bit(cpustate) ? "U" : ".",
-				SE_bit(cpustate) ? "S" : ".");
-			break;
-
-		case DSP56K_X:
-			str = string_format("%04x %04x", X1, X0);
-			break;
-
-		case DSP56K_Y:
-			str = string_format("%04x %04x", Y1, Y0);
-			break;
-
-		case DSP56K_A:
-			str = string_format("%02x %04x %04x", A2, A1, A0);
-			break;
-
-		case DSP56K_B:
-			str = string_format("%02x %04x %04x", B2, B1, B0);
-			break;
-	}
-}
-
-/***************************************************************************
-    RESET BEHAVIOR
-***************************************************************************/
-static void agu_reset(dsp56k_core* cpustate)
-{
-	/* FM.4-3 */
-	R0 = 0x0000;
-	R1 = 0x0000;
-	R2 = 0x0000;
-	R3 = 0x0000;
-
-	N0 = 0x0000;
-	N1 = 0x0000;
-	N2 = 0x0000;
-	N3 = 0x0000;
-
-	M0 = 0xffff;
-	M1 = 0xffff;
-	M2 = 0xffff;
-	M3 = 0xffff;
-
-	TEMP = 0x0000;
-}
-
-static void alu_reset(dsp56k_core* cpustate)
-{
-	X = 0x00000000;
-	Y = 0x00000000;
-	A = 0x0000000000;
-	B = 0x0000000000;
-}
-
-void dsp56k_device::device_reset()
-{
-	logerror("Dsp56k reset\n");
-
-	m_dsp56k_core.interrupt_cycles = 0;
-
-	m_dsp56k_core.repFlag = 0;
-	m_dsp56k_core.repAddr = 0x0000;
-
-	pcu_reset(&m_dsp56k_core);
-	mem_reset(&m_dsp56k_core);
-	agu_reset(&m_dsp56k_core);
-	alu_reset(&m_dsp56k_core);
-
-	m_dsp56k_core.ppc = m_dsp56k_core.PCU.pc;
-
-	/* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU locked to the instruction at address 0x0000 */
-	m_dsp56k_core.program->write_word(0x0000, 0x0124);
-}
-
-
-
-/***************************************************************************
-    CORE INCLUDE
-***************************************************************************/
-#include "dsp56ops.hxx"
-
-
-/***************************************************************************
-    CORE EXECUTION LOOP
-***************************************************************************/
-// Execute a single opcode and return how many cycles it took.
-static size_t execute_one_new(dsp56k_core* cpustate)
-{
-	// For MAME
-	cpustate->ppc = PC;
-	if (cpustate->device->machine().debug_flags & DEBUG_FLAG_CALL_HOOK) // FIXME: if this was a member, the helper would work
-		cpustate->device->debug()->instruction_hook(PC);
-
-	cpustate->op = ROPCODE(PC);
-	uint16_t w0 = ROPCODE(PC);
-	uint16_t w1 = ROPCODE(PC + 1);
-
-	Opcode op(w0, w1);
-	op.evaluate(cpustate);
-	PC += op.evalSize();    // Special size function needed to handle jmps, etc.
-
-	// TODO: Currently all operations take up 4 cycles (inst->cycles()).
-	return 4;
-}
-
-void dsp56k_device::execute_run()
-{
-	/* If reset line is asserted, do nothing */
-	if (m_dsp56k_core.reset_state)
-	{
-		m_dsp56k_core.icount = 0;
-		return;
-	}
-
-	/* HACK - if you're in bootstrap mode, simply pretend you ate up all your cycles waiting for data. */
-	if (m_dsp56k_core.bootstrap_mode != BOOTSTRAP_OFF)
-	{
-		m_dsp56k_core.icount = 0;
-		return;
-	}
-
-	//m_dsp56k_core.icount -= m_dsp56k_core.interrupt_cycles;
-	//m_dsp56k_core.interrupt_cycles = 0;
-
-	while(m_dsp56k_core.icount > 0)
-	{
-		execute_one(&m_dsp56k_core);
-		if (0) m_dsp56k_core.icount -= execute_one_new(&m_dsp56k_core);
-		pcu_service_interrupts(&m_dsp56k_core);   // TODO: Is it incorrect to service after each instruction?
-	}
-}
-
-
-std::unique_ptr<util::disasm_interface> dsp56k_device::create_disassembler()
-{
-	return std::make_unique<dsp56k_disassembler>();
-}
-
-} // namespace DSP56K
diff --git a/src/devices/cpu/dsp56k/dsp56mem.h b/src/devices/cpu/dsp56k/dsp56mem.h
deleted file mode 100644
index 2ceabc31c1e..00000000000
--- a/src/devices/cpu/dsp56k/dsp56mem.h
+++ /dev/null
@@ -1,241 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Andrew Gardner
-#ifndef MAME_CPU_DSP56K_DSP56MEM_H
-#define MAME_CPU_DSP56K_DSP56MEM_H
-
-#include "dsp56k.h"
-
-namespace DSP56K {
-
-/***************************************************************************
-    MEMORY
-***************************************************************************/
-void mem_reset(dsp56k_core* cpustate);
-
-// Adjusts the documented address to match the offset in peripheral RAM
-#define A2O(a) (a - 0xffc0)
-
-// Adjusts the offset in peripheral RAM to match the documented address
-#define O2A(a) (a + 0xffc0)
-
-// The memory 'registers'
-#define PBC      (cpustate->peripheral_ram[A2O(0xffc0)])
-#define PCC      (cpustate->peripheral_ram[A2O(0xffc1)])
-#define PBDDR    (cpustate->peripheral_ram[A2O(0xffc2)])
-#define PCDDR    (cpustate->peripheral_ram[A2O(0xffc3)])
-#define HCR      (cpustate->peripheral_ram[A2O(0xffc4)])
-#define COCR     (cpustate->peripheral_ram[A2O(0xffc8)])
-#define CRASSI0  (cpustate->peripheral_ram[A2O(0xffd0)])
-#define CRBSSI0  (cpustate->peripheral_ram[A2O(0xffd1)])
-#define CRASSI1  (cpustate->peripheral_ram[A2O(0xffd8)])
-#define CRBSSI1  (cpustate->peripheral_ram[A2O(0xffd9)])
-#define PLCR     (cpustate->peripheral_ram[A2O(0xffdc)])
-#define BCR      (cpustate->peripheral_ram[A2O(0xffde)])
-#define IPR      (cpustate->peripheral_ram[A2O(0xffdf)])
-#define PBD      (cpustate->peripheral_ram[A2O(0xffe2)])
-#define PCD      (cpustate->peripheral_ram[A2O(0xffe3)])
-#define HSR      (cpustate->peripheral_ram[A2O(0xffe4)])
-#define HTXHRX   (cpustate->peripheral_ram[A2O(0xffe5)])
-#define COSR     (cpustate->peripheral_ram[A2O(0xffe8)])
-#define CRXCTX   (cpustate->peripheral_ram[A2O(0xffe9)])
-#define TCR      (cpustate->peripheral_ram[A2O(0xffec)])
-#define TCTR     (cpustate->peripheral_ram[A2O(0xffed)])
-#define TCPR     (cpustate->peripheral_ram[A2O(0xffee)])
-#define TPR      (cpustate->peripheral_ram[A2O(0xffef)])
-#define TSRSSI0  (cpustate->peripheral_ram[A2O(0xfff0)])
-#define TRXSSI0  (cpustate->peripheral_ram[A2O(0xfff1)])
-#define RSMA0    (cpustate->peripheral_ram[A2O(0xfff2)])
-#define RSMB0    (cpustate->peripheral_ram[A2O(0xfff3)])
-#define TSMA0    (cpustate->peripheral_ram[A2O(0xfff4)])
-#define TSMB0    (cpustate->peripheral_ram[A2O(0xfff5)])
-#define TSRSSI1  (cpustate->peripheral_ram[A2O(0xfff8)])
-#define TRXSSI1  (cpustate->peripheral_ram[A2O(0xfff9)])
-#define RSMA1    (cpustate->peripheral_ram[A2O(0xfffa)])
-#define RSMB1    (cpustate->peripheral_ram[A2O(0xfffb)])
-#define TSMA1    (cpustate->peripheral_ram[A2O(0xfffc)])
-#define TSMB1    (cpustate->peripheral_ram[A2O(0xfffd)])
-
-/* Interrupt priority register (IPR) bits */
-void IPR_set(dsp56k_core* cpustate, uint16_t value);
-
-/* A return value of -1 means disabled */
-int8_t irqa_ipl(dsp56k_core* cpustate);
-int8_t irqb_ipl(dsp56k_core* cpustate);
-uint8_t irqa_trigger(dsp56k_core* cpustate);
-uint8_t irqb_trigger(dsp56k_core* cpustate);
-
-int8_t codec_ipl(dsp56k_core* cpustate);
-int8_t host_ipl(dsp56k_core* cpustate);
-int8_t ssi0_ipl(dsp56k_core* cpustate);
-int8_t ssi1_ipl(dsp56k_core* cpustate);
-int8_t tm_ipl(dsp56k_core* cpustate);
-
-
-/***************************************************************************
-    HOST INTERFACE
-***************************************************************************/
-void dsp56k_host_interface_reset(dsp56k_core* cpustate);
-#define HTX (HTXHRX)
-#define HRX (HTXHRX)
-
-#define ICR (cpustate->HI.icr)
-#define CVR (cpustate->HI.cvr)
-#define ISR (cpustate->HI.isr)
-#define IVR (cpustate->HI.ivr)
-#define TXH (cpustate->HI.trxh)
-#define TXL (cpustate->HI.trxl)
-#define RXH (cpustate->HI.trxh)
-#define RXL (cpustate->HI.trxl)
-
-/***************/
-/* DSP56k SIDE */
-/***************/
-/* Host Control Register (HCR) Bits */
-void HCR_set(dsp56k_core* cpustate, uint16_t value);
-
-//uint16_t HF3_bit(dsp56k_core* cpustate);  #define hf3BIT  ((HCR & 0x0010) != 0)
-//uint16_t HF2_bit(dsp56k_core* cpustate);  #define hf2BIT  ((HCR & 0x0008) != 0)
-uint16_t HCIE_bit(dsp56k_core* cpustate);
-uint16_t HTIE_bit(dsp56k_core* cpustate);
-uint16_t HRIE_bit(dsp56k_core* cpustate);
-
-void HF3_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HF2_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HCIE_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HTIE_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HRIE_bit_set(dsp56k_core* cpustate, uint16_t value);
-
-/* Host Status Register (HSR) Bits */
-//void HSR_set(dsp56k_core* cpustate, uint16_t value);
-
-//uint16_t DMA_bit(dsp56k_core* cpustate);  #define dmaBIT  ((HSR & 0x0080) != 0)
-//uint16_t HF1_bit(dsp56k_core* cpustate);  #define hf1BIT  ((HSR & 0x0010) != 0)
-//uint16_t HF0_bit(dsp56k_core* cpustate);  #define hf0BIT  ((HSR & 0x0008) != 0)
-//uint16_t HCP_bit(dsp56k_core* cpustate);  #define hcpBIT  ((HSR & 0x0004) != 0)
-uint16_t HTDE_bit(dsp56k_core* cpustate);
-uint16_t HRDF_bit(dsp56k_core* cpustate);
-
-void DMA_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HF1_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HF0_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HCP_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HTDE_bit_set(dsp56k_core* cpustate, uint16_t value);
-void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value);
-
-/*************/
-/* HOST SIDE */
-/*************/
-/* Interrupt Control Register (ICR) Bits */
-void ICR_set(dsp56k_core* cpustate, uint8_t value);
-
-//uint8_t INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0)
-//uint8_t HM1_bit(dsp56k_core* cpustate);  #define x_hm1BIT  ((dsp56k.HI.ICR & 0x0040) != 0)
-//uint8_t HM0_bit(dsp56k_core* cpustate);  #define x_hm0BIT  ((dsp56k.HI.ICR & 0x0020) != 0)
-//uint8_t HF1_bit_host(dsp56k_core* cpustate);  #define x_hf1BIT  ((dsp56k.HI.ICR & 0x0010) != 0)
-//uint8_t HF0_bit_host(dsp56k_core* cpustate);  #define x_hf0BIT  ((dsp56k.HI.ICR & 0x0008) != 0)
-//uint8_t TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0)
-//uint8_t RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0)
-
-//void INIT_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080))
-//void HM1_bit_set(dsp56k_core* cpustate, uint8_t value);  #define CLEAR_x_hm1BIT()  (dsp56k.HI.ICR &= (~0x0040))
-//void HM0_bit_set(dsp56k_core* cpustate, uint8_t value);  #define CLEAR_x_hm0BIT()  (dsp56k.HI.ICR &= (~0x0020))
-void HF1_bit_host_set(dsp56k_core* cpustate, uint8_t value);
-void HF0_bit_host_set(dsp56k_core* cpustate, uint8_t value);
-void TREQ_bit_set(dsp56k_core* cpustate, uint8_t value);
-void RREQ_bit_set(dsp56k_core* cpustate, uint8_t value);
-
-/* Command Vector Register (CVR) Bits */
-void CVR_set(dsp56k_core* cpustate, uint8_t value);
-
-//uint8_t HC_bit();
-uint8_t HV_bits(dsp56k_core* cpustate);
-
-void HC_bit_set(dsp56k_core* cpustate, uint8_t value);
-void HV_bits_set(dsp56k_core* cpustate, uint8_t value);
-
-/* Interrupt Status Register (ISR) Bits */
-// void ISR_set(dsp56k_core* cpustate, uint8_t value);
-
-//uint8_t HREQ_bit(dsp56k_core* cpustate); #define x_hreqBIT ((dsp56k.HI.ISR & 0x0080) != 0)
-//uint8_t DMA_bit(dsp56k_core* cpustate);  #define x_dmaBIT  ((dsp56k.HI.ISR & 0x0040) != 0)
-//uint8_t HF3_bit_host(dsp56k_core* cpustate);  #define x_hf3BIT  ((dsp56k.HI.ISR & 0x0010) != 0)
-//uint8_t HF2_bit_host(dsp56k_core* cpustate);  #define x_hf2BIT  ((dsp56k.HI.ISR & 0x0008) != 0)
-//uint8_t TRDY_bit(dsp56k_core* cpustate); #define x_trdyBIT ((dsp56k.HI.ISR & 0x0004) != 0)
-uint8_t TXDE_bit(dsp56k_core* cpustate);
-uint8_t RXDF_bit(dsp56k_core* cpustate);
-
-//void HREQ_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_hreqBIT() (dsp56k.HI.ISR &= (~0x0080))
-//void DMA_bit_set(dsp56k_core* cpustate, uint8_t value);  #define CLEAR_x_dmaBIT()  (dsp56k.HI.ISR &= (~0x0040))
-void HF3_bit_host_set(dsp56k_core* cpustate, uint8_t value);
-void HF2_bit_host_set(dsp56k_core* cpustate, uint8_t value);
-//void TRDY_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_trdyBIT() (dsp56k.HI.ISR &= (~0x0004))
-void TXDE_bit_set(dsp56k_core* cpustate, uint8_t value);
-void RXDF_bit_set(dsp56k_core* cpustate, uint8_t value);
-
-/* Interrupt Vector Register (IVR) Bits */
-//void IVR_set(dsp56k_core* cpustate, uint8_t value);
-
-//uint8_t IV7_bit(dsp56k_core* cpustate);
-//uint8_t IV6_bit(dsp56k_core* cpustate);
-//uint8_t IV5_bit(dsp56k_core* cpustate);
-//uint8_t IV4_bit(dsp56k_core* cpustate);
-//uint8_t IV3_bit(dsp56k_core* cpustate);
-//uint8_t IV2_bit(dsp56k_core* cpustate);
-//uint8_t IV1_bit(dsp56k_core* cpustate);
-//uint8_t IV0_bit(dsp56k_core* cpustate);
-
-//void IV7_bit_set(dsp56k_core* cpustate, uint8_t value);
-//void IV6_bit_set(dsp56k_core* cpustate, uint8_t value);
-//void IV5_bit_set(dsp56k_core* cpustate, uint8_t value);
-//void IV4_bit_set(dsp56k_core* cpustate, uint8_t value);
-//void IV3_bit_set(dsp56k_core* cpustate, uint8_t value);
-//void IV2_bit_set(dsp56k_core* cpustate, uint8_t value);
-//void IV1_bit_set(dsp56k_core* cpustate, uint8_t value);
-//void IV0_bit_set(dsp56k_core* cpustate, uint8_t value);
-
-
-/* PROTOTYPES */
-void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate);
-void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate);
-
-
-/***************************************************************************
-    I/O INTERFACE
-***************************************************************************/
-void dsp56k_io_reset(dsp56k_core* cpustate);
-
-/* Port A Bus Control Register (BCR) */
-void BCR_set(dsp56k_core* cpustate, uint16_t value);
-
-//uint16_t RH_bit(dsp56k_core* cpustate);
-//uint16_t BS_bit(dsp56k_core* cpustate);
-//uint16_t external_x_wait_states(dsp56k_core* cpustate);
-//uint16_t external_p_wait_states(dsp56k_core* cpustate);
-
-void RH_bit_set(dsp56k_core* cpustate, uint16_t value);
-void BS_bit_set(dsp56k_core* cpustate, uint16_t value);
-void external_x_wait_states_set(dsp56k_core* cpustate, uint16_t value);
-void external_p_wait_states_set(dsp56k_core* cpustate, uint16_t value);
-
-/* Port B Control Register (PBC) */
-void PBC_set(dsp56k_core* cpustate, uint16_t value);
-//int host_interface_active(dsp56k_core* cpustate);
-
-/* Port B Data Direction Register (PBDDR) */
-void PBDDR_set(dsp56k_core* cpustate, uint16_t value);
-
-/* Port B Data Register (PBD) */
-void PBD_set(dsp56k_core* cpustate, uint16_t value);
-
-/* Port C Control Register (PCC) */
-void PCC_set(dsp56k_core* cpustate, uint16_t value);
-
-/* Port C Data Direction Register (PCDDR) */
-void PCDDR_set(dsp56k_core* cpustate, uint16_t value);
-
-/* Port C Dtaa Register (PCD) */
-void PCD_set(dsp56k_core* cpustate, uint16_t value);
-
-} // namespace DSP56K
-
-#endif // MAME_CPU_DSP56K_DSP56MEM_H
diff --git a/src/devices/cpu/dsp56k/dsp56pcu.h b/src/devices/cpu/dsp56k/dsp56pcu.h
deleted file mode 100644
index 6e640af3839..00000000000
--- a/src/devices/cpu/dsp56k/dsp56pcu.h
+++ /dev/null
@@ -1,150 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Andrew Gardner
-#ifndef __DSP56_PCU_H__
-#define __DSP56_PCU_H__
-
-#include "dsp56k.h"
-
-namespace DSP56K
-{
-/***************************************************************************
-    PCU
-***************************************************************************/
-void pcu_reset(dsp56k_core* cpustate);
-void pcu_init(dsp56k_core* cpustate, device_t *device);
-#define PC  (cpustate->PCU.pc)
-#define LA  (cpustate->PCU.la)
-#define LC  (cpustate->PCU.lc)
-#define SR  (cpustate->PCU.sr)
-#define OMR (cpustate->PCU.omr)
-#define SP  (cpustate->PCU.sp)
-#define SS  (cpustate->PCU.ss)
-
-#define SSH (SS[SP].w.h)
-#define SSL (SS[SP].w.l)
-
-#define ST0     (SS[0].d)
-#define ST1     (SS[1].d)
-#define ST2     (SS[2].d)
-#define ST3     (SS[3].d)
-#define ST4     (SS[4].d)
-#define ST5     (SS[5].d)
-#define ST6     (SS[6].d)
-#define ST7     (SS[7].d)
-#define ST8     (SS[8].d)
-#define ST9     (SS[9].d)
-#define ST10    (SS[10].d)
-#define ST11    (SS[11].d)
-#define ST12    (SS[12].d)
-#define ST13    (SS[13].d)
-#define ST14    (SS[14].d)
-#define ST15    (SS[15].d)
-
-/* STATUS REGISTER (SR) BITS (1-25) */
-/* MR */
-uint8_t LF_bit(const dsp56k_core* cpustate);
-uint8_t FV_bit(const dsp56k_core* cpustate);
-//uint8_t S_bits(const dsp56k_core* cpustate);
-uint8_t I_bits(const dsp56k_core* cpustate);
-
-/* CCR - with macros for easy access */
-#define S() (S_bit(cpustate))
-uint8_t S_bit(const dsp56k_core* cpustate);
-#define L() (L_bit(cpustate))
-uint8_t L_bit(const dsp56k_core* cpustate);
-#define E() (E_bit(cpustate))
-uint8_t E_bit(const dsp56k_core* cpustate);
-#define U() (U_bit(cpustate))
-uint8_t U_bit(const dsp56k_core* cpustate);
-#define N() (N_bit(cpustate))
-uint8_t N_bit(const dsp56k_core* cpustate);
-#define Z() (Z_bit(cpustate))
-uint8_t Z_bit(const dsp56k_core* cpustate);
-#define V() (V_bit(cpustate))
-uint8_t V_bit(const dsp56k_core* cpustate);
-#define C() (C_bit(cpustate))
-uint8_t C_bit(const dsp56k_core* cpustate);
-
-/* MR setters */
-void LF_bit_set(dsp56k_core* cpustate, uint8_t value);
-void FV_bit_set(dsp56k_core* cpustate, uint8_t value);
-void S_bits_set(dsp56k_core* cpustate, uint8_t value);
-void I_bits_set(dsp56k_core* cpustate, uint8_t value);
-
-/* CCR setters - with macros for easy access */
-#define DSP56K_S_SET() (S_bit_set(cpustate, 1))
-#define DSP56K_S_CLEAR() (S_bit_set(cpustate, 0))
-void S_bit_set(dsp56k_core* cpustate, uint8_t value);
-#define DSP56K_L_SET() (L_bit_set(cpustate, 1))
-#define DSP56K_L_CLEAR() (L_bit_set(cpustate, 0))
-void L_bit_set(dsp56k_core* cpustate, uint8_t value);
-#define DSP56K_E_SET() (E_bit_set(cpustate, 1))
-#define DSP56K_E_CLEAR() (E_bit_set(cpustate, 0))
-void E_bit_set(dsp56k_core* cpustate, uint8_t value);
-#define DSP56K_U_SET() (U_bit_set(cpustate, 1))
-#define DSP56K_U_CLEAR() (U_bit_set(cpustate, 0))
-void U_bit_set(dsp56k_core* cpustate, uint8_t value);
-#define DSP56K_N_SET() (N_bit_set(cpustate, 1))
-#define DSP56K_N_CLEAR() (N_bit_set(cpustate, 0))
-void N_bit_set(dsp56k_core* cpustate, uint8_t value);
-#define DSP56K_Z_SET() (Z_bit_set(cpustate, 1))
-#define DSP56K_Z_CLEAR() (Z_bit_set(cpustate, 0))
-void Z_bit_set(dsp56k_core* cpustate, uint8_t value);
-#define DSP56K_V_SET() (V_bit_set(cpustate, 1))
-#define DSP56K_V_CLEAR() (V_bit_set(cpustate, 0))
-void V_bit_set(dsp56k_core* cpustate, uint8_t value);
-#define DSP56K_C_SET() (C_bit_set(cpustate, 1))
-#define DSP56K_C_CLEAR() (C_bit_set(cpustate, 0))
-void C_bit_set(dsp56k_core* cpustate, uint8_t value);
-
-// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here?
-
-
-/* 1-28 OPERATING MODE REGISTER (OMR) BITS */
-//uint8_t CD_bit(const dsp56k_core* cpustate);
-//uint8_t SD_bit(const dsp56k_core* cpustate);
-//uint8_t R_bit(const dsp56k_core* cpustate);
-//uint8_t SA_bit(const dsp56k_core* cpustate);
-//uint8_t MC_bit(const dsp56k_core* cpustate);
-uint8_t MB_bit(const dsp56k_core* cpustate);
-uint8_t MA_bit(const dsp56k_core* cpustate);
-
-void CD_bit_set(dsp56k_core* cpustate, uint8_t value);
-void SD_bit_set(dsp56k_core* cpustate, uint8_t value);
-void R_bit_set(dsp56k_core* cpustate, uint8_t value);
-void SA_bit_set(dsp56k_core* cpustate, uint8_t value);
-void MC_bit_set(dsp56k_core* cpustate, uint8_t value);
-void MB_bit_set(dsp56k_core* cpustate, uint8_t value);
-void MA_bit_set(dsp56k_core* cpustate, uint8_t value);
-
-/* 1-27 STACK POINTER (SP) BITS */
-uint8_t UF_bit(const dsp56k_core* cpustate);
-uint8_t SE_bit(const dsp56k_core* cpustate);
-
-//void UF_bit_set(dsp56k_core* cpustate, uint8_t value) {};
-//void SE_bit_set(dsp56k_core* cpustate, uint8_t value) {};
-
-
-// HACK - Bootstrap modes
-#define BOOTSTRAP_OFF (0)
-#define BOOTSTRAP_SSIX (1)
-#define BOOTSTRAP_HI (2)
-
-
-/* PCU IRQ goodies */
-void pcu_service_interrupts(dsp56k_core* cpustate);
-
-void dsp56k_irq_table_init(void);
-void dsp56k_set_irq_source(uint8_t irq_num, uint16_t iv, const char* source);
-int dsp56k_get_irq_index_by_tag(const char* tag);
-
-void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name);     // Call me to add an interrupt to the queue
-
-void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate);
-int dsp56k_count_pending_interrupts(dsp56k_core* cpustate);
-void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num);
-int8_t dsp56k_get_irq_priority(dsp56k_core* cpustate, int index);
-
-} // namespace DSP56K
-
-#endif
diff --git a/src/mame/drivers/indigo.cpp b/src/mame/drivers/indigo.cpp
index f5ceae47718..af32ece2422 100644
--- a/src/mame/drivers/indigo.cpp
+++ b/src/mame/drivers/indigo.cpp
@@ -16,7 +16,7 @@
 **********************************************************************/
 
 #include "emu.h"
-//#include "cpu/dsp56k/dsp56k.h"
+//#include "cpu/dsp56156/dsp56156.h"
 #include "cpu/mips/mips1.h"
 #include "cpu/mips/mips3.h"
 #include "machine/eepromser.h"
diff --git a/src/mame/drivers/plygonet.cpp b/src/mame/drivers/plygonet.cpp
index 5c86f066355..caba37690bf 100644
--- a/src/mame/drivers/plygonet.cpp
+++ b/src/mame/drivers/plygonet.cpp
@@ -186,16 +186,16 @@ WRITE32_MEMBER(polygonet_state::shared_ram_write)
 			m_maincpu->pc());
 	}
 
-	/* write to the current dsp56k word */
+	/* write to the current DSP word */
 	if (ACCESSING_BITS_16_31)
 	{
-		m_dsp56k_shared_ram_16[(offset<<1)] = (m_shared_ram[offset] & 0xffff0000) >> 16 ;
+		m_dsp56156_shared_ram_16[(offset<<1)] = (m_shared_ram[offset] & 0xffff0000) >> 16 ;
 	}
 
-	/* write to the next dsp56k word */
+	/* write to the next DSP word */
 	if (ACCESSING_BITS_0_15)
 	{
-		m_dsp56k_shared_ram_16[(offset<<1)+1] = (m_shared_ram[offset] & 0x0000ffff) ;
+		m_dsp56156_shared_ram_16[(offset<<1)+1] = (m_shared_ram[offset] & 0x0000ffff) ;
 	}
 }
 
@@ -207,12 +207,12 @@ WRITE32_MEMBER(polygonet_state::dsp_w_lines)
 	if ((data >> 24) & 0x01)
 	{
 //      logerror("RESET CLEARED\n");
-		m_dsp->set_input_line(DSP56K_IRQ_RESET, CLEAR_LINE);
+		m_dsp->set_input_line(DSP56156_IRQ_RESET, CLEAR_LINE);
 	}
 	else
 	{
 //      logerror("RESET ASSERTED\n");
-		m_dsp->set_input_line(DSP56K_IRQ_RESET, ASSERT_LINE);
+		m_dsp->set_input_line(DSP56156_IRQ_RESET, ASSERT_LINE);
 	}
 
 	/* 0x04000000 is the COMBNK line - it switches who has access to the shared RAM - the dsp or the 68020 */
@@ -241,16 +241,16 @@ READ32_MEMBER(polygonet_state::network_r)
 
 
 /**********************************************************************************/
-/*******                            DSP56k maps                             *******/
+/*******                           DSP56156 maps                            *******/
 /**********************************************************************************/
 
 /* It's believed this is hard-wired to return (at least) bit 15 as 0 - causes a host interface bootup */
-READ16_MEMBER(polygonet_state::dsp56k_bootload_r)
+READ16_MEMBER(polygonet_state::dsp56156_bootload_r)
 {
 	return 0x7fff;
 }
 
-/* The dsp56k's Port C Data register (0xffe3) :
+/* The dsp56156's Port C Data register (0xffe3) :
    Program code (function 4e) configures it as general purpose output I/O pins (ffc1 = 0000 & ffc3 = 0fff).
 
    XXXX ---- ---- ----  . Reserved bits
@@ -265,9 +265,9 @@ READ16_MEMBER(polygonet_state::dsp56k_bootload_r)
                                  bit 0002 turns on *just* before this happens.
 */
 
-static uint8_t dsp56k_bank_group(device_t* cpu)
+static uint8_t dsp56156_bank_group(device_t* cpu)
 {
-	uint16_t portC = downcast<dsp56k_device *>(cpu)->get_peripheral_memory(0xffe3);
+	uint16_t portC = downcast<dsp56156_device *>(cpu)->get_peripheral_memory(0xffe3);
 
 	/* If bank group B is on, it overrides bank group A */
 	if (portC & 0x0002)
@@ -278,9 +278,9 @@ static uint8_t dsp56k_bank_group(device_t* cpu)
 	return INVALID_BANK_GROUP;
 }
 
-static uint8_t dsp56k_bank_num(device_t* cpu, uint8_t bank_group)
+static uint8_t dsp56156_bank_num(device_t* cpu, uint8_t bank_group)
 {
-	uint16_t portC = downcast<dsp56k_device *>(cpu)->get_peripheral_memory(0xffe3);
+	uint16_t portC = downcast<dsp56156_device *>(cpu)->get_peripheral_memory(0xffe3);
 
 	if (bank_group == BANK_GROUP_A)
 	{
@@ -296,7 +296,7 @@ static uint8_t dsp56k_bank_num(device_t* cpu, uint8_t bank_group)
 	}
 	else if (bank_group == INVALID_BANK_GROUP)
 	{
-		fatalerror("Plygonet: dsp56k bank num invalid.\n");
+		fatalerror("Plygonet: dsp56156 bank num invalid.\n");
 	}
 
 	return 0;
@@ -304,110 +304,110 @@ static uint8_t dsp56k_bank_num(device_t* cpu, uint8_t bank_group)
 
 
 /* BANK HANDLERS */
-READ16_MEMBER(polygonet_state::dsp56k_ram_bank00_read)
+READ16_MEMBER(polygonet_state::dsp56156_ram_bank00_read)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_bank00_size * 8) + (bank_num * dsp56k_bank00_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_bank00_size * 8) + (bank_num * dsp56156_bank00_size);
 
-	return m_dsp56k_bank00_ram[driver_bank_offset + offset];
+	return m_dsp56156_bank00_ram[driver_bank_offset + offset];
 }
 
-WRITE16_MEMBER(polygonet_state::dsp56k_ram_bank00_write)
+WRITE16_MEMBER(polygonet_state::dsp56156_ram_bank00_write)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_bank00_size * 8) + (bank_num * dsp56k_bank00_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_bank00_size * 8) + (bank_num * dsp56156_bank00_size);
 
-	COMBINE_DATA(&m_dsp56k_bank00_ram[driver_bank_offset + offset]);
+	COMBINE_DATA(&m_dsp56156_bank00_ram[driver_bank_offset + offset]);
 }
 
 
-READ16_MEMBER(polygonet_state::dsp56k_ram_bank01_read)
+READ16_MEMBER(polygonet_state::dsp56156_ram_bank01_read)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_bank01_size * 8) + (bank_num * dsp56k_bank01_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_bank01_size * 8) + (bank_num * dsp56156_bank01_size);
 
-	return m_dsp56k_bank01_ram[driver_bank_offset + offset];
+	return m_dsp56156_bank01_ram[driver_bank_offset + offset];
 }
 
-WRITE16_MEMBER(polygonet_state::dsp56k_ram_bank01_write)
+WRITE16_MEMBER(polygonet_state::dsp56156_ram_bank01_write)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_bank01_size * 8) + (bank_num * dsp56k_bank01_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_bank01_size * 8) + (bank_num * dsp56156_bank01_size);
 
-	COMBINE_DATA(&m_dsp56k_bank01_ram[driver_bank_offset + offset]);
+	COMBINE_DATA(&m_dsp56156_bank01_ram[driver_bank_offset + offset]);
 
 	/* For now, *always* combine P:0x7000-0x7fff with bank01 with no regard to the banking hardware. */
-	m_dsp56k_p_mirror[offset] = data;
+	m_dsp56156_p_mirror[offset] = data;
 }
 
 
-READ16_MEMBER(polygonet_state::dsp56k_ram_bank02_read)
+READ16_MEMBER(polygonet_state::dsp56156_ram_bank02_read)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_bank02_size * 8) + (bank_num * dsp56k_bank02_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_bank02_size * 8) + (bank_num * dsp56156_bank02_size);
 
-	return m_dsp56k_bank02_ram[driver_bank_offset + offset];
+	return m_dsp56156_bank02_ram[driver_bank_offset + offset];
 }
 
-WRITE16_MEMBER(polygonet_state::dsp56k_ram_bank02_write)
+WRITE16_MEMBER(polygonet_state::dsp56156_ram_bank02_write)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_bank02_size * 8) + (bank_num * dsp56k_bank02_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_bank02_size * 8) + (bank_num * dsp56156_bank02_size);
 
-	COMBINE_DATA(&m_dsp56k_bank02_ram[driver_bank_offset + offset]);
+	COMBINE_DATA(&m_dsp56156_bank02_ram[driver_bank_offset + offset]);
 }
 
 
-READ16_MEMBER(polygonet_state::dsp56k_shared_ram_read)
+READ16_MEMBER(polygonet_state::dsp56156_shared_ram_read)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_shared_ram_16_size * 8) + (bank_num * dsp56k_shared_ram_16_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_shared_ram_16_size * 8) + (bank_num * dsp56156_shared_ram_16_size);
 
-	return m_dsp56k_shared_ram_16[driver_bank_offset + offset];
+	return m_dsp56156_shared_ram_16[driver_bank_offset + offset];
 }
 
-WRITE16_MEMBER(polygonet_state::dsp56k_shared_ram_write)
+WRITE16_MEMBER(polygonet_state::dsp56156_shared_ram_write)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_shared_ram_16_size * 8) + (bank_num * dsp56k_shared_ram_16_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_shared_ram_16_size * 8) + (bank_num * dsp56156_shared_ram_16_size);
 
-	COMBINE_DATA(&m_dsp56k_shared_ram_16[driver_bank_offset + offset]);
+	COMBINE_DATA(&m_dsp56156_shared_ram_16[driver_bank_offset + offset]);
 
 	/* Bank group A with offset 0 is believed to be the shared region */
 	if (en_group == BANK_GROUP_A && bank_num == 0)
 	{
 		if (offset % 2)
-			m_shared_ram[offset>>1] = ((m_dsp56k_shared_ram_16[offset-1]) << 16) | m_dsp56k_shared_ram_16[offset];
+			m_shared_ram[offset>>1] = ((m_dsp56156_shared_ram_16[offset-1]) << 16) | m_dsp56156_shared_ram_16[offset];
 		else
-			m_shared_ram[offset>>1] = ((m_dsp56k_shared_ram_16[offset])   << 16) | m_dsp56k_shared_ram_16[offset+1];
+			m_shared_ram[offset>>1] = ((m_dsp56156_shared_ram_16[offset])   << 16) | m_dsp56156_shared_ram_16[offset+1];
 	}
 }
 
 
-READ16_MEMBER(polygonet_state::dsp56k_ram_bank04_read)
+READ16_MEMBER(polygonet_state::dsp56156_ram_bank04_read)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_bank04_size * 8) + (bank_num * dsp56k_bank04_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_bank04_size * 8) + (bank_num * dsp56156_bank04_size);
 
-	return m_dsp56k_bank04_ram[driver_bank_offset + offset];
+	return m_dsp56156_bank04_ram[driver_bank_offset + offset];
 }
 
-WRITE16_MEMBER(polygonet_state::dsp56k_ram_bank04_write)
+WRITE16_MEMBER(polygonet_state::dsp56156_ram_bank04_write)
 {
-	uint8_t en_group = dsp56k_bank_group(m_dsp.target());
-	uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
-	uint32_t driver_bank_offset = (en_group * dsp56k_bank04_size * 8) + (bank_num * dsp56k_bank04_size);
+	uint8_t en_group = dsp56156_bank_group(m_dsp.target());
+	uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
+	uint32_t driver_bank_offset = (en_group * dsp56156_bank04_size * 8) + (bank_num * dsp56156_bank04_size);
 
-	COMBINE_DATA(&m_dsp56k_bank04_ram[driver_bank_offset + offset]);
+	COMBINE_DATA(&m_dsp56156_bank04_ram[driver_bank_offset + offset]);
 }
 
 
@@ -440,19 +440,19 @@ void polygonet_state::main_map(address_map &map)
 
 void polygonet_state::dsp_program_map(address_map &map)
 {
-	map(0x7000, 0x7fff).ram().share("dsp56k_p_mirror"); /* Unsure of size, but 0x1000 matches bank01 */
-	map(0x8000, 0x87ff).ram().share("dsp56k_p_8000");
-	map(0xc000, 0xc000).r(FUNC(polygonet_state::dsp56k_bootload_r));
+	map(0x7000, 0x7fff).ram().share("dsp56156_p_mirror"); /* Unsure of size, but 0x1000 matches bank01 */
+	map(0x8000, 0x87ff).ram().share("dsp56156_p_8000");
+	map(0xc000, 0xc000).r(FUNC(polygonet_state::dsp56156_bootload_r));
 }
 
 void polygonet_state::dsp_data_map(address_map &map)
 {
 	map(0x0800, 0x5fff).ram();      /* Appears to not be affected by banking? */
-	map(0x6000, 0x6fff).rw(FUNC(polygonet_state::dsp56k_ram_bank00_read), FUNC(polygonet_state::dsp56k_ram_bank00_write));
-	map(0x7000, 0x7fff).rw(FUNC(polygonet_state::dsp56k_ram_bank01_read), FUNC(polygonet_state::dsp56k_ram_bank01_write));  /* Mirrored in program space @ 0x7000 */
-	map(0x8000, 0xbfff).rw(FUNC(polygonet_state::dsp56k_ram_bank02_read), FUNC(polygonet_state::dsp56k_ram_bank02_write));
-	map(0xc000, 0xdfff).rw(FUNC(polygonet_state::dsp56k_shared_ram_read), FUNC(polygonet_state::dsp56k_shared_ram_write));
-	map(0xe000, 0xffbf).rw(FUNC(polygonet_state::dsp56k_ram_bank04_read), FUNC(polygonet_state::dsp56k_ram_bank04_write));
+	map(0x6000, 0x6fff).rw(FUNC(polygonet_state::dsp56156_ram_bank00_read), FUNC(polygonet_state::dsp56156_ram_bank00_write));
+	map(0x7000, 0x7fff).rw(FUNC(polygonet_state::dsp56156_ram_bank01_read), FUNC(polygonet_state::dsp56156_ram_bank01_write));  /* Mirrored in program space @ 0x7000 */
+	map(0x8000, 0xbfff).rw(FUNC(polygonet_state::dsp56156_ram_bank02_read), FUNC(polygonet_state::dsp56156_ram_bank02_write));
+	map(0xc000, 0xdfff).rw(FUNC(polygonet_state::dsp56156_shared_ram_read), FUNC(polygonet_state::dsp56156_shared_ram_write));
+	map(0xe000, 0xffbf).rw(FUNC(polygonet_state::dsp56156_ram_bank04_read), FUNC(polygonet_state::dsp56156_ram_bank04_write));
 }
 
 /**********************************************************************************/
@@ -519,9 +519,9 @@ void polygonet_state::machine_reset()
 	m_sound_ctrl = 0;
 
 	/* It's presumed the hardware has hard-wired operating mode 1 (MODA = 1, MODB = 0) */
-	m_dsp->set_input_line(DSP56K_IRQ_RESET, ASSERT_LINE);
-	m_dsp->set_input_line(DSP56K_IRQ_MODA, ASSERT_LINE);
-	m_dsp->set_input_line(DSP56K_IRQ_MODB, CLEAR_LINE);
+	m_dsp->set_input_line(DSP56156_IRQ_RESET, ASSERT_LINE);
+	m_dsp->set_input_line(DSP56156_IRQ_MODA, ASSERT_LINE);
+	m_dsp->set_input_line(DSP56156_IRQ_MODB, CLEAR_LINE);
 }
 
 void polygonet_state::machine_start()
@@ -532,11 +532,11 @@ void polygonet_state::machine_start()
 	m_inputs[3] = ioport("IN3");
 
 	/* save states */
-	save_item(NAME(m_dsp56k_bank00_ram));
-	save_item(NAME(m_dsp56k_bank01_ram));
-	save_item(NAME(m_dsp56k_bank02_ram));
-	save_item(NAME(m_dsp56k_shared_ram_16));
-	save_item(NAME(m_dsp56k_bank04_ram));
+	save_item(NAME(m_dsp56156_bank00_ram));
+	save_item(NAME(m_dsp56156_bank01_ram));
+	save_item(NAME(m_dsp56156_bank02_ram));
+	save_item(NAME(m_dsp56156_shared_ram_16));
+	save_item(NAME(m_dsp56156_bank04_ram));
 	save_item(NAME(m_sys0));
 	save_item(NAME(m_sys1));
 	save_item(NAME(m_sound_ctrl));
@@ -667,12 +667,12 @@ void polygonet_state::init_polygonet()
 {
 	membank("bank1")->configure_entries(0, 8, memregion("audiocpu")->base(), 0x4000);
 
-	/* Allocate space for the dsp56k banking */
-	memset(m_dsp56k_bank00_ram, 0, sizeof(m_dsp56k_bank00_ram));
-	memset(m_dsp56k_bank01_ram, 0, sizeof(m_dsp56k_bank01_ram));
-	memset(m_dsp56k_bank02_ram, 0, sizeof(m_dsp56k_bank02_ram));
-	memset(m_dsp56k_shared_ram_16, 0, sizeof(m_dsp56k_shared_ram_16));
-	memset(m_dsp56k_bank04_ram, 0, sizeof(m_dsp56k_bank04_ram));
+	/* Allocate space for the dsp56156 banking */
+	memset(m_dsp56156_bank00_ram, 0, sizeof(m_dsp56156_bank00_ram));
+	memset(m_dsp56156_bank01_ram, 0, sizeof(m_dsp56156_bank01_ram));
+	memset(m_dsp56156_bank02_ram, 0, sizeof(m_dsp56156_bank02_ram));
+	memset(m_dsp56156_shared_ram_16, 0, sizeof(m_dsp56156_shared_ram_16));
+	memset(m_dsp56156_bank04_ram, 0, sizeof(m_dsp56156_bank04_ram));
 }
 
 
diff --git a/src/mame/includes/plygonet.h b/src/mame/includes/plygonet.h
index 8c5685b0b99..566d6289d03 100644
--- a/src/mame/includes/plygonet.h
+++ b/src/mame/includes/plygonet.h
@@ -8,15 +8,15 @@
 #include "machine/eepromser.h"
 #include "machine/k054321.h"
 #include "video/k053936.h"
-#include "cpu/dsp56k/dsp56k.h"
+#include "cpu/dsp56156/dsp56156.h"
 #include "emupal.h"
 
 
-static const uint16_t dsp56k_bank00_size = 0x1000;
-static const uint16_t dsp56k_bank01_size = 0x1000;
-static const uint16_t dsp56k_bank02_size = 0x4000;
-static const uint16_t dsp56k_shared_ram_16_size = 0x2000;
-static const uint16_t dsp56k_bank04_size = 0x1fc0;
+static const uint16_t dsp56156_bank00_size = 0x1000;
+static const uint16_t dsp56156_bank01_size = 0x1000;
+static const uint16_t dsp56156_bank02_size = 0x4000;
+static const uint16_t dsp56156_shared_ram_16_size = 0x2000;
+static const uint16_t dsp56156_bank04_size = 0x1fc0;
 
 class polygonet_state : public driver_device
 {
@@ -32,8 +32,8 @@ public:
 		m_palette(*this, "palette"),
 		m_k054321(*this, "k054321"),
 		m_shared_ram(*this, "shared_ram"),
-		m_dsp56k_p_mirror(*this, "dsp56k_p_mirror"),
-		m_dsp56k_p_8000(*this, "dsp56k_p_8000")
+		m_dsp56156_p_mirror(*this, "dsp56156_p_mirror"),
+		m_dsp56156_p_8000(*this, "dsp56156_p_8000")
 	{ }
 
 	void plygonet(machine_config &config);
@@ -43,7 +43,7 @@ public:
 private:
 	required_device<cpu_device> m_maincpu;
 	required_device<cpu_device> m_audiocpu;
-	required_device<dsp56k_device> m_dsp;
+	required_device<dsp56156_device> m_dsp;
 	required_device<eeprom_serial_er5911_device> m_eeprom;
 	required_device<k053936_device> m_k053936;
 	required_device<gfxdecode_device> m_gfxdecode;
@@ -53,8 +53,8 @@ private:
 	/* 68k-side shared ram */
 	required_shared_ptr<uint32_t> m_shared_ram;
 
-	required_shared_ptr<uint16_t> m_dsp56k_p_mirror;
-	required_shared_ptr<uint16_t> m_dsp56k_p_8000;
+	required_shared_ptr<uint16_t> m_dsp56156_p_mirror;
+	required_shared_ptr<uint16_t> m_dsp56156_p_8000;
 
 	ioport_port *m_inputs[4];
 	uint8_t m_sys0;
@@ -72,11 +72,11 @@ private:
 	uint8_t m_sound_intck;
 
 	/* memory buffers */
-	uint16_t m_dsp56k_bank00_ram[2 * 8 * dsp56k_bank00_size]; /* 2 bank sets, 8 potential banks each */
-	uint16_t m_dsp56k_bank01_ram[2 * 8 * dsp56k_bank01_size];
-	uint16_t m_dsp56k_bank02_ram[2 * 8 * dsp56k_bank02_size];
-	uint16_t m_dsp56k_shared_ram_16[2 * 8 * dsp56k_shared_ram_16_size];
-	uint16_t m_dsp56k_bank04_ram[2 * 8 * dsp56k_bank04_size];
+	uint16_t m_dsp56156_bank00_ram[2 * 8 * dsp56156_bank00_size]; /* 2 bank sets, 8 potential banks each */
+	uint16_t m_dsp56156_bank01_ram[2 * 8 * dsp56156_bank01_size];
+	uint16_t m_dsp56156_bank02_ram[2 * 8 * dsp56156_bank02_size];
+	uint16_t m_dsp56156_shared_ram_16[2 * 8 * dsp56156_shared_ram_16_size];
+	uint16_t m_dsp56156_bank04_ram[2 * 8 * dsp56156_bank04_size];
 
 	DECLARE_WRITE8_MEMBER(polygonet_sys_w);
 	DECLARE_READ8_MEMBER(polygonet_inputs_r);
@@ -86,17 +86,17 @@ private:
 	DECLARE_WRITE32_MEMBER(dsp_w_lines);
 	DECLARE_WRITE32_MEMBER(dsp_host_interface_w);
 	DECLARE_READ32_MEMBER(network_r);
-	DECLARE_READ16_MEMBER(dsp56k_bootload_r);
-	DECLARE_READ16_MEMBER(dsp56k_ram_bank00_read);
-	DECLARE_WRITE16_MEMBER(dsp56k_ram_bank00_write);
-	DECLARE_READ16_MEMBER(dsp56k_ram_bank01_read);
-	DECLARE_WRITE16_MEMBER(dsp56k_ram_bank01_write);
-	DECLARE_READ16_MEMBER(dsp56k_ram_bank02_read);
-	DECLARE_WRITE16_MEMBER(dsp56k_ram_bank02_write);
-	DECLARE_READ16_MEMBER(dsp56k_shared_ram_read);
-	DECLARE_WRITE16_MEMBER(dsp56k_shared_ram_write);
-	DECLARE_READ16_MEMBER(dsp56k_ram_bank04_read);
-	DECLARE_WRITE16_MEMBER(dsp56k_ram_bank04_write);
+	DECLARE_READ16_MEMBER(dsp56156_bootload_r);
+	DECLARE_READ16_MEMBER(dsp56156_ram_bank00_read);
+	DECLARE_WRITE16_MEMBER(dsp56156_ram_bank00_write);
+	DECLARE_READ16_MEMBER(dsp56156_ram_bank01_read);
+	DECLARE_WRITE16_MEMBER(dsp56156_ram_bank01_write);
+	DECLARE_READ16_MEMBER(dsp56156_ram_bank02_read);
+	DECLARE_WRITE16_MEMBER(dsp56156_ram_bank02_write);
+	DECLARE_READ16_MEMBER(dsp56156_shared_ram_read);
+	DECLARE_WRITE16_MEMBER(dsp56156_shared_ram_write);
+	DECLARE_READ16_MEMBER(dsp56156_ram_bank04_read);
+	DECLARE_WRITE16_MEMBER(dsp56156_ram_bank04_write);
 	DECLARE_WRITE8_MEMBER(sound_ctrl_w);
 	DECLARE_READ32_MEMBER(polygonet_ttl_ram_r);
 	DECLARE_WRITE32_MEMBER(polygonet_ttl_ram_w);