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XaviX logical improvements (nw) (#5244)

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* xavix - change stack behavior slighlty (nw)

* adjust xavix zero page behavior so that opcodes using the zeropage space ignore banks etc. and always read / write to zero page

* kill off some memory access special casing now that the opcodes handle it (nw)
This commit is contained in:
David Haywood 2019-06-16 14:02:06 +01:00 committed by R. Belmont
parent 5cb33d0a7f
commit 45abf5619f
8 changed files with 1040 additions and 298 deletions
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32
src/devices/cpu/m6502/dxavix.lst
View File

@ -1,20 +1,20 @@
# license:BSD-3-Clause
# copyright-holders:David Haywood
# xavix - m6502 with custom opcodes
brk_xav_imp xavora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba
bpl_rel xavora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx
jsr_adr xavand_idx callf_xa3 rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba
bmi_rel xavand_idy kil_non rla_idy nop_zpx and_zpx rol_zpx rla_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx
rti_xav_imp xaveor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba
bvc_rel xaveor_idy kil_non sre_idy nop_zpx eor_zpx lsr_zpx sre_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx
rts_imp xavadc_idx kil_non rra_idx nop_zpg adc_zpg ror_zpg rra_zpg pla_imp adc_imm ror_acc arr_imm jmp_ind adc_aba ror_aba rra_aba
bvs_rel xavadc_idy kil_non rra_idy nop_zpx adc_zpx ror_zpx rra_zpx sei_imp adc_aby nop_imp rra_aby nop_abx adc_abx ror_abx rra_abx
retf_imp xavsta_idx nop_imm sax_idx sty_zpg sta_zpg stx_zpg sax_zpg dey_imp nop_imm txa_imp ane_imm sty_aba sta_aba stx_aba sax_aba
bcc_rel xavsta_idy kil_non sha_idy sty_zpx sta_zpx stx_zpy sax_zpy tya_imp sta_aby txs_imp shs_aby shy_abx sta_abx shx_aby sha_aby
ldy_imm xavlda_idx ldx_imm lax_idx ldy_zpg lda_zpg ldx_zpg lax_zpg tay_imp lda_imm tax_imp lxa_imm ldy_aba lda_aba ldx_aba lax_aba
bcs_rel xavlda_idy kil_non lax_idy ldy_zpx lda_zpx ldx_zpy lax_zpy clv_imp lda_aby tsx_imp las_aby ldy_abx lda_abx ldx_aby lax_aby
cpy_imm xavcmp_idx nop_imm dcp_idx cpy_zpg cmp_zpg dec_zpg dcp_zpg iny_imp cmp_imm dex_imp sbx_imm cpy_aba cmp_aba dec_aba dcp_aba
bne_rel xavcmp_idy kil_non dcp_idy nop_zpx cmp_zpx dec_zpx dcp_zpx cld_imp cmp_aby nop_imp dcp_aby nop_abx cmp_abx dec_abx dcp_abx
cpx_imm xavsbc_idx nop_imm isb_idx cpx_zpg sbc_zpg inc_zpg isb_zpg inx_imp sbc_imm nop_imp sbc_imm cpx_aba sbc_aba inc_aba isb_aba
beq_rel xavsbc_idy kil_non isb_idy nop_zpx sbc_zpx inc_zpx isb_zpx sed_imp sbc_aby nop_imp isb_aby nop_abx sbc_abx inc_abx isb_abx
brk_xav_imp ora_xav_idx kil_non slo_xav_idx nop_xav_zpg ora_xav_zpg asl_xav_zpg slo_xav_zpg php_xav_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba
bpl_rel ora_xav_idy kil_non slo_xav_idy nop_xav_zpx ora_xav_zpx asl_xav_zpx slo_xav_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx
jsr_xav_adr and_xav_idx callf_xa3 rla_xav_idx bit_xav_zpg and_xav_zpg rol_xav_zpg rla_xav_zpg plp_xav_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba
bmi_rel and_xav_idy kil_non rla_xav_idy nop_xav_zpx and_xav_zpx rol_xav_zpx rla_xav_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx
rti_xav_imp eor_xav_idx kil_non sre_xav_idx nop_xav_zpg eor_xav_zpg lsr_xav_zpg sre_xav_zpg pha_xav_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba
bvc_rel eor_xav_idy kil_non sre_xav_idy nop_xav_zpx eor_xav_zpx lsr_xav_zpx sre_xav_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx
rts_xav_imp adc_xav_idx kil_non rra_xav_idx nop_xav_zpg adc_xav_zpg ror_xav_zpg rra_xav_zpg pla_xav_imp adc_imm ror_acc arr_imm jmp_ind adc_aba ror_aba rra_aba
bvs_rel adc_xav_idy kil_non rra_xav_idy nop_xav_zpx adc_xav_zpx ror_xav_zpx rra_xav_zpx sei_imp adc_aby nop_imp rra_aby nop_abx adc_abx ror_abx rra_abx
retf_imp sta_xav_idx nop_imm sax_xav_idx sty_xav_zpg sta_xav_zpg stx_xav_zpg sax_xav_zpg dey_imp nop_imm txa_imp ane_imm sty_aba sta_aba stx_aba sax_aba
bcc_rel sta_xav_idy kil_non sha_xav_idy sty_xav_zpx sta_xav_zpx stx_xav_zpy sax_xav_zpy tya_imp sta_aby txs_imp shs_aby shy_abx sta_abx shx_aby sha_aby
ldy_imm lda_xav_idx ldx_imm lax_xav_idx ldy_xav_zpg lda_xav_zpg ldx_xav_zpg lax_xav_zpg tay_imp lda_imm tax_imp lxa_imm ldy_aba lda_aba ldx_aba lax_aba
bcs_rel lda_xav_idy kil_non lax_xav_idy ldy_xav_zpx lda_xav_zpx ldx_xav_zpy lax_xav_zpy clv_imp lda_aby tsx_imp las_aby ldy_abx lda_abx ldx_aby lax_aby
cpy_imm cmp_xav_idx nop_imm dcp_xav_idx cpy_xav_zpg cmp_xav_zpg dec_xav_zpg dcp_xav_zpg iny_imp cmp_imm dex_imp sbx_imm cpy_aba cmp_aba dec_aba dcp_aba
bne_rel cmp_xav_idy kil_non dcp_xav_idy nop_xav_zpx cmp_xav_zpx dec_xav_zpx dcp_xav_zpx cld_imp cmp_aby nop_imp dcp_aby nop_abx cmp_abx dec_abx dcp_abx
cpx_imm sbc_xav_idx nop_imm isb_xav_idx cpx_xav_zpg sbc_xav_zpg inc_xav_zpg isb_xav_zpg inx_imp sbc_imm nop_imp sbc_imm cpx_aba sbc_aba inc_aba isb_aba
beq_rel sbc_xav_idy kil_non isb_xav_idy nop_xav_zpx sbc_xav_zpx inc_xav_zpx isb_xav_zpx sed_imp sbc_aby nop_imp isb_aby nop_abx sbc_abx inc_abx isb_abx
reset

32
src/devices/cpu/m6502/dxavix2000.lst
View File

@ -1,20 +1,20 @@
# license:BSD-3-Clause
# copyright-holders:David Haywood
# Super XaviX (SSD 2000) - m6502 with custom opcodes
brk_xav_imp xavora_idx cmc_imp oraj_imp asr_zpg ora_zpg asl_zpg orak_imp php_imp ora_imm asl_acc oral_imp asr_aba ora_aba asl_aba oram_imp
bpl_rel xavora_idy phx_imp orapa_imp asr_zpx ora_zpx asl_zpx orapb_imp clc_imp ora_aby asr_acc spa0_imp asr_abx ora_abx asl_abx spb0_imp
jsr_adr xavand_idx callf_xa3 andj_imp bit_zpg and_zpg rol_zpg andk_imp plp_imp and_imm rol_acc andl_imp bit_aba and_aba rol_aba andm_imp
bmi_rel xavand_idy plx_imp andpa_imp bit_zpx and_zpx rol_zpx andpb_imp sec_imp and_aby bit_imm lpa0_imp bit_abx and_abx rol_abx lpb0_imp
rti_xav_imp xaveor_idx nop_imp eorj_imp nop_imp eor_zpg lsr_zpg eork_imp pha_imp eor_imm lsr_acc eorl_imp jmp_adr eor_aba lsr_aba eorm_imp
bvc_rel xaveor_idy phy_imp eorpa_imp nop_imp eor_zpx lsr_zpx eorpb_imp cli_imp eor_aby nop_imp spa1_imp jmp_xa3 eor_abx lsr_abx spb1_imp
rts_imp xavadc_idx nop_imp adcj_imp nop_imp adc_zpg ror_zpg adck_imp pla_imp adc_imm ror_acc adcl_imp jmp_ind adc_aba ror_aba adcm_imp
bvs_rel xavadc_idy ply_imp adcpa_imp nop_imp adc_zpx ror_zpx adcpb_imp sei_imp adc_aby nop_imp lpa1_imp jmpf_ind adc_abx ror_abx lpb1_imp
retf_imp xavsta_idx stz_zpg staj_imp sty_zpg sta_zpg stx_zpg stak_imp dey_imp sev_imp txa_imp stal_imp sty_aba sta_aba stx_aba stam_imp
bcc_rel xavsta_idy stz_aba stapa_imp sty_zpx sta_zpx stx_zpy stapb_imp tya_imp sta_aby txs_imp spa2_imp sty_abx sta_abx stx_aby spb2_imp
ldy_imm xavlda_idx ldx_imm ldaj_imp ldy_zpg lda_zpg ldx_zpg ldak_imp tay_imp lda_imm tax_imp ldal_imp ldy_aba lda_aba ldx_aba ldam_imp
bcs_rel xavlda_idy clr_acc ldapa_imp ldy_zpx lda_zpx ldx_zpy ldapb_imp clv_imp lda_aby tsx_imp lpa2_imp ldy_abx lda_abx ldx_aby lpb2_imp
cpy_imm xavcmp_idx dec_acc cmpj_imp cpy_zpg cmp_zpg dec_zpg cmpk_imp iny_imp cmp_imm dex_imp cmpl_imp cpy_aba cmp_aba dec_aba cmpm_imp
bne_rel xavcmp_idy not_acc cmppa_imp nop_imp cmp_zpx dec_zpx cmppb_imp cld_imp cmp_aby nop_imp decpa_imp nop_imp cmp_abx dec_abx decpb_imp
cpx_imm xavsbc_idx inc_acc sbcj_imp cpx_zpg sbc_zpg inc_zpg sbck_imp inx_imp sbc_imm nop_imp sbcl_imp cpx_aba sbc_aba inc_aba sbcm_imp
beq_rel xavsbc_idy neg_acc sbcpa_imp nop_imp sbc_zpx inc_zpx sbcpb_imp sed_imp sbc_aby nop_imp incpa_imp nop_imp sbc_abx inc_abx incpb_imp
brk_xav_imp ora_xav_idx cmc_imp oraj_imp asr_xav_zpg ora_xav_zpg asl_xav_zpg orak_imp php_xav_imp ora_imm asl_acc oral_imp asr_aba ora_aba asl_aba oram_imp
bpl_rel ora_xav_idy phx_imp orapa_imp asr_xav_zpx ora_xav_zpx asl_xav_zpx orapb_imp clc_imp ora_aby asr_acc spa0_imp asr_abx ora_abx asl_abx spb0_imp
jsr_xav_adr and_xav_idx callf_xa3 andj_imp bit_xav_zpg and_xav_zpg rol_xav_zpg andk_imp plp_xav_imp and_imm rol_acc andl_imp bit_aba and_aba rol_aba andm_imp
bmi_rel and_xav_idy plx_imp andpa_imp bit_xav_zpx and_xav_zpx rol_xav_zpx andpb_imp sec_imp and_aby bit_imm lpa0_imp bit_abx and_abx rol_abx lpb0_imp
rti_xav_imp eor_xav_idx nop_imp eorj_imp nop_imp eor_xav_zpg lsr_xav_zpg eork_imp pha_xav_imp eor_imm lsr_acc eorl_imp jmp_adr eor_aba lsr_aba eorm_imp
bvc_rel eor_xav_idy phy_imp eorpa_imp nop_imp eor_xav_zpx lsr_xav_zpx eorpb_imp cli_imp eor_aby nop_imp spa1_imp jmp_xa3 eor_abx lsr_abx spb1_imp
rts_xav_imp adc_xav_idx nop_imp adcj_imp nop_imp adc_xav_zpg ror_xav_zpg adck_imp pla_xav_imp adc_imm ror_acc adcl_imp jmp_ind adc_aba ror_aba adcm_imp
bvs_rel adc_xav_idy ply_imp adcpa_imp nop_imp adc_xav_zpx ror_xav_zpx adcpb_imp sei_imp adc_aby nop_imp lpa1_imp jmpf_ind adc_abx ror_abx lpb1_imp
retf_imp sta_xav_idx stz_xav_zpg staj_imp sty_xav_zpg sta_xav_zpg stx_xav_zpg stak_imp dey_imp sev_imp txa_imp stal_imp sty_aba sta_aba stx_aba stam_imp
bcc_rel sta_xav_idy stz_aba stapa_imp sty_xav_zpx sta_xav_zpx stx_xav_zpy stapb_imp tya_imp sta_aby txs_imp spa2_imp sty_abx sta_abx stx_aby spb2_imp
ldy_imm lda_xav_idx ldx_imm ldaj_imp ldy_xav_zpg lda_xav_zpg ldx_xav_zpg ldak_imp tay_imp lda_imm tax_imp ldal_imp ldy_aba lda_aba ldx_aba ldam_imp
bcs_rel lda_xav_idy clr_acc ldapa_imp ldy_xav_zpx lda_xav_zpx ldx_xav_zpy ldapb_imp clv_imp lda_aby tsx_imp lpa2_imp ldy_abx lda_abx ldx_aby lpb2_imp
cpy_imm cmp_xav_idx dec_acc cmpj_imp cpy_xav_zpg cmp_xav_zpg dec_xav_zpg cmpk_imp iny_imp cmp_imm dex_imp cmpl_imp cpy_aba cmp_aba dec_aba cmpm_imp
bne_rel cmp_xav_idy not_acc cmppa_imp nop_imp cmp_xav_zpx dec_xav_zpx cmppb_imp cld_imp cmp_aby nop_imp decpa_imp nop_imp cmp_abx dec_abx decpb_imp
cpx_imm sbc_xav_idx inc_acc sbcj_imp cpx_xav_zpg sbc_xav_zpg inc_xav_zpg sbck_imp inx_imp sbc_imm nop_imp sbcl_imp cpx_aba sbc_aba inc_aba sbcm_imp
beq_rel sbc_xav_idy neg_acc sbcpa_imp nop_imp sbc_xav_zpx inc_xav_zpx sbcpb_imp sed_imp sbc_aby nop_imp incpa_imp nop_imp sbc_abx inc_abx incpb_imp
reset

899
src/devices/cpu/m6502/oxavix.lst
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File diff suppressed because it is too large Load Diff

40
src/devices/cpu/m6502/oxavix2000.lst
View File

@ -4,29 +4,29 @@
phy_imp
read_pc_noinc();
write(SP, Y);
write_stack(SP, Y);
dec_SP();
prefetch();
phx_imp
read_pc_noinc();
write(SP, X);
write_stack(SP, X);
dec_SP();
prefetch();
plx_imp
read_pc_noinc();
read(SP);
read_stack(SP);
inc_SP();
X = read(SP);
X = read_stack(SP);
set_nz(X);
prefetch();
ply_imp
read_pc_noinc();
read(SP);
read_stack(SP);
inc_SP();
Y = read(SP);
Y = read_stack(SP);
set_nz(Y);
prefetch();
@ -342,15 +342,15 @@ eorpa_imp
prefetch();
adcpa_imp
do_adc(read_full_data_sp(m_pa));
do_adc(read_full_data(m_pa));
prefetch();
stapa_imp
write_full_data_sp(m_pa, A);
write_full_data(m_pa, A);
prefetch();
ldapa_imp
A = read_full_data_sp(m_pa);
A = read_full_data(m_pa);
set_nz(A);
prefetch();
@ -360,7 +360,7 @@ cmppa_imp
prefetch();
sbcpa_imp
do_sbc(read_full_data_sp(m_pa));
do_sbc(read_full_data(m_pa));
prefetch();
orapb_imp
@ -379,15 +379,15 @@ eorpb_imp
prefetch();
adcpb_imp
do_adc(read_full_data_sp(m_pb));
do_adc(read_full_data(m_pb));
prefetch();
stapb_imp
write_full_data_sp(m_pb, A);
write_full_data(m_pb, A);
prefetch();
ldapb_imp
A = read_full_data_sp(m_pb);
A = read_full_data(m_pb);
set_nz(A);
prefetch();
@ -397,7 +397,7 @@ cmppb_imp
prefetch();
sbcpb_imp
do_sbc(read_full_data_sp(m_pb));
do_sbc(read_full_data(m_pb));
prefetch();
stx_aby
@ -412,9 +412,9 @@ sty_abx
write(TMP+X, Y);
prefetch();
stz_zpg
stz_xav_zpg
TMP = read_pc();
write(TMP, 0x00);
write_zeropage(TMP, 0x00);
prefetch();
stz_aba
@ -423,7 +423,7 @@ stz_aba
write(TMP, 0x00);
prefetch();
bit_zpx
bit_xav_zpx
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
read_pc_noinc();
prefetch();
@ -441,9 +441,9 @@ bit_imm
P |= F_Z;
prefetch();
asr_zpg
asr_xav_zpg
TMP = read_pc(); // TODO: verify this, should it write back or set A?
TMP = read(TMP);
TMP = read_zeropage(TMP);
do_asr(TMP);
prefetch();
@ -456,7 +456,7 @@ asr_aba
write(TMP, TMP2);
prefetch();
asr_zpx
asr_xav_zpx
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
read_pc_noinc();
prefetch();

175
src/devices/cpu/m6502/xavix.cpp
View File

@ -18,9 +18,12 @@
0x0000-0x7fff seems to be a 'low bus' area, it is always the same regardless
of banking
0x8000-0xffff is a banked area with individual code and data banks
0x00ff contains the DATA bank, set manually in code
0x00fe appears to be the current CODE bank, set with either the
custom opcodes, or manually (if running from lowbus only?)
Zero Page notes:
0x00ff contains the DATA bank, set manually in code
0x00fe appears to be the current CODE bank, set with either the
custom opcodes, or manually (if running from lowbus only?)
***************************************************************************/
@ -111,22 +114,7 @@ void xavix_device::device_reset()
m6502_device::device_reset();
}
// used by the xalda_idy ( lda ($**), y )opcodes where databank value is used for high address bits
inline uint8_t xavix_device::read_special(uint16_t adr)
{
return read_full_data_sp(m_databank, adr);
}
// used by DMA and video operations (and custom new opcodes) where full address is specified
uint8_t xavix_device::read_full_data_sp(uint32_t adr)
{
return read_full_data_sp((adr&0xff0000)>>16, adr&0xffff);
}
void xavix_device::write_full_data_sp(uint32_t adr, uint8_t val)
{
write_full_data_sp((adr&0xff0000)>>16, adr&0xffff, val);
}
xavix_device::mi_xavix_normal::mi_xavix_normal(xavix_device *_base)
{
@ -155,7 +143,7 @@ uint8_t xavix_device::read_special_stack()
inline uint8_t xavix_device::read_full_data(uint32_t addr)
uint8_t xavix_device::read_full_data(uint32_t addr)
{
return read_full_data((addr & 0xff0000)>>16, addr & 0xffff);
}
@ -172,58 +160,8 @@ inline uint8_t xavix_device::read_full_data(uint8_t databank, uint16_t adr)
}
else if (adr == 0xff)
{
return databank;
}
return m_lowbus_space->read_byte(adr);
}
else
{
return m_extbus_space->read_byte((databank << 16) | adr);
}
}
else
{
if (adr < 0x8000)
{
if (adr == 0xfe)
{
//logerror("%02x%04x returning codebank\n", m_codebank, PC);
return m_codebank;
}
else if (adr == 0xff)
{
//logerror("%02x%04x returning databank\n", m_codebank, PC);
return databank;
}
if ((adr & 0x7fff) >= 0x200)
{
return m_extbus_space->read_byte((databank << 16) | adr);
}
else
{
//logerror("%02x%04x returning lowbus %04x\n", m_codebank, PC, adr); // useful for debugging opcodes which must ignore lowbus (all indirect ones?)
return m_lowbus_space->read_byte(adr);
}
}
else
{
return m_extbus_space->read_byte((databank << 16) | adr);
}
}
}
inline uint8_t xavix_device::read_full_data_sp(uint8_t databank, uint16_t adr)
{
if (databank < 0x80)
{
if (adr < 0x8000)
{
if (adr == 0xfe)
return m_codebank;
else if (adr == 0xff)
return m_databank;
}
return m_lowbus_space->read_byte(adr);
}
@ -238,7 +176,6 @@ inline uint8_t xavix_device::read_full_data_sp(uint8_t databank, uint16_t adr)
}
}
// data reads
inline uint8_t xavix_device::mi_xavix_normal::read(uint16_t adr)
{
@ -264,6 +201,55 @@ void xavix_device::write_full_data(uint32_t addr, uint8_t val)
write_full_data((addr & 0xff0000)>>16, addr & 0xffff, val);
}
uint8_t xavix_device::read_stack(uint32_t addr)
{
// address is always 0x100-0x1ff
return m_lowbus_space->read_byte((addr & 0xff)+0x100);
}
void xavix_device::write_stack(uint32_t addr, uint8_t val)
{
// address is always 0x100-0x1ff
m_lowbus_space->write_byte((addr & 0xff)+0x100, val);
}
uint8_t xavix_device::read_zeropage(uint32_t addr)
{
// address is always 0x00-0xff
addr &= 0xff;
if (addr == 0xfe)
{
return m_codebank;
}
else if (addr == 0xff)
{
return m_databank;
}
return m_lowbus_space->read_byte(addr);
}
void xavix_device::write_zeropage(uint32_t addr, uint8_t val)
{
// address is always 0x00-0xff
addr &= 0xff;
if (addr == 0xfe)
{
m_codebank = val;
return;
}
else if (addr == 0xff)
{
m_databank = val;
return;
}
m_lowbus_space->write_byte(addr, val);
}
// data writes
inline void xavix_device::write_full_data(uint8_t databank, uint16_t adr, uint8_t val)
{
@ -290,53 +276,6 @@ inline void xavix_device::write_full_data(uint8_t databank, uint16_t adr, uint8_
}
}
else
{
if (adr < 0x8000)
{
if (adr == 0xfe)
{
m_codebank = val;
return;
}
else if (adr == 0xff)
{
m_databank = val;
return;
}
// actually it is more likely that all zero page and stack operations should go through their own handlers, and never reach here
// there is code that explicitly uses pull/push opcodes when in the high banks indicating that the stack area likely isn't
// mapped normally
if ((adr & 0x7fff) >= 0x200)
{
m_extbus_space->write_byte((databank << 16) | adr, val);
}
else
{
m_lowbus_space->write_byte(adr, val);
}
}
else
{
m_extbus_space->write_byte((databank << 16) | adr, val);
}
}
}
inline void xavix_device::write_full_data_sp(uint8_t databank, uint16_t adr, uint8_t val)
{
if (databank < 0x80)
{
if (adr < 0x8000)
{
m_lowbus_space->write_byte(adr, val);
}
else
{
m_extbus_space->write_byte((databank << 16) | adr, val);
}
}
else
{
m_extbus_space->write_byte((databank << 16) | adr, val);
}

136
src/devices/cpu/m6502/xavix.h
View File

@ -29,22 +29,111 @@ public:
O(brk_xav_imp);
O(rti_xav_imp);
O(xavora_idx);
O(xavora_idy);
O(xavand_idx);
O(xavand_idy);
O(xaveor_idx);
O(xaveor_idy);
O(xavadc_idx);
O(xavadc_idy);
O(xavsta_idx);
O(xavsta_idy);
O(xavlda_idx);
O(xavlda_idy);
O(xavcmp_idx);
O(xavcmp_idy);
O(xavsbc_idx);
O(xavsbc_idy);
O(ora_xav_idx);
O(ora_xav_idy);
O(and_xav_idx);
O(and_xav_idy);
O(eor_xav_idx);
O(eor_xav_idy);
O(adc_xav_idx);
O(adc_xav_idy);
O(sta_xav_idx);
O(sta_xav_idy);
O(lda_xav_idx);
O(lda_xav_idy);
O(cmp_xav_idx);
O(cmp_xav_idy);
O(sbc_xav_idx);
O(sbc_xav_idy);
O(plp_xav_imp);
O(pla_xav_imp);
O(php_xav_imp);
O(pha_xav_imp);
O(jsr_xav_adr);
O(rts_xav_imp);
O(adc_xav_zpg);
O(and_xav_zpg);
O(asl_xav_zpg);
O(bit_xav_zpg);
O(cmp_xav_zpg);
O(cpx_xav_zpg);
O(cpy_xav_zpg);
O(dec_xav_zpg);
O(eor_xav_zpg);
O(inc_xav_zpg);
O(lda_xav_zpg);
O(ldx_xav_zpg);
O(ldy_xav_zpg);
O(lsr_xav_zpg);
O(ora_xav_zpg);
O(rol_xav_zpg);
O(ror_xav_zpg);
O(sbc_xav_zpg);
O(sta_xav_zpg);
O(stx_xav_zpg);
O(sty_xav_zpg);
O(dcp_xav_zpg);
O(isb_xav_zpg);
O(lax_xav_zpg);
O(rla_xav_zpg);
O(rra_xav_zpg);
O(sax_xav_zpg);
O(slo_xav_zpg);
O(sre_xav_zpg);
O(nop_xav_zpg);
O(ldx_xav_zpy);
O(stx_xav_zpy);
O(lax_xav_zpy);
O(sax_xav_zpy);
O(adc_xav_zpx);
O(and_xav_zpx);
O(asl_xav_zpx);
O(cmp_xav_zpx);
O(dec_xav_zpx);
O(eor_xav_zpx);
O(inc_xav_zpx);
O(lda_xav_zpx);
O(ldy_xav_zpx);
O(lsr_xav_zpx);
O(ora_xav_zpx);
O(rol_xav_zpx);
O(ror_xav_zpx);
O(sbc_xav_zpx);
O(sta_xav_zpx);
O(sty_xav_zpx);
O(dcp_xav_zpx);
O(isb_xav_zpx);
O(rla_xav_zpx);
O(rra_xav_zpx);
O(slo_xav_zpx);
O(sre_xav_zpx);
O(nop_xav_zpx);
O(slo_xav_idx);
O(rla_xav_idx);
O(sre_xav_idx);
O(rra_xav_idx);
O(sax_xav_idx);
O(lax_xav_idx);
O(dcp_xav_idx);
O(isb_xav_idx);
O(slo_xav_idy);
O(rla_xav_idy);
O(sre_xav_idy);
O(rra_xav_idy);
O(sha_xav_idy);
O(lax_xav_idy);
O(dcp_xav_idy);
O(isb_xav_idy);
typedef device_delegate<int16_t (int which, int half)> xavix_interrupt_vector_delegate;
@ -68,12 +157,6 @@ public:
void write_full_data(uint8_t databank, uint16_t adr, uint8_t val);
void write_full_data(uint32_t addr, uint8_t val);
// used for opcodes etc. that can't see certain things in banks > 0x80
uint8_t read_full_data_sp(uint8_t databank, uint16_t adr);
uint8_t read_full_data_sp(uint32_t adr);
void write_full_data_sp(uint8_t databank, uint16_t adr, uint8_t val);
void write_full_data_sp(uint32_t adr, uint8_t val);
protected:
class mi_xavix_normal : public memory_interface {
public:
@ -121,8 +204,6 @@ protected:
address_space *m_lowbus_space;
address_space *m_extbus_space;
uint8_t read_special(uint16_t adr);
protected:
xavix_interrupt_vector_delegate m_vector_callback;
@ -143,6 +224,13 @@ protected:
need further research */
uint8_t m_special_stack[0x100];
uint8_t m_special_stackpos;
uint8_t read_stack(uint32_t addr);
void write_stack(uint32_t addr, uint8_t val);
uint8_t read_zeropage(uint32_t addr);
void write_zeropage(uint32_t addr, uint8_t val);
};
enum {

8
src/devices/cpu/m6502/xavix2000.h
View File

@ -124,15 +124,15 @@ protected:
O(sty_abx);
O(stz_aba);
O(stz_zpg);
O(stz_xav_zpg);
O(bit_zpx);
O(bit_xav_zpx);
O(bit_abx);
O(bit_imm);
O(asr_zpg);
O(asr_xav_zpg);
O(asr_aba);
O(asr_zpx);
O(asr_xav_zpx);
O(asr_acc);
O(asr_abx);

16
src/mame/drivers/xavix.cpp
View File

@ -2036,16 +2036,16 @@ ROM_START( ban_onep )
ROM_LOAD("onepiece.bin", 0x000000, 0x800000, CRC(c5cb5a5f) SHA1(db85f6cc48d77c5a4967b9b8e2999167e3dfc8c8) )
ROM_END
CONS( 2002, epo_ebox, 0, 0, xavix2000_nv, epo_epp, xavix_state, init_xavix, "Epoch / SSD Company LTD", "Excite Boxing (Japan)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND ) // doesn't use XaviX2000 extra opcodes, but had that type of CPU
CONS( 2004, epo_sdb, 0, 0, xavix2000_nv_sdb, epo_sdb, xavix_2000_nv_sdb_state, init_xavix, "Epoch / SSD Company LTD", "Super Dash Ball (Japan)", MACHINE_IMPERFECT_SOUND )
CONS( 2002, epo_ebox, 0, 0, xavix2000_nv, epo_epp, xavix_state, init_xavix, "Epoch / SSD Company LTD", "Excite Boxing (Japan)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND ) // doesn't use XaviX2000 extra opcodes, but had that type of CPU
CONS( 2004, epo_sdb, 0, 0, xavix2000_nv_sdb, epo_sdb, xavix_2000_nv_sdb_state, init_xavix, "Epoch / SSD Company LTD", "Super Dash Ball (Japan)", MACHINE_IMPERFECT_SOUND )
CONS( 2005, ttv_sw, 0, 0, xavix2000_i2c_24c02, ttv_lotr, xavix_i2c_lotr_state, init_xavix, "Tiger / SSD Company LTD", "Star Wars Saga Edition - Lightsaber Battle Game", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND )
CONS( 2005, ttv_lotr, 0, 0, xavix2000_i2c_24c02, ttv_lotr, xavix_i2c_lotr_state, init_xavix, "Tiger / SSD Company LTD", "Lord Of The Rings - Warrior of Middle-Earth", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND )
CONS( 2005, ttv_mx, 0, 0, xavix2000_i2c_24c04, ttv_mx, xavix_i2c_state, init_xavix, "Tiger / SSD Company LTD", "MX Dirt Rebel", MACHINE_IMPERFECT_SOUND )
CONS( 2003, drgqst, 0, 0, xavix2000_i2c_24c02, ttv_lotr, xavix_i2c_lotr_state, init_xavix, "Square Enix / SSD Company LTD", "Kenshin Dragon Quest: Yomigaerishi Densetsu no Ken", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND )
CONS( 2005, ttv_sw, 0, 0, xavix2000_i2c_24c02, ttv_lotr, xavix_i2c_lotr_state, init_xavix, "Tiger / SSD Company LTD", "Star Wars Saga Edition - Lightsaber Battle Game", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND )
CONS( 2005, ttv_lotr, 0, 0, xavix2000_i2c_24c02, ttv_lotr, xavix_i2c_lotr_state, init_xavix, "Tiger / SSD Company LTD", "Lord Of The Rings - Warrior of Middle-Earth", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND )
CONS( 2005, ttv_mx, 0, 0, xavix2000_i2c_24c04, ttv_mx, xavix_i2c_state, init_xavix, "Tiger / SSD Company LTD", "MX Dirt Rebel", MACHINE_IMPERFECT_SOUND )
CONS( 2003, drgqst, 0, 0, xavix2000_i2c_24c02, ttv_lotr, xavix_i2c_lotr_state, init_xavix, "Square Enix / SSD Company LTD", "Kenshin Dragon Quest: Yomigaerishi Densetsu no Ken", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND )
// hangs after starting a game, or after quite a long time in attract mode (first problem could be bad save data read with the eeprom code, 2nd problem might just be how it is, ends up in a dead loop, not executing invalid code)
CONS( 2004, ban_onep, 0, 0, xavix2000_i2c_24c04, ttv_lotr, xavix_i2c_lotr_state, init_xavix, "Bandai / SSD Company LTD", "One Piece Punch Battle (Japan)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND )
// hangs after starting a game, or after quite a long time in attract mode (first problem could be bad save data read with the eeprom code, 2nd problem might just be how it is, ends up in a dead loop, not executing invalid code, idle timeout / battery saver)
CONS( 2004, ban_onep, 0, 0, xavix2000_i2c_24c04, ttv_lotr, xavix_i2c_lotr_state, init_xavix, "Bandai / SSD Company LTD", "One Piece Punch Battle (Japan)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND )
/* SuperXaviX (XaviX 2002 type CPU) hardware titles (3rd XaviX generation?)