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This commit is contained in:
Michaël Banaan Ananas 2011-02-09 21:22:18 +00:00
parent e5a30e7eae
commit 45e080abeb
5 changed files with 10 additions and 10 deletions
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2
src/emu/cpu/mn10200/mn10200.c
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@ -1923,7 +1923,7 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
case 0x181: case 0x191: { case 0x181: case 0x191: {
int ser = (adr-0x180) >> 4; int ser = (adr-0x180) >> 4;
mn102->serial[ser].ctrlh = data; mn102->serial[ser].ctrlh = data;
// log_event("MN102", "Serial %d transmit=%s, recieve=%s, break=%s, proto=%s, order=%s", // log_event("MN102", "Serial %d transmit=%s, receive=%s, break=%s, proto=%s, order=%s",
// ser, // ser,
// data & 0x80 ? "on" : "off", data & 0x40 ? "on" : "off", // data & 0x80 ? "on" : "off", data & 0x40 ? "on" : "off",
// data & 0x20 ? "on" : "off", data & 8 ? "sync" : "async", // data & 0x20 ? "on" : "off", data & 8 ? "sync" : "async",

2
src/emu/cpu/tms32025/tms32025.c
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@ -1895,7 +1895,7 @@ static int process_IRQs(tms32025_state *cpustate)
return cpustate->tms32025_irq_cycles; return cpustate->tms32025_irq_cycles;
} }
if ((cpustate->IFR & 0x10) && (IMR & 0x10)) { /* Serial port receive IRQ (internal) */ if ((cpustate->IFR & 0x10) && (IMR & 0x10)) { /* Serial port receive IRQ (internal) */
// logerror("TMS32025: Active RINT (Serial recieve)\n"); // logerror("TMS32025: Active RINT (Serial receive)\n");
DRR = S_IN(TMS32025_DR); DRR = S_IN(TMS32025_DR);
SET_PC(0x001A); SET_PC(0x001A);
cpustate->idle = 0; cpustate->idle = 0;

12
src/emu/machine/68681.c
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@ -113,14 +113,14 @@ static void duart68681_update_interrupts(duart68681_state *duart68681)
SRn: bits 7-4: handled elsewhere. SRn: bits 7-4: handled elsewhere.
SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined) SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined)
SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well) SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well)
SRn: bit 1 (FFULLn) (this bit we actually emulate; if the recieve fifo for channel n is full, this bit is 1, otherwise it is 0. the recieve fifo should be three words long.) SRn: bit 1 (FFULLn) (this bit we actually emulate; if the receive fifo for channel n is full, this bit is 1, otherwise it is 0. the receive fifo should be three words long.)
SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the recieve fifo is not empty) SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the receive fifo is not empty)
ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler
ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data recieve handler ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data receive handler
ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively
ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2 ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2
ISR: bit 3: Counter ready; this should be handled by the timer generator ISR: bit 3: Counter ready; this should be handled by the timer generator
ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data recieve handler ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data receive handler
ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively
ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2 ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2
*/ */
@ -200,7 +200,7 @@ static void duart68681_update_interrupts(duart68681_state *duart68681)
else else
duart68681->ISR &= ~INT_TXRDYB; duart68681->ISR &= ~INT_TXRDYB;
} }
//logerror("DEBUG: 68681 int check: before reciever test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR); //logerror("DEBUG: 68681 int check: before receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
if ( duart68681->channel[ch].MR1 & MODE_RX_INT_SELECT_BIT ) if ( duart68681->channel[ch].MR1 & MODE_RX_INT_SELECT_BIT )
{ {
if ( duart68681->channel[ch].SR & STATUS_FIFO_FULL ) if ( duart68681->channel[ch].SR & STATUS_FIFO_FULL )
@ -223,7 +223,7 @@ static void duart68681_update_interrupts(duart68681_state *duart68681)
duart68681->ISR &= ((ch == 0) ? ~INT_RXRDY_FFULLA : ~INT_RXRDY_FFULLB); duart68681->ISR &= ((ch == 0) ? ~INT_RXRDY_FFULLA : ~INT_RXRDY_FFULLB);
} }
} }
//logerror("DEBUG: 68681 int check: after reciever test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR); //logerror("DEBUG: 68681 int check: after receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
} }
if ( (duart68681->ISR & duart68681->IMR) != 0 ) if ( (duart68681->ISR & duart68681->IMR) != 0 )
{ {

2
src/mame/video/dc.c
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@ -1439,7 +1439,7 @@ static void process_ta_fifo(running_machine* machine)
mame_printf_verbose("\n"); mame_printf_verbose("\n");
#endif #endif
// set type of list currently being recieved // set type of list currently being received
if ((state_ta.paratype == 4) || (state_ta.paratype == 5) || (state_ta.paratype == 6)) if ((state_ta.paratype == 4) || (state_ta.paratype == 5) || (state_ta.paratype == 6))
{ {
if (state_ta.tafifo_listtype < 0) if (state_ta.tafifo_listtype < 0)

2
src/osd/windows/input.c
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@ -1692,7 +1692,7 @@ static void rawinput_init(running_machine *machine)
rawinput_mouse_enum(machine, device); rawinput_mouse_enum(machine, device);
} }
// finally, register to recieve raw input WM_INPUT messages // finally, register to receive raw input WM_INPUT messages
regcount = 0; regcount = 0;
if (keyboard_list != NULL) if (keyboard_list != NULL)
{ {