mirror of
https://github.com/holub/mame
synced 2025-04-21 07:52:35 +03:00
Implemented a few SysCtrl, Maple, and PVR/HOLLY bits for Naomi. The BIOS gets slightly further but is nowhere near starting up.
This commit is contained in:
R. Belmont
parent
fc148a8f56
commit
45f85e2677
@ -28,6 +28,8 @@ WRITE64_HANDLER( dc_aica_reg_w );
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MACHINE_RESET( dc );
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void dc_vblank( void );
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/*----------- defined in video/dc.c -----------*/
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READ64_HANDLER( pvr_ctrl_r );
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@ -4,27 +4,189 @@
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*/
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#include "mamecore.h"
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#include "driver.h"
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#include "dc.h"
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#define DEBUG_REGISTERS (1)
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#if DEBUG_REGISTERS
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#define DEBUG_SYSCTRL (1)
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#define DEBUG_MAPLE (0)
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#if DEBUG_SYSCTRL
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static const char *sysctrl_names[] =
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{
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"CH2 DMA dest",
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"CH2 DMA length",
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"CH2 DMA start",
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"5f680c",
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"Sort DMA start link table addr",
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"Sort DMA link base addr",
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"Sort DMA link address bit width",
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"Sort DMA link address shift control",
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"Sort DMA start",
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"5f6824", "5f6828", "5f682c", "5f6830",
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"5f6834", "5f6838", "5f683c",
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"DBREQ # signal mask control",
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"BAVL # signal wait count",
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"DMA priority count",
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"CH2 DMA max burst length",
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"5f6850", "5f6854", "5f6858", "5f685c",
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"5f6860", "5f6864", "5f6868", "5f686c",
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"5f6870", "5f6874", "5f6878", "5f687c",
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"TA FIFO remaining",
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"TA texture memory bus select 0",
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"TA texture memory bus select 1",
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"FIFO status",
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"System reset", "5f6894", "5f6898",
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"System bus version",
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"SH4 root bus split enable",
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"5f68a4", "5f68a8", "5f68ac",
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"5f68b0", "5f68b4", "5f68b8", "5f68bc",
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"5f68c0", "5f68c4", "5f68c8", "5f68cc",
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"5f68d0", "5f68d4", "5f68d8", "5f68dc",
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"5f68e0", "5f68e4", "5f68e8", "5f68ec",
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"5f68f0", "5f68f4", "5f68f8", "5f68fc",
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"Normal IRQ status",
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"External IRQ status",
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"Error IRQ status", "5f690c",
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"Level 2 normal IRQ mask",
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"Level 2 external IRQ mask",
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"Level 2 error IRQ mask", "5f691c",
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"Level 4 normal IRQ mask",
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"Level 4 external IRQ mask",
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"Level 4 error IRQ mask", "5f692c",
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"Level 6 normal IRQ mask",
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"Level 6 external IRQ mask",
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"Level 6 error IRQ mask", "5f693c",
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"Normal IRQ PVR-DMA startup mask",
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"External IRQ PVR-DMA startup mask",
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"5f6948", "5f694c",
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"Normal IRQ G2-DMA startup mask",
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"External IRQ G2-DMA startup mask"
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};
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#endif
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#if DEBUG_MAPLE
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static const char *maple_names[] =
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{
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"5f6c00",
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"DMA command table addr",
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"5f6c08", "5f6c0c",
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"DMA trigger select",
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"DMA enable",
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"DMA start", "5f6c1c",
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"5f6c20", "5f6c24", "5f6c28", "5f6c2c",
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"5f6c30", "5f6c34", "5f6c38", "5f6c3c",
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"5f6c40", "5f6c44", "5f6c48", "5f6c4c",
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"5f6c50", "5f6c54", "5f6c58", "5f6c5c",
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"5f6c60", "5f6c64", "5f6c68", "5f6c6c",
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"5f6c70", "5f6c74", "5f6c78", "5f6c7c",
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"System control",
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"Status",
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"DMA hard trigger clear",
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"DMA address range",
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"5f6c90", "5f6c94", "5f6c98", "5f6c9c",
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"5f6ca0", "5f6ca4", "5f6ca8", "5f6cac",
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"5f6cb0", "5f6cb4", "5f6cb8", "5f6cbc",
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"5f6cc0", "5f6cc4", "5f6cc8", "5f6ccc",
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"5f6cd0", "5f6cd4", "5f6cd8", "5f6cdc",
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"5f6ce0", "5f6ce4",
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"MSB select", "5f6cec", "5f6cf0",
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"Txd address counter",
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"Rxd address counter",
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"Rxd base address"
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};
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#endif
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#endif
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// selected Maple registers
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enum
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{
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MAPLE_DMACMD = 1,
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MAPLE_DMATRIGGERSEL = 4,
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MAPLE_DMAENABLE = 5,
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MAPLE_DMASTART = 6,
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MAPLE_SYSCTRL = 0x20,
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MAPLE_STATUS = 0x21,
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};
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static UINT32 sysctrl_regs[0x200/4];
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static UINT32 maple_regs[0x100/4];
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// register decode helper
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INLINE int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
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{
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int reg = offset * 2;
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*shift = 0;
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if (mem_mask == U64(0x00000000ffffffff))
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{
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reg++;
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*shift = 32;
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}
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return reg;
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}
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// I/O functions
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READ64_HANDLER( dc_sysctrl_r )
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{
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return 0;
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int reg;
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UINT64 shift;
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reg = decode_reg_64(offset, mem_mask, &shift);
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#if DEBUG_SYSCTRL
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mame_printf_verbose("SYSCTRL: read %x @ %x (reg %x: %s), mask %llx (PC=%x)\n", sysctrl_regs[reg], offset, reg, sysctrl_names[reg], mem_mask, activecpu_get_pc());
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#endif
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return (UINT64)sysctrl_regs[reg] << shift;
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}
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WRITE64_HANDLER( dc_sysctrl_w )
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{
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mame_printf_verbose("SYSCTRL: write %llx to %x, mask %llx\n", data, offset, mem_mask);
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int reg;
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UINT64 shift;
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reg = decode_reg_64(offset, mem_mask, &shift);
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#if DEBUG_SYSCTRL
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mame_printf_verbose("SYSCTRL: write %llx to %x (reg %x: %s), mask %llx\n", data>>shift, offset, reg, sysctrl_names[reg], mem_mask);
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#endif
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sysctrl_regs[reg] |= data >> shift;
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}
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READ64_HANDLER( dc_maple_r )
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{
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return 0;
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int reg;
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UINT64 shift;
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reg = decode_reg_64(offset, mem_mask, &shift);
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return (UINT64)maple_regs[reg] << shift;
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}
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WRITE64_HANDLER( dc_maple_w )
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{
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mame_printf_verbose("MAPLE: write %llx to %x, mask %llx\n", data, offset, mem_mask);
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int reg;
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UINT64 shift;
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reg = decode_reg_64(offset, mem_mask, &shift);
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#if DEBUG_MAPLE
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mame_printf_verbose("MAPLE: write %llx to %x (reg %x: %s), mask %llx\n", data >> shift, offset, reg, maple_names[reg], mem_mask);
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#endif
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maple_regs[reg] |= data >> shift;
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}
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READ64_HANDLER( dc_gdrom_r )
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@ -77,12 +239,6 @@ WRITE64_HANDLER( dc_rtc_w )
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mame_printf_verbose("RTC: write %llx to %x, mask %llx\n", data, offset, mem_mask);
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}
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MACHINE_RESET( dc )
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{
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/* halt the ARM7 */
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cpunum_set_input_line(1, INPUT_LINE_RESET, ASSERT_LINE);
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}
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READ64_HANDLER( dc_aica_reg_r )
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{
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return 0;
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@ -93,3 +249,62 @@ WRITE64_HANDLER( dc_aica_reg_w )
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mame_printf_verbose("AICA REG: write %llx to %x, mask %llx\n", data, offset, mem_mask);
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}
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MACHINE_RESET( dc )
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{
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/* halt the ARM7 */
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cpunum_set_input_line(1, INPUT_LINE_RESET, ASSERT_LINE);
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memset(sysctrl_regs, 0, sizeof(sysctrl_regs));
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memset(maple_regs, 0, sizeof(maple_regs));
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sysctrl_regs[0x27] = 0x00000008; // Naomi BIOS requires at least this version
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}
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// called at vblank
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void dc_vblank( void )
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{
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// is system control set for automatic polling on VBL?
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if ((maple_regs[MAPLE_SYSCTRL] & 0xffff0000) == 0x3a980000)
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{
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// is enabled?
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if (maple_regs[MAPLE_DMAENABLE] == 1)
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{
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// is started?
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if (maple_regs[MAPLE_DMASTART] == 1)
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{
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UINT32 cmd, dest, addr = maple_regs[MAPLE_DMACMD];
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// process the command list
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// first word: bit 31 set = last command in list, 16-17 = port, 8-10 = pattern, 0-7 = xfer length
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// second word: destination address
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// third word: what to send to port A
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cmd = 0;
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while (!(cmd & 0x80000000))
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{
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// read command word
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cmd = program_read_dword(addr);
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dest = program_read_dword(addr+4);
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// just indicate "no connection" for now
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program_write_dword(dest, 0);
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program_write_dword(dest+4, 0xffffffff);
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// skip fixed packet header
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addr += 8;
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// skip transfer data
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addr += ((cmd & 0xff) + 1) * 4;
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}
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#if DEBUG_MAPLE
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mame_printf_verbose("MAPLE: automatic read, table @ %x\n", addr);
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#endif
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// indicate transfer completed
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maple_regs[MAPLE_DMASTART] = 0;
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}
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}
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}
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}
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@ -6,33 +6,99 @@
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#include "driver.h"
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#include "dc.h"
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#define DEBUG_PVRCTRL (1)
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#define DEBUG_PVRTA (1)
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static UINT32 pvrctrl_regs[0x100/4];
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static UINT32 pvrta_regs[0x2000/4];
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VIDEO_START(dc)
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{
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memset(pvrctrl_regs, 0, sizeof(pvrctrl_regs));
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memset(pvrta_regs, 0, sizeof(pvrta_regs));
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pvrta_regs[0] = 0x17fd11db; // vendor and device ID of HOLLY chip
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pvrta_regs[1] = 1; // chip revision
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}
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VIDEO_UPDATE(dc)
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{
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dc_vblank();
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return 0;
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}
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// register decode helper
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INLINE int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
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{
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int reg = offset * 2;
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*shift = 0;
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if (mem_mask == U64(0x00000000ffffffff))
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{
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reg++;
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*shift = 32;
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}
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return reg;
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}
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READ64_HANDLER( pvr_ctrl_r )
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{
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return 0;
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int reg;
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UINT64 shift;
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reg = decode_reg_64(offset, mem_mask, &shift);
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#if DEBUG_PVRCTRL
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mame_printf_verbose("PVRCTRL: read %x @ %x (reg %x), mask %llx (PC=%x)\n", pvrctrl_regs[reg], offset, reg, mem_mask, activecpu_get_pc());
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#endif
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return (UINT64)pvrctrl_regs[reg] << shift;
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}
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WRITE64_HANDLER( pvr_ctrl_w )
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{
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mame_printf_verbose("PVRCTRL: write %llx to %x, mask %llx\n", data, offset, mem_mask);
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int reg;
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UINT64 shift;
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reg = decode_reg_64(offset, mem_mask, &shift);
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#if DEBUG_PVRCTRL
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mame_printf_verbose("PVRCTRL: write %llx to %x (reg %x), mask %llx\n", data>>shift, offset, reg, mem_mask);
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#endif
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pvrctrl_regs[reg] |= data >> shift;
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}
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READ64_HANDLER( pvr_ta_r )
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{
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return 0;
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int reg;
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UINT64 shift;
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reg = decode_reg_64(offset, mem_mask, &shift);
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#if DEBUG_PVRTA
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mame_printf_verbose("PVRTA: read %x @ %x (reg %x), mask %llx (PC=%x)\n", pvrta_regs[reg], offset, reg, mem_mask, activecpu_get_pc());
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#endif
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return (UINT64)pvrta_regs[reg] << shift;
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}
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WRITE64_HANDLER( pvr_ta_w )
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{
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mame_printf_verbose("PVR TA: write %llx to %x, mask %llx\n", data, offset, mem_mask);
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int reg;
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UINT64 shift;
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reg = decode_reg_64(offset, mem_mask, &shift);
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#if DEBUG_PVRTA
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mame_printf_verbose("PVRTA: write %llx to %x (reg %x %x), mask %llx\n", data>>shift, offset, reg, (reg*4)+0x8000, mem_mask);
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#endif
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pvrta_regs[reg] |= data >> shift;
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}
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@ -45,4 +111,3 @@ WRITE64_HANDLER( ta_fifo_yuv_w )
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{
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mame_printf_verbose("YUV FIFO: write %llx to %x, mask %llx\n", data, offset, mem_mask);
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}
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