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namcoic.c: remove legacy read/write handlers [Alex Jackson]

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This commit is contained in:
Alex W. Jackson 2014-04-19 10:36:03 +00:00
parent cea459d28b
commit 464f7eb46d
6 changed files with 33 additions and 101 deletions
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14
src/mame/drivers/namcofl.c
View File

@ -226,15 +226,15 @@ WRITE32_MEMBER(namcofl_state::namcofl_share_w)
static ADDRESS_MAP_START( namcofl_mem, AS_PROGRAM, 32, namcofl_state )
AM_RANGE(0x00000000, 0x000fffff) AM_RAMBANK("bank1")
AM_RANGE(0x10000000, 0x100fffff) AM_RAMBANK("bank2")
AM_RANGE(0x20000000, 0x201fffff) AM_ROM AM_REGION("user1", 0) /* data */
AM_RANGE(0x20000000, 0x201fffff) AM_ROM AM_REGION("data", 0)
AM_RANGE(0x30000000, 0x30001fff) AM_RAM AM_SHARE("nvram") /* nvram */
AM_RANGE(0x30100000, 0x30100003) AM_WRITE(namcofl_spritebank_w)
AM_RANGE(0x30284000, 0x3028bfff) AM_READWRITE(namcofl_share_r, namcofl_share_w)
AM_RANGE(0x30300000, 0x30303fff) AM_RAM /* COMRAM */
AM_RANGE(0x30380000, 0x303800ff) AM_READ(fl_network_r ) /* network registers */
AM_RANGE(0x30400000, 0x3040ffff) AM_RAM_WRITE(namcofl_paletteram_w) AM_SHARE("paletteram")
AM_RANGE(0x30800000, 0x3080ffff) AM_READWRITE_LEGACY(namco_tilemapvideoram32_le_r, namco_tilemapvideoram32_le_w )
AM_RANGE(0x30a00000, 0x30a0003f) AM_READWRITE_LEGACY(namco_tilemapcontrol32_le_r, namco_tilemapcontrol32_le_w )
AM_RANGE(0x30800000, 0x3080ffff) AM_READWRITE16(c123_tilemap_videoram_r,c123_tilemap_videoram_w,0xffffffff)
AM_RANGE(0x30a00000, 0x30a0003f) AM_READWRITE16(c123_tilemap_control_r,c123_tilemap_control_w,0xffffffff)
AM_RANGE(0x30c00000, 0x30c1ffff) AM_READWRITE16(c169_roz_videoram_r,c169_roz_videoram_w,0xffffffff) AM_SHARE("rozvideoram")
AM_RANGE(0x30d00000, 0x30d0001f) AM_READWRITE16(c169_roz_control_r,c169_roz_control_w,0xffffffff)
AM_RANGE(0x30e00000, 0x30e1ffff) AM_READWRITE16(c355_obj_ram_r,c355_obj_ram_w,0xffffffff) AM_SHARE("objram")
@ -619,7 +619,7 @@ ROM_START( speedrcr )
ROM_LOAD32_WORD("se2mpea4.19a", 0x000000, 0x080000, CRC(95ab3fd7) SHA1(273a536f8512f3c55260ac1b78533bc35b8390ed) )
ROM_LOAD32_WORD("se2mpoa4.18a", 0x000002, 0x080000, CRC(5b5ef1eb) SHA1(3e9e4abb1a32269baef772079de825dfe1ea230c) )
ROM_REGION( 0x200000, "user1", 0 ) // Data
ROM_REGION32_LE( 0x200000, "data", 0 ) // Data
ROM_LOAD32_BYTE("se1_dat0.13a", 0x000000, 0x080000, CRC(cc5d6ff5) SHA1(6fad40a1fac75bc64d3b7a7562cf7ce2a3abd36a) )
ROM_LOAD32_BYTE("se1_dat1.14a", 0x000001, 0x080000, CRC(ddc8b306) SHA1(f169d521b800c108deffdef9fc6b0058621ee909) )
ROM_LOAD32_BYTE("se1_dat2.15a", 0x000002, 0x080000, CRC(2a29abbb) SHA1(945419ed61e9a656a340214a63a01818396fbe98) )
@ -675,7 +675,7 @@ ROM_START( finalapr )
ROM_LOAD32_WORD("flr2mpeb.19a", 0x000000, 0x080000, CRC(8bfe615f) SHA1(7b867eb261268a83177f1f873689f77d1b6c47ca) )
ROM_LOAD32_WORD("flr2mpob.18a", 0x000002, 0x080000, CRC(91c14e4f) SHA1(934a86daaef0e3e2c2b3066f4677ccb3aaab6eaf) )
ROM_REGION( 0x200000, "user1", ROMREGION_ERASEFF ) // Data
ROM_REGION32_LE( 0x200000, "data", ROMREGION_ERASEFF ) // Data
ROM_REGION16_LE( 0x4000, "c75", 0 ) // C75 program
ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
@ -717,7 +717,7 @@ ROM_START( finalapro )
ROM_LOAD32_WORD("flr2mpe.19a", 0x000000, 0x080000, CRC(cc8961ae) SHA1(08ce4d27a723101370d1c536b26256ce0d8a1b6c) )
ROM_LOAD32_WORD("flr2mpo.18a", 0x000002, 0x080000, CRC(8118f465) SHA1(c4b79878a82fd36b5707e92aa893f69c2b942d57) )
ROM_REGION( 0x200000, "user1", ROMREGION_ERASEFF ) // Data
ROM_REGION32_LE( 0x200000, "data", ROMREGION_ERASEFF ) // Data
ROM_REGION16_LE( 0x4000, "c75", 0 ) // C75 program
ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
@ -760,7 +760,7 @@ ROM_START( finalaprj )
ROM_LOAD32_WORD("flr1_mpec.19a", 0x000000, 0x080000, CRC(52735494) SHA1(db9873cb39bcfdd3dbe2e5079249fecac2c46df9) )
ROM_LOAD32_WORD("flr1_mpoc.18a", 0x000002, 0x080000, CRC(b11fe577) SHA1(70b51a1e66a3bb92f027aad7ba0f358c0e139b3c) )
ROM_REGION( 0x200000, "user1", ROMREGION_ERASEFF ) // Data
ROM_REGION32_LE( 0x200000, "data", ROMREGION_ERASEFF ) // Data
ROM_REGION16_LE( 0x4000, "c75", 0 ) // C75 program
ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )

71
src/mame/drivers/namcoic.c
View File

@ -115,14 +115,14 @@ SetTilemapVideoram( int offset, UINT16 newword )
}
} /* SetTilemapVideoram */
WRITE16_MEMBER( namcos2_state::namco_tilemapvideoram16_w )
WRITE16_MEMBER( namcos2_shared_state::c123_tilemap_videoram_w )
{
UINT16 newword = mTilemapInfo.videoram[offset];
COMBINE_DATA( &newword );
SetTilemapVideoram( offset, newword );
}
READ16_MEMBER( namcos2_state::namco_tilemapvideoram16_r )
READ16_MEMBER( namcos2_shared_state::c123_tilemap_videoram_r )
{
return mTilemapInfo.videoram[offset];
}
@ -178,81 +178,18 @@ SetTilemapControl( int offset, UINT16 newword )
}
} /* SetTilemapControl */
WRITE16_MEMBER( namcos2_state::namco_tilemapcontrol16_w )
WRITE16_MEMBER( namcos2_shared_state::c123_tilemap_control_w )
{
UINT16 newword = mTilemapInfo.control[offset];
COMBINE_DATA( &newword );
SetTilemapControl( offset, newword );
}
READ16_MEMBER( namcos2_state::namco_tilemapcontrol16_r )
READ16_MEMBER( namcos2_shared_state::c123_tilemap_control_r )
{
return mTilemapInfo.control[offset];
}
READ32_HANDLER( namco_tilemapvideoram32_r )
{
offset *= 2;
return (mTilemapInfo.videoram[offset]<<16)|mTilemapInfo.videoram[offset+1];
}
WRITE32_HANDLER( namco_tilemapvideoram32_w )
{
UINT32 v;
offset *=2;
v = (mTilemapInfo.videoram[offset]<<16)|mTilemapInfo.videoram[offset+1];
COMBINE_DATA(&v);
SetTilemapVideoram( offset, v>>16 );
SetTilemapVideoram( offset+1, v&0xffff );
}
READ32_HANDLER( namco_tilemapcontrol32_r )
{
offset *= 2;
return (mTilemapInfo.control[offset]<<16)|mTilemapInfo.control[offset+1];
}
WRITE32_HANDLER( namco_tilemapcontrol32_w )
{
UINT32 v;
offset *=2;
v = (mTilemapInfo.control[offset]<<16)|mTilemapInfo.control[offset+1];
COMBINE_DATA(&v);
SetTilemapControl( offset, v>>16 );
SetTilemapControl( offset+1, v&0xffff );
}
READ32_HANDLER( namco_tilemapcontrol32_le_r )
{
offset *= 2;
return (mTilemapInfo.control[offset+1]<<16)|mTilemapInfo.control[offset];
}
WRITE32_HANDLER( namco_tilemapcontrol32_le_w )
{
UINT32 v;
offset *=2;
v = (mTilemapInfo.control[offset+1]<<16)|mTilemapInfo.control[offset];
COMBINE_DATA(&v);
SetTilemapControl( offset+1, v>>16 );
SetTilemapControl( offset, v&0xffff );
}
READ32_HANDLER( namco_tilemapvideoram32_le_r )
{
offset *= 2;
return (mTilemapInfo.videoram[offset+1]<<16)|mTilemapInfo.videoram[offset];
}
WRITE32_HANDLER( namco_tilemapvideoram32_le_w )
{
UINT32 v;
offset *=2;
v = (mTilemapInfo.videoram[offset+1]<<16)|mTilemapInfo.videoram[offset];
COMBINE_DATA(&v);
SetTilemapVideoram( offset+1, v>>16 );
SetTilemapVideoram( offset, v&0xffff );
}
/**************************************************************************************/

8
src/mame/drivers/namconb1.c
View File

@ -708,8 +708,8 @@ static ADDRESS_MAP_START( namconb1_am, AS_PROGRAM, 32, namconb1_state )
AM_RANGE(0x580000, 0x5807ff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0xffffffff)
AM_RANGE(0x600000, 0x61ffff) AM_READWRITE16(c355_obj_ram_r,c355_obj_ram_w,0xffffffff) AM_SHARE("objram")
AM_RANGE(0x620000, 0x620007) AM_READWRITE16(c355_obj_position_r,c355_obj_position_w,0xffffffff)
AM_RANGE(0x640000, 0x64ffff) AM_READWRITE_LEGACY(namco_tilemapvideoram32_r,namco_tilemapvideoram32_w )
AM_RANGE(0x660000, 0x66003f) AM_READWRITE_LEGACY(namco_tilemapcontrol32_r,namco_tilemapcontrol32_w)
AM_RANGE(0x640000, 0x64ffff) AM_READWRITE16(c123_tilemap_videoram_r,c123_tilemap_videoram_w,0xffffffff)
AM_RANGE(0x660000, 0x66003f) AM_READWRITE16(c123_tilemap_control_r,c123_tilemap_control_w,0xffffffff)
AM_RANGE(0x680000, 0x68000f) AM_RAM AM_SHARE("spritebank32")
AM_RANGE(0x6e0000, 0x6e001f) AM_READ(custom_key_r) AM_WRITENOP
AM_RANGE(0x700000, 0x707fff) AM_RAM AM_SHARE("paletteram")
@ -725,8 +725,8 @@ static ADDRESS_MAP_START( namconb2_am, AS_PROGRAM, 32, namconb1_state )
AM_RANGE(0x600000, 0x61ffff) AM_READWRITE16(c355_obj_ram_r,c355_obj_ram_w,0xffffffff) AM_SHARE("objram")
AM_RANGE(0x620000, 0x620007) AM_READWRITE16(c355_obj_position_r,c355_obj_position_w,0xffffffff)
AM_RANGE(0x640000, 0x64000f) AM_RAM /* unknown xy offset */
AM_RANGE(0x680000, 0x68ffff) AM_READWRITE_LEGACY(namco_tilemapvideoram32_r, namco_tilemapvideoram32_w )
AM_RANGE(0x6c0000, 0x6c003f) AM_READWRITE_LEGACY(namco_tilemapcontrol32_r, namco_tilemapcontrol32_w )
AM_RANGE(0x680000, 0x68ffff) AM_READWRITE16(c123_tilemap_videoram_r,c123_tilemap_videoram_w,0xffffffff)
AM_RANGE(0x6c0000, 0x6c003f) AM_READWRITE16(c123_tilemap_control_r,c123_tilemap_control_w,0xffffffff)
AM_RANGE(0x700000, 0x71ffff) AM_READWRITE16(c169_roz_videoram_r,c169_roz_videoram_w,0xffffffff) AM_SHARE("rozvideoram")
AM_RANGE(0x740000, 0x74001f) AM_READWRITE16(c169_roz_control_r,c169_roz_control_w,0xffffffff)
AM_RANGE(0x800000, 0x807fff) AM_RAM AM_SHARE("paletteram")

4
src/mame/drivers/namcos2.c
View File

@ -598,8 +598,8 @@ READ8_MEMBER(namcos2_state::ack_mcu_vbl_r)
static ADDRESS_MAP_START( namcos2_68k_default_cpu_board_am, AS_PROGRAM, 16, namcos2_state )
AM_RANGE(0x200000, 0x3fffff) AM_ROM AM_REGION("data_rom", 0)
AM_RANGE(0x400000, 0x41ffff) AM_READWRITE(namco_tilemapvideoram16_r,namco_tilemapvideoram16_w)
AM_RANGE(0x420000, 0x42003f) AM_READWRITE(namco_tilemapcontrol16_r,namco_tilemapcontrol16_w)
AM_RANGE(0x400000, 0x41ffff) AM_READWRITE(c123_tilemap_videoram_r,c123_tilemap_videoram_w)
AM_RANGE(0x420000, 0x42003f) AM_READWRITE(c123_tilemap_control_r,c123_tilemap_control_w)
AM_RANGE(0x440000, 0x44ffff) AM_READWRITE(paletteram_word_r,paletteram_word_w) AM_SHARE("paletteram")
AM_RANGE(0x460000, 0x460fff) AM_READWRITE(dpram_word_r,dpram_word_w)
AM_RANGE(0x468000, 0x468fff) AM_READWRITE(dpram_word_r,dpram_word_w) /* mirror */

10
src/mame/includes/namcoic.h
View File

@ -100,16 +100,6 @@ C102 - Controls CPU access to ROZ Memory Area.
void namco_tilemap_draw( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int pri );
void namco_tilemap_invalidate( void );
DECLARE_READ32_HANDLER( namco_tilemapvideoram32_r );
DECLARE_WRITE32_HANDLER( namco_tilemapvideoram32_w );
DECLARE_READ32_HANDLER( namco_tilemapcontrol32_r );
DECLARE_WRITE32_HANDLER( namco_tilemapcontrol32_w );
DECLARE_READ32_HANDLER( namco_tilemapvideoram32_le_r );
DECLARE_WRITE32_HANDLER( namco_tilemapvideoram32_le_w );
DECLARE_READ32_HANDLER( namco_tilemapcontrol32_le_r );
DECLARE_WRITE32_HANDLER( namco_tilemapcontrol32_le_w );
/***********************************************************************************/
#endif

27
src/mame/includes/namcos2.h
View File

@ -121,6 +121,21 @@ public:
bool is_system21();
int m_gametype;
// C123 Tilemap Emulation
// TODO: merge with namcos1.c implementation and convert to device
public:
DECLARE_WRITE16_MEMBER( c123_tilemap_videoram_w );
DECLARE_READ16_MEMBER( c123_tilemap_videoram_r );
DECLARE_WRITE16_MEMBER( c123_tilemap_control_w );
DECLARE_READ16_MEMBER( c123_tilemap_control_r );
TILE_GET_INFO_MEMBER( get_tile_info0 );
TILE_GET_INFO_MEMBER( get_tile_info1 );
TILE_GET_INFO_MEMBER( get_tile_info2 );
TILE_GET_INFO_MEMBER( get_tile_info3 );
TILE_GET_INFO_MEMBER( get_tile_info4 );
TILE_GET_INFO_MEMBER( get_tile_info5 );
void namco_tilemap_init(int gfxbank, void *pMaskROM, void (*cb)( running_machine &machine, UINT16 code, int *gfx, int *mask) );
// C169 ROZ Layer Emulation
public:
void c169_roz_init(int gfxbank, const char *maskregion);
@ -131,13 +146,7 @@ public:
DECLARE_WRITE16_MEMBER( c169_roz_bank_w );
DECLARE_READ16_MEMBER( c169_roz_videoram_r );
DECLARE_WRITE16_MEMBER( c169_roz_videoram_w );
TILE_GET_INFO_MEMBER( get_tile_info0 );
TILE_GET_INFO_MEMBER( get_tile_info1 );
TILE_GET_INFO_MEMBER( get_tile_info2 );
TILE_GET_INFO_MEMBER( get_tile_info3 );
TILE_GET_INFO_MEMBER( get_tile_info4 );
TILE_GET_INFO_MEMBER( get_tile_info5 );
void namco_tilemap_init(int gfxbank, void *pMaskROM, void (*cb)( running_machine &machine, UINT16 code, int *gfx, int *mask) );
protected:
struct roz_parameters
{
@ -334,10 +343,6 @@ public:
DECLARE_READ16_MEMBER( namcos2_68k_key_r );
DECLARE_WRITE16_MEMBER( namcos2_68k_key_w );
DECLARE_WRITE16_MEMBER( namco_tilemapvideoram16_w );
DECLARE_READ16_MEMBER( namco_tilemapvideoram16_r );
DECLARE_WRITE16_MEMBER( namco_tilemapcontrol16_w );
DECLARE_READ16_MEMBER( namco_tilemapcontrol16_r );
DECLARE_READ16_MEMBER( namcos2_finallap_prot_r );
};