mirror of
https://github.com/holub/mame
synced 2025-04-24 17:30:55 +03:00
updated lsi53c810 to use delegates, and moved some formerly static
stuff into bebox and model3 classes. nw.
This commit is contained in:
Fabio Priuli
parent
38e37f2ad4
commit
46769cf6b2
@ -9,7 +9,7 @@
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UINT32 lsi53c810_device::FETCH()
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{
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UINT32 r = fetch(machine(), dsp);
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UINT32 r = m_fetch_cb(dsp);
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dsp += 4;
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return r;
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}
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@ -26,9 +26,8 @@ void lsi53c810_device::dmaop_move_memory()
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int count;
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count = dcmd & 0xffffff;
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if(dma_callback != NULL) {
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dma_callback(machine(), src, dst, count, 1);
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}
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if (!m_dma_cb.isnull())
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m_dma_cb(src, dst, count, 1);
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}
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void lsi53c810_device::dmaop_interrupt()
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@ -41,9 +40,9 @@ void lsi53c810_device::dmaop_interrupt()
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istat |= 0x1; /* DMA interrupt pending */
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dstat |= 0x4; /* SIR (SCRIPTS Interrupt Instruction Received) */
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if(irq_callback != NULL) {
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irq_callback(machine(), 1);
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}
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if (!m_irq_cb.isnull())
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m_irq_cb(1);
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dma_icount = 0;
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halted = 1;
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}
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@ -59,7 +58,7 @@ void lsi53c810_device::dmaop_block_move()
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// normal indirect
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if (dcmd & 0x20000000)
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address = fetch(machine(), address);
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address = m_fetch_cb(address);
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// table indirect
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if (dcmd & 0x10000000)
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@ -74,8 +73,8 @@ void lsi53c810_device::dmaop_block_move()
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dsps += dsa;
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logerror("Loading from table at %x\n", dsps);
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count = fetch(machine(),dsps);
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address = fetch(machine(),dsps+4);
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count = m_fetch_cb(dsps);
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address = m_fetch_cb(dsps + 4);
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}
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logerror("block move: address %x count %x phase %x\n", address, count, (dcmd>>24)&7);
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@ -428,10 +427,8 @@ UINT8 lsi53c810_device::lsi53c810_reg_r( int offset )
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return (dsa >> 24) & 0xff;
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case 0x14: /* ISTAT */
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// clear the interrupt on service
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if(irq_callback != NULL)
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{
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irq_callback(machine(), 0);
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}
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if (!m_irq_cb.isnull())
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m_irq_cb(0);
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return istat;
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case 0x2c: /* DSP [7-0] */
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@ -572,9 +569,8 @@ void lsi53c810_device::lsi53c810_reg_w(int offset, UINT8 data)
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istat |= 0x3; /* DMA interrupt pending */
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dstat |= 0x8; /* SSI (Single Step Interrupt) */
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if(irq_callback != NULL) {
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irq_callback(machine(), 1);
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}
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if (!m_irq_cb.isnull())
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m_irq_cb(1);
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}
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else if(dcntl & 0x04 && !halted) /* manual start DMA */
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{
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@ -610,9 +606,10 @@ void lsi53c810_device::lsi53c810_reg_w(int offset, UINT8 data)
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void lsi53c810_device::add_opcode(UINT8 op, UINT8 mask, opcode_handler_delegate handler)
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{
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int i;
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for(i=0; i < 256; i++) {
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if((i & mask) == op) {
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for (int i = 0; i < 256; i++)
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{
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if ((i & mask) == op)
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{
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dma_opcode[i] = handler;
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}
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}
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@ -623,23 +620,15 @@ lsi53c810_device::lsi53c810_device(const machine_config &mconfig, const char *ta
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{
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}
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void lsi53c810_device::device_config_complete()
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{
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// inherit a copy of the static data
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const LSI53C810interface *intf = reinterpret_cast<const LSI53C810interface *>(static_config());
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if (intf != NULL)
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{
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*static_cast<LSI53C810interface *>(this) = *intf;
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}
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}
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void lsi53c810_device::device_start()
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{
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int i;
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for(i = 0; i < 256; i++)
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m_irq_cb.bind_relative_to(*owner());
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m_dma_cb.bind_relative_to(*owner());
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m_fetch_cb.bind_relative_to(*owner());
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for (int i = 0; i < 256; i++)
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{
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dma_opcode[i] = opcode_handler_delegate(FUNC( lsi53c810_device::dmaop_invalid ), this);
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dma_opcode[i] = opcode_handler_delegate(FUNC(lsi53c810_device::dmaop_invalid), this);
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}
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add_opcode(0x00, 0xc0, opcode_handler_delegate(FUNC( lsi53c810_device::dmaop_block_move ), this));
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@ -662,10 +651,10 @@ void lsi53c810_device::device_start()
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memset(devices, 0, sizeof(devices));
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// try to open the devices
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for( device_t *device = owner()->first_subdevice(); device != NULL; device = device->next() )
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for (device_t *device = owner()->first_subdevice(); device != NULL; device = device->next())
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{
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scsihle_device *scsidev = dynamic_cast<scsihle_device *>(device);
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if( scsidev != NULL )
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if (scsidev != NULL)
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{
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devices[scsidev->GetDeviceID()] = scsidev;
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}
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@ -704,7 +693,7 @@ void lsi53c810_device::lsi53c810_write_data(int bytes, UINT8 *pData)
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UINT32 lsi53c810_device::lsi53c810_dasm_fetch(UINT32 pc)
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{
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return fetch(machine(), pc);
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return m_fetch_cb(pc);
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}
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unsigned lsi53c810_device::lsi53c810_dasm(char *buf, UINT32 pc)
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@ -3,24 +3,26 @@
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#include "machine/scsihle.h"
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struct LSI53C810interface
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{
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void (*irq_callback)(running_machine &machine, int); /* IRQ callback */
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void (*dma_callback)(running_machine &machine, UINT32, UINT32, int, int); /* DMA callback */
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UINT32 (*fetch)(running_machine &machine, UINT32 dsp);
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};
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typedef device_delegate<void (int state)> lsi53c810_irq_delegate;
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#define LSI53C810_IRQ_CB(name) void name(int state)
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#define MCFG_LSI53C810_ADD( _tag, _config ) \
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MCFG_DEVICE_ADD( _tag, LSI53C810, 0 ) \
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MCFG_DEVICE_CONFIG(_config)
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typedef device_delegate<void (UINT32 src, UINT32 dst, int length, int byteswap)> lsi53c810_dma_delegate;
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#define LSI53C810_DMA_CB(name) void name(UINT32 src, UINT32 dst, int length, int byteswap)
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class lsi53c810_device : public device_t,
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public LSI53C810interface
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typedef device_delegate<UINT32 (UINT32 dsp)> lsi53c810_fetch_delegate;
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#define LSI53C810_FETCH_CB(name) UINT32 name(UINT32 dsp)
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class lsi53c810_device : public device_t
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{
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public:
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// construction/destruction
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lsi53c810_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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static void set_irq_callback(device_t &device, lsi53c810_irq_delegate callback) { downcast<lsi53c810_device &>(device).m_irq_cb = callback; }
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static void set_dma_callback(device_t &device, lsi53c810_dma_delegate callback) { downcast<lsi53c810_device &>(device).m_dma_cb = callback; }
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static void set_fetch_callback(device_t &device, lsi53c810_fetch_delegate callback) { downcast<lsi53c810_device &>(device).m_fetch_cb = callback; }
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void lsi53c810_read_data(int bytes, UINT8 *pData);
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void lsi53c810_write_data(int bytes, UINT8 *pData);
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@ -29,13 +31,16 @@ public:
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protected:
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// device-level overrides
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virtual void device_config_complete();
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virtual void device_start();
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private:
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typedef delegate<void (void)> opcode_handler_delegate;
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opcode_handler_delegate dma_opcode[256];
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lsi53c810_irq_delegate m_irq_cb;
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lsi53c810_dma_delegate m_dma_cb;
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lsi53c810_fetch_delegate m_fetch_cb;
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UINT32 FETCH();
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void dmaop_invalid();
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void dmaop_move_memory();
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@ -100,4 +105,14 @@ private:
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// device type definition
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extern const device_type LSI53C810;
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#define MCFG_LSI53C810_IRQ_CB(_class, _method) \
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lsi53c810_device::set_irq_callback(*device, lsi53c810_irq_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
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#define MCFG_LSI53C810_DMA_CB(_class, _method) \
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lsi53c810_device::set_dma_callback(*device, lsi53c810_dma_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
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#define MCFG_LSI53C810_FETCH_CB(_class, _method) \
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lsi53c810_device::set_fetch_callback(*device, lsi53c810_fetch_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
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#endif
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@ -662,34 +662,28 @@ ALL VROM ROMs are 16M MASK
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#include "includes/model3.h"
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static void real3d_dma_callback(running_machine &machine, UINT32 src, UINT32 dst, int length, int byteswap);
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static void update_irq_state(running_machine &machine)
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void model3_state::update_irq_state()
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{
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model3_state *state = machine.driver_data<model3_state>();
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if ((state->m_irq_enable & state->m_irq_state) || state->m_scsi_irq_state)
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if ((m_irq_enable & m_irq_state) || m_scsi_irq_state)
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{
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// printf("IRQ set: state %x enable %x scsi %x\n", state->m_irq_state, state->m_irq_enable, state->m_scsi_irq_state);
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state->m_maincpu->set_input_line(PPC_IRQ, ASSERT_LINE);
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state->m_scsi_irq_state = 0;
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// printf("IRQ set: state %x enable %x scsi %x\n", m_irq_state, m_irq_enable, m_scsi_irq_state);
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m_maincpu->set_input_line(PPC_IRQ, ASSERT_LINE);
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m_scsi_irq_state = 0;
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}
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else
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{
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// printf("IRQ clear: state %x enable %x scsi %x\n", state->m_irq_state, state->m_irq_enable, state->m_scsi_irq_state);
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state->m_maincpu->set_input_line(PPC_IRQ, CLEAR_LINE);
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// printf("IRQ clear: state %x enable %x scsi %x\n", m_irq_state, m_irq_enable, m_scsi_irq_state);
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m_maincpu->set_input_line(PPC_IRQ, CLEAR_LINE);
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}
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}
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void model3_set_irq_line(running_machine &machine, UINT8 bit, int line)
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void model3_state::set_irq_line(UINT8 bit, int line)
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{
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model3_state *state = machine.driver_data<model3_state>();
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if (line != CLEAR_LINE)
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state->m_irq_state |= bit;
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m_irq_state |= bit;
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else
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state->m_irq_state &= ~bit;
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update_irq_state(machine);
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m_irq_state &= ~bit;
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update_irq_state();
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}
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@ -1056,20 +1050,17 @@ WRITE64_MEMBER(model3_state::scsi_w)
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}
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}
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static UINT32 scsi_fetch(running_machine &machine, UINT32 dsp)
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LSI53C810_FETCH_CB(model3_state::scsi_fetch)
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{
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model3_state *drvstate = machine.driver_data<model3_state>();
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address_space &space = drvstate->m_maincpu->space(AS_PROGRAM);
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UINT32 result;
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result = space.read_dword(dsp);
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address_space &space = m_maincpu->space(AS_PROGRAM);
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UINT32 result = space.read_dword(dsp);
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return FLIPENDIAN_INT32(result);
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}
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static void scsi_irq_callback(running_machine &machine, int state)
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LSI53C810_IRQ_CB(model3_state::scsi_irq_callback)
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{
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model3_state *drvstate = machine.driver_data<model3_state>();
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drvstate->m_scsi_irq_state = state;
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update_irq_state(machine);
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m_scsi_irq_state = state;
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update_irq_state();
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}
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/*****************************************************************************/
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@ -1112,21 +1103,21 @@ WRITE64_MEMBER(model3_state::real3d_dma_w)
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int length = FLIPENDIAN_INT32((UINT32)(data >> 32)) * 4;
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if (m_dma_endian & 0x80)
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{
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real3d_dma_callback(machine(), m_dma_source, m_dma_dest, length, 0);
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real3d_dma_callback(m_dma_source, m_dma_dest, length, 0);
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}
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else
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{
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real3d_dma_callback(machine(), m_dma_source, m_dma_dest, length, 1);
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real3d_dma_callback(m_dma_source, m_dma_dest, length, 1);
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}
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m_dma_irq |= 0x01;
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scsi_irq_callback(machine(), 1);
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scsi_irq_callback(1);
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return;
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}
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else if(ACCESSING_BITS_16_23)
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{
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if(data & 0x10000) {
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m_dma_irq &= ~0x1;
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scsi_irq_callback(machine(), 0);
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scsi_irq_callback(0);
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}
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return;
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}
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@ -1157,47 +1148,38 @@ WRITE64_MEMBER(model3_state::real3d_dma_w)
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logerror("real3d_dma_w: %08X, %08X%08X, %08X%08X", offset, (UINT32)(data >> 32), (UINT32)(data), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask));
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}
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static void real3d_dma_callback(running_machine &machine, UINT32 src, UINT32 dst, int length, int byteswap)
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LSI53C810_DMA_CB(model3_state::real3d_dma_callback)
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{
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model3_state *drvstate = machine.driver_data<model3_state>();
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address_space &space = drvstate->m_maincpu->space(AS_PROGRAM);
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switch(dst >> 24)
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{
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case 0x88: /* Display List End Trigger */
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real3d_display_list_end(machine);
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real3d_display_list_end();
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break;
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case 0x8c: /* Display List RAM 2 */
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real3d_display_list2_dma(space, src, dst, length, byteswap);
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real3d_display_list2_dma(src, dst, length, byteswap);
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break;
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case 0x8e: /* Display List RAM 1 */
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real3d_display_list1_dma(space, src, dst, length, byteswap);
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real3d_display_list1_dma(src, dst, length, byteswap);
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break;
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case 0x90: /* VROM Texture Download */
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real3d_vrom_texture_dma(space, src, dst, length, byteswap);
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real3d_vrom_texture_dma(src, dst, length, byteswap);
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break;
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case 0x94: /* Texture FIFO */
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real3d_texture_fifo_dma(space, src, length, byteswap);
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real3d_texture_fifo_dma(src, length, byteswap);
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break;
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case 0x98: /* Polygon RAM */
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real3d_polygon_ram_dma(space, src, dst, length, byteswap);
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real3d_polygon_ram_dma(src, dst, length, byteswap);
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break;
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case 0x9c: /* Unknown */
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break;
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default:
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logerror("dma_callback: %08X, %08X, %d at %08X", src, dst, length, machine.device("maincpu")->safe_pc());
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logerror("dma_callback: %08X, %08X, %d at %08X", src, dst, length, machine().device("maincpu")->safe_pc());
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break;
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}
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}
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/*****************************************************************************/
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static const struct LSI53C810interface lsi53c810_intf =
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{
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&scsi_irq_callback,
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&real3d_dma_callback,
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&scsi_fetch,
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};
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static void configure_fast_ram(running_machine &machine)
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{
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model3_state *state = machine.driver_data<model3_state>();
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@ -1212,7 +1194,7 @@ TIMER_CALLBACK_MEMBER(model3_state::model3_sound_timer_tick)
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{
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if (m_sound_irq_enable)
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{
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model3_set_irq_line(machine(), 0x40, ASSERT_LINE);
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set_irq_line(0x40, ASSERT_LINE);
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}
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}
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@ -1617,7 +1599,7 @@ WRITE8_MEMBER(model3_state::model3_sound_w)
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{
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case 0:
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// clear the interrupt
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model3_set_irq_line(machine(), 0x40, CLEAR_LINE);
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set_irq_line(0x40, CLEAR_LINE);
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if (m_dsbz80 != NULL)
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{
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@ -5395,9 +5377,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(model3_state::model3_interrupt)
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int scanline = param;
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if (scanline == 384)
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model3_set_irq_line(machine(), 0x02, ASSERT_LINE);
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set_irq_line(0x02, ASSERT_LINE);
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else if(scanline == 0)
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model3_set_irq_line(machine(), 0x0d, ASSERT_LINE);
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set_irq_line(0x0d, ASSERT_LINE);
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}
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static const powerpc_config model3_10 =
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@ -5457,7 +5439,10 @@ static MACHINE_CONFIG_START( model3_10, model3_state )
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MCFG_SOUND_ROUTE(0, "rspeaker", 2.0)
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MCFG_SCSIBUS_ADD("scsi")
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MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
|
||||
MCFG_DEVICE_ADD("scsi:lsi53c810", LSI53C810, 0)
|
||||
MCFG_LSI53C810_IRQ_CB(model3_state, scsi_irq_callback)
|
||||
MCFG_LSI53C810_DMA_CB(model3_state, real3d_dma_callback)
|
||||
MCFG_LSI53C810_FETCH_CB(model3_state, scsi_fetch)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( model3_15, model3_state )
|
||||
@ -5497,7 +5482,10 @@ static MACHINE_CONFIG_START( model3_15, model3_state )
|
||||
MCFG_SOUND_ROUTE(0, "rspeaker", 2.0)
|
||||
|
||||
MCFG_SCSIBUS_ADD("scsi")
|
||||
MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
|
||||
MCFG_DEVICE_ADD("scsi:lsi53c810", LSI53C810, 0)
|
||||
MCFG_LSI53C810_IRQ_CB(model3_state, scsi_irq_callback)
|
||||
MCFG_LSI53C810_DMA_CB(model3_state, real3d_dma_callback)
|
||||
MCFG_LSI53C810_FETCH_CB(model3_state, scsi_fetch)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_DERIVED(scud, model3_15)
|
||||
|
||||
@ -214,14 +214,19 @@ public:
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(model3_interrupt);
|
||||
void model3_exit();
|
||||
DECLARE_WRITE8_MEMBER(scsp_irq);
|
||||
LSI53C810_DMA_CB(real3d_dma_callback);
|
||||
LSI53C810_FETCH_CB(scsi_fetch);
|
||||
LSI53C810_IRQ_CB(scsi_irq_callback);
|
||||
void update_irq_state();
|
||||
void set_irq_line(UINT8 bit, int line);
|
||||
void real3d_display_list_end();
|
||||
void real3d_display_list1_dma(UINT32 src, UINT32 dst, int length, int byteswap);
|
||||
void real3d_display_list2_dma(UINT32 src, UINT32 dst, int length, int byteswap);
|
||||
void real3d_vrom_texture_dma(UINT32 src, UINT32 dst, int length, int byteswap);
|
||||
void real3d_texture_fifo_dma(UINT32 src, int length, int byteswap);
|
||||
void real3d_polygon_ram_dma(UINT32 src, UINT32 dst, int length, int byteswap);
|
||||
};
|
||||
|
||||
|
||||
/*----------- defined in drivers/model3.c -----------*/
|
||||
|
||||
void model3_set_irq_line(running_machine &machine, UINT8 bit, int state);
|
||||
|
||||
|
||||
/*----------- defined in machine/model3.c -----------*/
|
||||
|
||||
void model3_machine_init(running_machine &machine, int step);
|
||||
@ -229,12 +234,3 @@ int model3_tap_read(running_machine &machine);
|
||||
void model3_tap_write(running_machine &machine, int tck, int tms, int tdi, int trst);
|
||||
void model3_tap_reset(running_machine &machine);
|
||||
|
||||
|
||||
/*----------- defined in video/model3.c -----------*/
|
||||
|
||||
void real3d_display_list_end(running_machine &machine);
|
||||
void real3d_display_list1_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap);
|
||||
void real3d_display_list2_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap);
|
||||
void real3d_vrom_texture_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap);
|
||||
void real3d_texture_fifo_dma(address_space &space, UINT32 src, int length, int byteswap);
|
||||
void real3d_polygon_ram_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap);
|
||||
|
||||
@ -446,7 +446,7 @@ WRITE64_MEMBER(model3_state::model3_vid_reg_w)
|
||||
{
|
||||
case 0x00/8: logerror("vid_reg0: %08X%08X\n", (UINT32)(data>>32),(UINT32)(data)); m_vid_reg0 = data; break;
|
||||
case 0x08/8: break; /* ??? */
|
||||
case 0x10/8: model3_set_irq_line(machine(), (data >> 56) & 0x0f, CLEAR_LINE); break; /* VBL IRQ Ack */
|
||||
case 0x10/8: set_irq_line((data >> 56) & 0x0f, CLEAR_LINE); break; /* VBL IRQ Ack */
|
||||
|
||||
case 0x20/8: m_layer_enable = (data >> 52); break;
|
||||
|
||||
@ -747,65 +747,64 @@ static void real3d_upload_texture(running_machine &machine, UINT32 header, UINT3
|
||||
}
|
||||
}
|
||||
|
||||
void real3d_display_list_end(running_machine &machine)
|
||||
void model3_state::real3d_display_list_end()
|
||||
{
|
||||
model3_state *state = machine.driver_data<model3_state>();
|
||||
/* upload textures if there are any in the FIFO */
|
||||
if (state->m_texture_fifo_pos > 0)
|
||||
if (m_texture_fifo_pos > 0)
|
||||
{
|
||||
int i = 0;
|
||||
while(i < state->m_texture_fifo_pos)
|
||||
while (i < m_texture_fifo_pos)
|
||||
{
|
||||
int length = (state->m_texture_fifo[i] / 2) + 2;
|
||||
UINT32 header = state->m_texture_fifo[i+1];
|
||||
real3d_upload_texture(machine, header, &state->m_texture_fifo[i+2]);
|
||||
int length = (m_texture_fifo[i] / 2) + 2;
|
||||
UINT32 header = m_texture_fifo[i+1];
|
||||
real3d_upload_texture(machine(), header, &m_texture_fifo[i+2]);
|
||||
i += length;
|
||||
};
|
||||
}
|
||||
state->m_texture_fifo_pos = 0;
|
||||
state->m_zbuffer.fill(0);
|
||||
state->m_bitmap3d.fill(0x8000);
|
||||
real3d_traverse_display_list(machine);
|
||||
m_texture_fifo_pos = 0;
|
||||
m_zbuffer.fill(0);
|
||||
m_bitmap3d.fill(0x8000);
|
||||
real3d_traverse_display_list(machine());
|
||||
//state->m_real3d_display_list = 1;
|
||||
}
|
||||
|
||||
void real3d_display_list1_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
void model3_state::real3d_display_list1_dma(UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
{
|
||||
model3_state *state = space.machine().driver_data<model3_state>();
|
||||
int i;
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
int d = (dst & 0xffffff) / 4;
|
||||
for(i=0; i < length; i+=4) {
|
||||
for (int i = 0; i < length; i += 4)
|
||||
{
|
||||
UINT32 w;
|
||||
if (byteswap) {
|
||||
w = BYTE_REVERSE32(space.read_dword(src));
|
||||
} else {
|
||||
w = space.read_dword(src);
|
||||
}
|
||||
state->m_display_list_ram[d++] = w;
|
||||
m_display_list_ram[d++] = w;
|
||||
src += 4;
|
||||
}
|
||||
}
|
||||
|
||||
void real3d_display_list2_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
void model3_state::real3d_display_list2_dma(UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
{
|
||||
model3_state *state = space.machine().driver_data<model3_state>();
|
||||
int i;
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
int d = (dst & 0xffffff) / 4;
|
||||
for(i=0; i < length; i+=4) {
|
||||
for (int i = 0; i < length; i += 4)
|
||||
{
|
||||
UINT32 w;
|
||||
if (byteswap) {
|
||||
w = BYTE_REVERSE32(space.read_dword(src));
|
||||
} else {
|
||||
w = space.read_dword(src);
|
||||
}
|
||||
state->m_culling_ram[d++] = w;
|
||||
m_culling_ram[d++] = w;
|
||||
src += 4;
|
||||
}
|
||||
}
|
||||
|
||||
void real3d_vrom_texture_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
void model3_state::real3d_vrom_texture_dma(UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
{
|
||||
model3_state *state = space.machine().driver_data<model3_state>();
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
if((dst & 0xff) == 0) {
|
||||
UINT32 address, header;
|
||||
|
||||
@ -816,47 +815,47 @@ void real3d_vrom_texture_dma(address_space &space, UINT32 src, UINT32 dst, int l
|
||||
address = space.read_dword((src+0));
|
||||
header = space.read_dword((src+4));
|
||||
}
|
||||
real3d_upload_texture(space.machine(), header, (UINT32*)&state->m_vrom[address]);
|
||||
real3d_upload_texture(space.machine(), header, (UINT32*)&m_vrom[address]);
|
||||
}
|
||||
}
|
||||
|
||||
void real3d_texture_fifo_dma(address_space &space, UINT32 src, int length, int byteswap)
|
||||
void model3_state::real3d_texture_fifo_dma(UINT32 src, int length, int byteswap)
|
||||
{
|
||||
model3_state *state = space.machine().driver_data<model3_state>();
|
||||
int i;
|
||||
for(i=0; i < length; i+=4) {
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
for (int i = 0; i < length; i += 4)
|
||||
{
|
||||
UINT32 w;
|
||||
if (byteswap) {
|
||||
w = BYTE_REVERSE32(space.read_dword(src));
|
||||
} else {
|
||||
w = space.read_dword(src);
|
||||
}
|
||||
state->m_texture_fifo[state->m_texture_fifo_pos] = w;
|
||||
state->m_texture_fifo_pos++;
|
||||
m_texture_fifo[m_texture_fifo_pos] = w;
|
||||
m_texture_fifo_pos++;
|
||||
src += 4;
|
||||
}
|
||||
}
|
||||
|
||||
void real3d_polygon_ram_dma(address_space &space, UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
void model3_state::real3d_polygon_ram_dma(UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
{
|
||||
model3_state *state = space.machine().driver_data<model3_state>();
|
||||
int i;
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
int d = (dst & 0xffffff) / 4;
|
||||
for(i=0; i < length; i+=4) {
|
||||
for (int i = 0; i < length; i += 4)
|
||||
{
|
||||
UINT32 w;
|
||||
if (byteswap) {
|
||||
w = BYTE_REVERSE32(space.read_dword(src));
|
||||
} else {
|
||||
w = space.read_dword(src);
|
||||
}
|
||||
state->m_polygon_ram[d++] = w;
|
||||
m_polygon_ram[d++] = w;
|
||||
src += 4;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::real3d_cmd_w)
|
||||
{
|
||||
real3d_display_list_end(machine());
|
||||
real3d_display_list_end();
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -100,34 +100,23 @@ ADDRESS_MAP_END
|
||||
((x << 8) & 0xff0000) | \
|
||||
((x << 24) & 0xff000000))
|
||||
|
||||
static UINT32 scsi53c810_fetch(running_machine &machine, UINT32 dsp)
|
||||
LSI53C810_FETCH_CB(bebox_state::scsi_fetch)
|
||||
{
|
||||
UINT32 result;
|
||||
bebox_state *state = machine.driver_data<bebox_state>();
|
||||
result = state->m_ppc1->space(AS_PROGRAM).read_dword(dsp & 0x7FFFFFFF);
|
||||
UINT32 result = m_ppc1->space(AS_PROGRAM).read_dword(dsp & 0x7FFFFFFF);
|
||||
return BYTE_REVERSE32(result);
|
||||
}
|
||||
|
||||
|
||||
static void scsi53c810_irq_callback(running_machine &machine, int value)
|
||||
LSI53C810_IRQ_CB(bebox_state::scsi_irq_callback)
|
||||
{
|
||||
bebox_set_irq_bit(machine, 21, value);
|
||||
bebox_set_irq_bit(21, state);
|
||||
}
|
||||
|
||||
|
||||
static void scsi53c810_dma_callback(running_machine &machine, UINT32 src, UINT32 dst, int length, int byteswap)
|
||||
LSI53C810_DMA_CB(bebox_state::scsi_dma_callback)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
static const struct LSI53C810interface lsi53c810_intf =
|
||||
{
|
||||
&scsi53c810_irq_callback,
|
||||
&scsi53c810_dma_callback,
|
||||
&scsi53c810_fetch,
|
||||
};
|
||||
|
||||
|
||||
FLOPPY_FORMATS_MEMBER( bebox_state::floppy_formats )
|
||||
FLOPPY_PC_FORMAT
|
||||
FLOPPY_FORMATS_END
|
||||
@ -150,7 +139,7 @@ MACHINE_CONFIG_END
|
||||
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_keyboard_interrupt)
|
||||
{
|
||||
bebox_set_irq_bit(machine(), 16, state);
|
||||
bebox_set_irq_bit(16, state);
|
||||
m_pic8259_1->ir1_w(state);
|
||||
}
|
||||
|
||||
@ -202,7 +191,10 @@ static MACHINE_CONFIG_START( bebox, bebox_state )
|
||||
MCFG_SCSIBUS_ADD("scsi")
|
||||
MCFG_SCSIDEV_ADD("scsi:harddisk1", SCSIHD, SCSI_ID_0)
|
||||
MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_3)
|
||||
MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
|
||||
MCFG_DEVICE_ADD("scsi:lsi53c810", LSI53C810, 0)
|
||||
MCFG_LSI53C810_IRQ_CB(bebox_state, scsi_irq_callback)
|
||||
MCFG_LSI53C810_DMA_CB(bebox_state, scsi_dma_callback)
|
||||
MCFG_LSI53C810_FETCH_CB(bebox_state, scsi_fetch)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD( "ide", ata_devices, "hdd", NULL, false ) /* FIXME */
|
||||
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(bebox_state, bebox_ide_interrupt))
|
||||
|
||||
@ -105,6 +105,13 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER( fdc_interrupt );
|
||||
DECLARE_FLOPPY_FORMATS( floppy_formats );
|
||||
|
||||
LSI53C810_FETCH_CB(scsi_fetch);
|
||||
LSI53C810_IRQ_CB(scsi_irq_callback);
|
||||
LSI53C810_DMA_CB(scsi_dma_callback);
|
||||
|
||||
void bebox_set_irq_bit(unsigned int interrupt_bit, int val);
|
||||
void bebox_update_interrupts();
|
||||
|
||||
protected:
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
};
|
||||
@ -119,8 +126,6 @@ extern const ins8250_interface bebox_uart_inteface_1;
|
||||
extern const ins8250_interface bebox_uart_inteface_2;
|
||||
extern const ins8250_interface bebox_uart_inteface_3;
|
||||
|
||||
void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int val);
|
||||
|
||||
UINT32 scsi53c810_pci_read(device_t *busdevice, device_t *device, int function, int offset, UINT32 mem_mask);
|
||||
void scsi53c810_pci_write(device_t *busdevice, device_t *device, int function, int offset, UINT32 data, UINT32 mem_mask);
|
||||
|
||||
|
||||
@ -116,8 +116,6 @@
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static void bebox_update_interrupts(running_machine &machine);
|
||||
|
||||
static void bebox_mbreg32_w(UINT32 *target, UINT64 data, UINT64 mem_mask)
|
||||
{
|
||||
int i;
|
||||
@ -163,7 +161,7 @@ WRITE64_MEMBER(bebox_state::bebox_cpu0_imask_w )
|
||||
logerror("BeBox CPU #0 pc=0x%08X imask=0x%08x\n",
|
||||
(unsigned) space.device().safe_pc( ), m_cpu_imask[0]);
|
||||
}
|
||||
bebox_update_interrupts(space.machine());
|
||||
bebox_update_interrupts();
|
||||
}
|
||||
}
|
||||
|
||||
@ -180,7 +178,7 @@ WRITE64_MEMBER(bebox_state::bebox_cpu1_imask_w )
|
||||
logerror("BeBox CPU #1 pc=0x%08X imask=0x%08x\n",
|
||||
(unsigned) space.device() .safe_pc( ), m_cpu_imask[1]);
|
||||
}
|
||||
bebox_update_interrupts(space.machine());
|
||||
bebox_update_interrupts();
|
||||
}
|
||||
}
|
||||
|
||||
@ -253,31 +251,28 @@ WRITE64_MEMBER(bebox_state::bebox_processor_resets_w )
|
||||
}
|
||||
|
||||
|
||||
static void bebox_update_interrupts(running_machine &machine)
|
||||
void bebox_state::bebox_update_interrupts()
|
||||
{
|
||||
bebox_state *state = machine.driver_data<bebox_state>();
|
||||
int cpunum;
|
||||
UINT32 interrupt;
|
||||
static const char *const cputags[] = { "ppc1", "ppc2" };
|
||||
|
||||
for (cpunum = 0; cpunum < 2; cpunum++)
|
||||
for (int cpunum = 0; cpunum < 2; cpunum++)
|
||||
{
|
||||
interrupt = state->m_interrupts & state->m_cpu_imask[cpunum];
|
||||
interrupt = m_interrupts & m_cpu_imask[cpunum];
|
||||
|
||||
if (LOG_INTERRUPTS)
|
||||
{
|
||||
logerror("\tbebox_update_interrupts(): CPU #%d [%08X|%08X] IRQ %s\n", cpunum,
|
||||
state->m_interrupts, state->m_cpu_imask[cpunum], interrupt ? "on" : "off");
|
||||
m_interrupts, m_cpu_imask[cpunum], interrupt ? "on" : "off");
|
||||
}
|
||||
|
||||
machine.device(cputags[cpunum])->execute().set_input_line(INPUT_LINE_IRQ0, interrupt ? ASSERT_LINE : CLEAR_LINE);
|
||||
machine().device(cputags[cpunum])->execute().set_input_line(INPUT_LINE_IRQ0, interrupt ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int val)
|
||||
void bebox_state::bebox_set_irq_bit(unsigned int interrupt_bit, int val)
|
||||
{
|
||||
bebox_state *state = machine.driver_data<bebox_state>();
|
||||
static const char *const interrupt_names[32] =
|
||||
{
|
||||
NULL,
|
||||
@ -321,21 +316,21 @@ void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int
|
||||
assert_always((interrupt_bit < ARRAY_LENGTH(interrupt_names)) && (interrupt_names[interrupt_bit] != NULL), "Raising invalid interrupt");
|
||||
|
||||
logerror("bebox_set_irq_bit(): pc[0]=0x%08x pc[1]=0x%08x %s interrupt #%u (%s)\n",
|
||||
(unsigned) machine.device("ppc1")->safe_pc(),
|
||||
(unsigned) machine.device("ppc2")->safe_pc(),
|
||||
(unsigned) machine().device("ppc1")->safe_pc(),
|
||||
(unsigned) machine().device("ppc2")->safe_pc(),
|
||||
val ? "Asserting" : "Clearing",
|
||||
interrupt_bit, interrupt_names[interrupt_bit]);
|
||||
}
|
||||
|
||||
old_interrupts = state->m_interrupts;
|
||||
old_interrupts = m_interrupts;
|
||||
if (val)
|
||||
state->m_interrupts |= 1 << interrupt_bit;
|
||||
m_interrupts |= 1 << interrupt_bit;
|
||||
else
|
||||
state->m_interrupts &= ~(1 << interrupt_bit);
|
||||
m_interrupts &= ~(1 << interrupt_bit);
|
||||
|
||||
/* if interrupt values have changed, update the lines */
|
||||
if (state->m_interrupts != old_interrupts)
|
||||
bebox_update_interrupts(machine);
|
||||
if (m_interrupts != old_interrupts)
|
||||
bebox_update_interrupts();
|
||||
}
|
||||
|
||||
|
||||
@ -394,7 +389,7 @@ const ins8250_interface bebox_uart_inteface_3 =
|
||||
|
||||
WRITE_LINE_MEMBER( bebox_state::fdc_interrupt )
|
||||
{
|
||||
bebox_set_irq_bit(machine(), 13, state);
|
||||
bebox_set_irq_bit(13, state);
|
||||
m_pic8259_1->ir6_w(state);
|
||||
}
|
||||
|
||||
@ -408,7 +403,7 @@ READ64_MEMBER(bebox_state::bebox_interrupt_ack_r )
|
||||
{
|
||||
UINT32 result;
|
||||
result = m_pic8259_1->acknowledge();
|
||||
bebox_set_irq_bit(space.machine(), 5, 0); /* HACK */
|
||||
bebox_set_irq_bit(5, 0); /* HACK */
|
||||
return ((UINT64) result) << 56;
|
||||
}
|
||||
|
||||
@ -421,7 +416,7 @@ READ64_MEMBER(bebox_state::bebox_interrupt_ack_r )
|
||||
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_pic8259_master_set_int_line)
|
||||
{
|
||||
bebox_set_irq_bit(machine(), 5, state);
|
||||
bebox_set_irq_bit(5, state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_pic8259_slave_set_int_line)
|
||||
@ -443,7 +438,7 @@ READ8_MEMBER(bebox_state::get_slave_ack)
|
||||
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_ide_interrupt)
|
||||
{
|
||||
bebox_set_irq_bit(machine(), 7, state);
|
||||
bebox_set_irq_bit(7, state);
|
||||
m_pic8259_1->ir6_w(state);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user