From 46883925092b3b805d160e2e4b79c95562b5fe87 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Banaan=20Ananas?= Date: Sat, 22 Feb 2014 20:29:45 +0000 Subject: [PATCH] improved i/o port skeleton stuff, taitofx1b sounds ok now --- src/emu/cpu/mn10200/mn10200.c | 216 +++++++++++++++++++--------------- src/emu/cpu/mn10200/mn10200.h | 64 ++++++---- src/emu/sound/zsg2.c | 2 +- src/mame/audio/taito_zm.c | 1 - 4 files changed, 164 insertions(+), 119 deletions(-) diff --git a/src/emu/cpu/mn10200/mn10200.c b/src/emu/cpu/mn10200/mn10200.c index ec6dc1e4d98..2d293b910f9 100644 --- a/src/emu/cpu/mn10200/mn10200.c +++ b/src/emu/cpu/mn10200/mn10200.c @@ -53,11 +53,29 @@ mn10200_device::mn10200_device(const machine_config &mconfig, const char *tag, d void mn10200_device::device_start() { - m_p4 = 0xf; - m_program = &space(AS_PROGRAM); m_io = &space(AS_IO); + // init and register for savestates + save_item(NAME(m_pc)); + save_item(NAME(m_d)); + save_item(NAME(m_a)); + save_item(NAME(m_psw)); + save_item(NAME(m_mdr)); + + // interrupts + memset(&m_icrl, 0, sizeof(m_icrl)); + memset(&m_icrh, 0, sizeof(m_icrh)); + + save_item(NAME(m_nmicr)); + save_item(NAME(m_iagr)); + save_item(NAME(m_extmdl)); + save_item(NAME(m_extmdh)); + save_item(NAME(m_icrl)); + save_item(NAME(m_icrh)); + save_item(NAME(m_possible_irq)); + + // timers m_sysclock_base = attotime::from_hz(unscaled_clock() / 2); for (int tmr = 0; tmr < MN10200_NUM_TIMERS_8BIT; tmr++) @@ -66,12 +84,6 @@ void mn10200_device::device_start() m_timer_timers[tmr]->adjust(attotime::never, tmr); } - // zerofill, register for savestates - for (int i = 0; i < MN10200_NUM_IRQ_GROUPS; i++) - { - m_icrl[i] = 0; - m_icrh[i] = 0; - } for (int i = 0; i < MN10200_NUM_TIMERS_8BIT; i++) { m_simple_timer[i].mode = 0; @@ -82,6 +94,7 @@ void mn10200_device::device_start() save_item(NAME(m_simple_timer[i].base), i); save_item(NAME(m_simple_timer[i].cur), i); } + for (int i = 0; i < MN10200_NUM_PRESCALERS; i++) { m_prescaler[i].mode = 0; @@ -92,6 +105,8 @@ void mn10200_device::device_start() save_item(NAME(m_prescaler[i].base), i); save_item(NAME(m_prescaler[i].cur), i); } + + // dma for (int i = 0; i < 8; i++) { m_dma[i].adr = 0; @@ -108,6 +123,8 @@ void mn10200_device::device_start() save_item(NAME(m_dma[i].ctrlh), i); save_item(NAME(m_dma[i].irq), i); } + + // serial for (int i = 0; i < 2; i++) { m_serial[i].ctrll = 0; @@ -118,25 +135,23 @@ void mn10200_device::device_start() save_item(NAME(m_serial[i].ctrlh), i); save_item(NAME(m_serial[i].buf), i); } - for (int i = 0; i < 8; i++) - { - m_ddr[i] = 0; - } + + // ports + m_p4 = 0xf; - save_item(NAME(m_pc)); - save_item(NAME(m_d)); - save_item(NAME(m_a)); - save_item(NAME(m_psw)); - save_item(NAME(m_mdr)); - save_item(NAME(m_nmicr)); - save_item(NAME(m_iagr)); + save_item(NAME(m_pplul)); + save_item(NAME(m_ppluh)); + save_item(NAME(m_p3md)); save_item(NAME(m_p4)); - save_item(NAME(m_extmdl)); - save_item(NAME(m_extmdh)); - save_item(NAME(m_icrl)); - save_item(NAME(m_icrh)); - save_item(NAME(m_ddr)); - save_item(NAME(m_possible_irq)); + + for (int i = 0; i < 4; i++) + { + m_port[i].out = 0; + m_port[i].dir = 0; + + save_item(NAME(m_port[i].out), i); + save_item(NAME(m_port[i].dir), i); + } // register for debugger state_add( MN10200_PC, "PC", m_pc ).mask(0xffffff).formatstr("%06X"); @@ -1639,7 +1654,7 @@ void mn10200_device::execute_run() WRITE8_MEMBER(mn10200_device::io_control_w) { - switch(offset) + switch (offset) { case 0x000: if(data & 12) @@ -1661,7 +1676,7 @@ WRITE8_MEMBER(mn10200_device::io_control_w) case 0x036: case 0x037: // Memory mode reg 3 break; - // 0xfc40-0xfc57: irq control + // irq control // group 0, NMI control case 0x040: m_nmicr &= data; // nmi ack @@ -1742,7 +1757,7 @@ WRITE8_MEMBER(mn10200_device::io_control_w) log_event("MN102", "AN chans=0-%d current=%d", (data >> 4) & 7, data & 7); break; - // 0xfe00-0xfe2f: 8-bit timers + // 8-bit timers // timer base case 0x210: case 0x211: case 0x212: case 0x213: case 0x214: case 0x215: case 0x216: case 0x217: case 0x218: case 0x219: @@ -1843,10 +1858,6 @@ WRITE8_MEMBER(mn10200_device::io_control_w) log_event("MN102", "Sync Output buffer = %02x", data); break; - case 0x264: - m_io->write_byte(MN10200_PORT1, data); - break; - case 0x280: case 0x290: case 0x2a0: case 0x2b0: case 0x2c0: case 0x2d0: case 0x2e0: case 0x2f0: { int dma = (offset-0x280) >> 4; @@ -1971,27 +1982,6 @@ WRITE8_MEMBER(mn10200_device::io_control_w) case 0x28d: case 0x29d: case 0x2ad: case 0x2bd: case 0x2cd: case 0x2dd: case 0x2ed: case 0x2fd: break; - case 0x3b0: - log_event("MN102", "Pull-ups 0-7 = -%c%c%c%c%c%c%c", - data & 0x40 ? '#' : '.', - data & 0x20 ? '#' : '.', - data & 0x10 ? '#' : '.', - data & 0x08 ? '#' : '.', - data & 0x04 ? '#' : '.', - data & 0x02 ? '#' : '.', - data & 0x01 ? '#' : '.'); - break; - - case 0x3b1: - log_event("MN102", "Pull-ups 8-f = --%c%c%c%c%c%c", - data & 0x20 ? '#' : '.', - data & 0x10 ? '#' : '.', - data & 0x08 ? '#' : '.', - data & 0x04 ? '#' : '.', - data & 0x02 ? '#' : '.', - data & 0x01 ? '#' : '.'); - break; - case 0x3b2: log_event("MN102", "Timer I/O 4-0 = %c%c%c%c%c", data & 0x10 ? 'o' : 'i', @@ -2011,41 +2001,46 @@ WRITE8_MEMBER(mn10200_device::io_control_w) data & 0x01 ? 'o' : 'i'); break; - case 0x3c0: // port 0 data - m_io->write_byte(MN10200_PORT0, data); + // ports + // pull-up control + case 0x3b0: + m_pplul = data & 0x7f; + break; + case 0x3b1: + m_ppluh = data & 0x3f; break; - case 0x3c2: // port 2 data - m_io->write_byte(MN10200_PORT2, data); + // outputs + case 0x3c0: + m_port[0].out = data; + m_io->write_byte(MN10200_PORT0, m_port[0].out | (m_port[0].dir ^ 0xff)); + break; + case 0x264: + m_port[1].out = data; + m_io->write_byte(MN10200_PORT1, m_port[1].out | (m_port[1].dir ^ 0xff)); + break; + case 0x3c2: + m_port[2].out = data & 0x0f; + m_io->write_byte(MN10200_PORT2, m_port[2].out | (m_port[2].dir ^ 0x0f)); + break; + case 0x3c3: + m_port[3].out = data & 0x1f; + m_io->write_byte(MN10200_PORT3, m_port[3].out | (m_port[3].dir ^ 0x1f)); break; - case 0x3c3: // port 3 data - m_io->write_byte(MN10200_PORT3, data); - break; - - case 0x3e0: // port0 ddr - m_ddr[0] = data; - break; - - case 0x3e1: // port1 ddr - m_ddr[1] = data; - break; - - case 0x3e2: // port2 ddr - m_ddr[2] = data; - break; - - case 0x3e3: // port3 ddr - m_ddr[3] = data; - break; + // directions (0=input, 1=output) + case 0x3e0: + m_port[0].dir = data; + case 0x3e1: + m_port[1].dir = data; + case 0x3e2: + m_port[2].dir = data & 0x0f; + case 0x3e3: + m_port[3].dir = data & 0x1f; + // port 3 output mode case 0x3f3: - // log_event("MN102", "Port 3 bits 4=%s 3=%s 2=%s 1=%s 0=%s", - // data & 0x10 ? data & 0x40 ? "serial_1" : "tm9" : "p34", - // data & 0x08 ? data & 0x20 ? "serial_0" : "tm8" : "p33", - // data & 0x04 ? "tm7" : "p32", - // data & 0x04 ? "tm6" : "p31", - // data & 0x04 ? "tm5" : "p30"); + m_p3md = data & 0x7f; break; @@ -2059,7 +2054,7 @@ WRITE8_MEMBER(mn10200_device::io_control_w) READ8_MEMBER(mn10200_device::io_control_r) { - switch(offset) + switch (offset) { // active irq group case 0x00e: @@ -2067,7 +2062,7 @@ READ8_MEMBER(mn10200_device::io_control_r) case 0x00f: return 0; - // 0xfc40-0xfc57: irq control + // irq control // group 0, NMI control case 0x040: return m_nmicr; @@ -2105,7 +2100,7 @@ READ8_MEMBER(mn10200_device::io_control_r) case 0x183: return 0x10; - // 0xfe00-0xfe2f: 8-bit timers + // 8-bit timers // timer counter (not accurate) case 0x200: case 0x201: case 0x202: case 0x203: case 0x204: case 0x205: case 0x206: case 0x207: case 0x208: case 0x209: @@ -2133,23 +2128,56 @@ READ8_MEMBER(mn10200_device::io_control_r) case 0x22a: case 0x22b: return m_prescaler[offset & 1].mode; - case 0x264: // port 1 data - return m_io->read_byte(MN10200_PORT1); - case 0x28c: case 0x29c: case 0x2ac: case 0x2bc: case 0x2cc: case 0x2dc: case 0x2ec: case 0x2fc: { int dma = (offset-0x280) >> 4; return m_dma[dma].irq; } - case 0x3c0: // port 0 data - return m_io->read_byte(MN10200_PORT0); + // ports + // pull-up control + case 0x3b0: + return m_pplul; + break; + case 0x3b1: + return m_ppluh; + break; - case 0x3c2: // port 2 data - return m_io->read_byte(MN10200_PORT2); + // outputs + case 0x3c0: + return m_port[0].out; + case 0x264: + return m_port[1].out; + case 0x3c2: + return m_port[2].out; + case 0x3c3: + return m_port[3].out; + + // inputs + case 0x3d0: + return m_io->read_byte(MN10200_PORT0) | m_port[0].dir; + case 0x3d1: + return m_io->read_byte(MN10200_PORT1) | m_port[1].dir; + case 0x3d2: + return (m_io->read_byte(MN10200_PORT2) & 0x0f) | m_port[2].dir; + case 0x3d3: + return (m_io->read_byte(MN10200_PORT3) & 0x1f) | m_port[3].dir; + + // directions (0=input, 1=output) + case 0x3e0: + return m_port[0].dir; + case 0x3e1: + return m_port[1].dir; + case 0x3e2: + return m_port[2].dir; + case 0x3e3: + return m_port[3].dir; + + // port 3 output mode + case 0x3f3: + return m_p3md; + break; - case 0x3c3: // port 3 data - return m_io->read_byte(MN10200_PORT3); default: log_event("MN102", "internal_r %04x (%03x)", offset+0xfc00, adr); diff --git a/src/emu/cpu/mn10200/mn10200.h b/src/emu/cpu/mn10200/mn10200.h index 49d9413947b..51b3078ca71 100644 --- a/src/emu/cpu/mn10200/mn10200.h +++ b/src/emu/cpu/mn10200/mn10200.h @@ -97,36 +97,49 @@ private: address_space_config m_program_config; address_space_config m_io_config; + address_space *m_program; + address_space *m_io; + + int m_cycles; + // The UINT32s are really UINT24 UINT32 m_pc; UINT32 m_d[4]; UINT32 m_a[4]; - - UINT8 m_p4; - UINT8 m_extmdl; - UINT8 m_extmdh; - UINT8 m_nmicr; - UINT8 m_iagr; - UINT8 m_icrl[MN10200_NUM_IRQ_GROUPS]; - UINT8 m_icrh[MN10200_NUM_IRQ_GROUPS]; UINT16 m_psw; UINT16 m_mdr; - struct { + // interrupts + UINT8 m_icrl[MN10200_NUM_IRQ_GROUPS]; + UINT8 m_icrh[MN10200_NUM_IRQ_GROUPS]; + + UINT8 m_nmicr; + UINT8 m_iagr; + UINT8 m_extmdl; + UINT8 m_extmdh; + bool m_possible_irq; + + // timers + attotime m_sysclock_base; + emu_timer *m_timer_timers[MN10200_NUM_TIMERS_8BIT]; + + struct + { UINT8 mode; UINT8 base; UINT8 cur; } m_simple_timer[MN10200_NUM_TIMERS_8BIT]; - emu_timer *m_timer_timers[MN10200_NUM_TIMERS_8BIT]; - - struct { + struct + { UINT8 mode; UINT8 base; UINT8 cur; } m_prescaler[MN10200_NUM_PRESCALERS]; - struct { + // dma + struct + { UINT32 adr; UINT32 count; UINT16 iadr; @@ -135,21 +148,26 @@ private: UINT8 irq; } m_dma[8]; - struct { + // serial + struct + { UINT8 ctrll; UINT8 ctrlh; UINT8 buf; } m_serial[2]; + + // ports + UINT8 m_pplul; + UINT8 m_ppluh; + UINT8 m_p3md; + UINT8 m_p4; - UINT8 m_ddr[8]; - - bool m_possible_irq; - attotime m_sysclock_base; - int m_cycles; - - address_space *m_program; - address_space *m_io; - + struct + { + UINT8 out; + UINT8 dir; + } m_port[4]; + // internal read/write inline UINT8 read_arg8(UINT32 address) { return m_program->read_byte(address); } inline UINT16 read_arg16(UINT32 address) { return m_program->read_byte(address) | m_program->read_byte(address + 1) << 8; } diff --git a/src/emu/sound/zsg2.c b/src/emu/sound/zsg2.c index cc143f31cc5..6fa7ae64dff 100644 --- a/src/emu/sound/zsg2.c +++ b/src/emu/sound/zsg2.c @@ -45,7 +45,7 @@ --------------------------------------------------------- TODO: -- volume/panning is linear? +- volume/panning is linear? volume slides are too steep - what is reg 0xa/0xc? seems related to volume - identify sample flags - memory reads out of range sometimes diff --git a/src/mame/audio/taito_zm.c b/src/mame/audio/taito_zm.c index b54e4bc0337..9da4d49f9b2 100644 --- a/src/mame/audio/taito_zm.c +++ b/src/mame/audio/taito_zm.c @@ -25,7 +25,6 @@ and a Zoom Corp. ZFX-2 DSP instead of the TMS57002. TODO: - add DSP, sound is tinny without it -- howcome taito fx1b sounds worse than gnet? especially raystorm ***************************************************************************/