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https://github.com/holub/mame
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ti99_8: OSO implementation completed; pending tests (nw)
This commit is contained in:
Michael Zapf
parent
8593fdceab
commit
46958737cf
@ -2243,6 +2243,15 @@ enum
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CR7 = 0x01
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};
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/* Line */
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enum
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{
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LINE_HSK = 0x10,
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LINE_BAV = 0x04,
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LINE_BIT32 = 0xc0,
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LINE_BIT10 = 0x03
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};
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oso_device::oso_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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bus::hexbus::hexbus_chained_device(mconfig, TI99_OSO, tag, owner, clock),
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m_int(*this),
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@ -2250,17 +2259,16 @@ oso_device::oso_device(const machine_config &mconfig, const char *tag, device_t
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m_status(0xff),
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m_control(0),
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m_xmit(0), m_lasthxvalue(0x01),
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m_clkcount(0),
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m_sbav(false), m_sbavold(true),
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m_bav(false), m_bavhold(false),
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m_shsk(false), m_shskold(true),
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m_hsk(false), m_hskhold(false),
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m_bav(false), m_sbav(false), m_sbavold(true), m_bavhold(false),
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m_hsk(false), m_shsk(false), m_shskold(true), m_hskhold(false),
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m_wq1(false), m_wq1old(true), m_wq2(false), m_wq2old(true),
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m_wnp(false),
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m_wbusy(false), m_wbusyold(false),
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m_sendbyte(false),
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m_wrst(false), m_counting(false),
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m_rq2(false), m_rq2old(true)
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m_wnp(false), m_wbusyold(false), m_sendbyte(false),
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m_wrset(false), m_counting(false), m_clkcount(0),
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m_rq1(false), m_rq2(false), m_rq2old(true),
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m_rnib(false), m_rnibcold(false),
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m_rdset(false), m_rdsetold(true),
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m_msns(false), m_lsns(false),
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m_rdend(false), m_byteavailable(false)
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{
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(void)m_shskold;
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m_hexbus_inbound = nullptr;
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@ -2277,6 +2285,8 @@ READ8_MEMBER( oso_device::read )
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// read 5FF8: read data register
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if (TRACE_OSO) logerror("Read data register = %02x\n", value);
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value = m_data;
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// Release the handshake
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m_byteavailable = false;
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break;
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case 1:
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// read 5FFA: read status register
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@ -2314,9 +2324,8 @@ WRITE8_MEMBER( oso_device::write )
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m_sendbyte = true;
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if (!m_wq1)
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{
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m_wbusy = true;
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m_wbusyold = true;
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set_status(WBUSY, m_wbusy);
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set_status(WBUSY, true);
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}
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m_xmit = data;
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@ -2327,12 +2336,16 @@ WRITE8_MEMBER( oso_device::write )
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data, (data & WIEN)? 1:0, (data & RIEN)? 1:0, (data&BAVIAEN)? 1:0, (data&BAVAIEN)? 1:0,
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(data & BAVC)? 1:0, (data & WEN)? 1:0, (data & REN)? 1:0);
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m_control = data;
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// Reset some flipflops in the write/read timing section
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if (!control_bit(WEN))
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{
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// Reset some flipflops in the write timing section
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m_wq1 = m_wq2 = m_wrst = false;
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m_wq1 = m_wq2 = m_wrset = false;
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}
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if (!control_bit(REN))
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{
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m_rq1 = m_rq2 = m_rdset = false;
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}
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m_bav = control_bit(BAVC);
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break;
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default:
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// write 5FFC, 5FFE: undefined
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@ -2344,12 +2357,22 @@ WRITE8_MEMBER( oso_device::write )
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void oso_device::clear_int_status()
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{
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m_status &= ~(HSKWT | HSKRD | BAVIAS | BAVAIS);
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m_rdend = false;
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m_int(CLEAR_LINE);
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}
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void oso_device::hexbus_value_changed(uint8_t data)
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{
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if (TRACE_OSO) logerror("Hexbus value changed to %02x\n", data);
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m_bav = ((data & LINE_BAV)==0) | control_bit(BAVC);
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m_hsk = (data & LINE_HSK)==0;
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int nibble = ((data & LINE_BIT32)>>4) | (data & LINE_BIT10);
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if (m_msns)
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m_data = (m_data & 0x0f) | (nibble<<4);
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if (m_lsns)
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m_data = (m_data & 0xf0) | nibble;
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}
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/*
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@ -2363,13 +2386,21 @@ WRITE_LINE_MEMBER( oso_device::clock_in )
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// When BAV/HSK is 0/1 for two rising edges of Phi3*, SBAV/SHSK goes to
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// 0/1 at the following falling edge of Phi3*.
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// Page 5
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m_sbav = m_bavhold && m_bav;
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m_sbav = m_bavhold && m_bav; // could mean "stable BAV"
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m_bavhold = m_bav;
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m_shsk = m_hskhold && m_hsk;
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m_hskhold = m_hsk;
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set_status(SHSK, m_shsk);
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set_status(SBAV, m_sbav);
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// Raising edge of SBAV*
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if (m_sbav == true && m_sbavold == false)
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set_status(BAVIAS, true);
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// Falling edge of SBAV*
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if (m_sbav == false && m_sbavold == true)
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set_status(BAVAIS, true);
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m_sbavold = m_sbav;
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// Implement the write timing logic
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// This subcircuit in the OSO chip autonomously runs the Hexbus
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// protocol. After loading a byte into the transmit register, it sends
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@ -2382,11 +2413,11 @@ WRITE_LINE_MEMBER( oso_device::clock_in )
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if (control_bit(WEN)) // Nothing happens without WEN
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{
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if (TRACE_OSO) if (!m_wrst && m_sendbyte) logerror("Starting write process\n");
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if (TRACE_OSO) if (!m_wrset && m_sendbyte) logerror("Starting write process\n");
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// Page 3: Write timing
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// Note: First pass counts to 30, second to 31
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bool cnt30 = ((m_clkcount & 0x1e) == 30);
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bool cont = (m_wrst && !m_wq2 && !m_wq1) || (cnt30 && m_wq2 && !m_wq1)
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bool cont = (m_wrset && !m_wq2 && !m_wq1) || (cnt30 && m_wq2 && !m_wq1)
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|| (cnt30 && !m_wq2 && m_wq1) || (m_shsk && m_wq2 && m_wq1);
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bool jwq1 = cont && m_wq2;
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@ -2401,37 +2432,17 @@ WRITE_LINE_MEMBER( oso_device::clock_in )
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if (m_wq1 == true)
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m_sendbyte = false;
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// logerror("sendbyte=%d, wq1=%d, wq2=%d, jwq1=%d, kwq1=%d, jwq2=%d, kwq2=%d, shsk=%d\n", m_sendbyte, m_wq1, m_wq2, jwq1, kwq1, jwq2, kwq2, m_shsk);
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// WBUSY is asserted on byte load, during phase 1, and phase 2.
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m_wbusy = m_sendbyte || m_wq1 || m_wq2;
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bool wbusy = m_sendbyte || m_wq1 || m_wq2;
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// Set status bits and raise interrupt (p. 4)
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set_status(WBUSY, m_wbusy);
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if (m_wbusy != m_wbusyold)
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{
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// Raising edge of wbusy*
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if (!m_wbusy) set_status(HSKWT, !m_wbusy);
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m_wbusyold = m_wbusy;
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}
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set_status(WBUSY, wbusy);
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if (m_rq2 != m_rq2old)
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{
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// Raising edge of RQ2*
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if (!m_rq2)
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{
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set_status(HSKRD, m_rq2);
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}
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m_wbusyold = m_wbusy;
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}
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if (m_sbav != m_sbavold)
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{
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// Raising edge of SBAV -> BAVIA
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// Falling edge of SBAV -> BAVAI
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if (m_sbav)
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set_status(BAVIAS, m_sbav);
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else
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set_status(BAVAIS, !m_sbav);
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}
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// Raising edge of wbusy*
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if (m_wbusyold == true && wbusy == false)
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set_status(HSKWT, true);
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m_wbusyold = wbusy;
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// Operate flipflops
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// Write phases
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@ -2462,26 +2473,80 @@ WRITE_LINE_MEMBER( oso_device::clock_in )
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}
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m_wq1old = m_wq1;
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// Set HSK
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m_hsk = !m_wq1 && m_wq2;
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// Reset WNP if phases are done
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if (!m_wq2 && !m_wq1)
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{
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m_wnp = false;
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}
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update_hexbus();
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}
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// This is the reading behavior. In this case, the master (this
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// component) pulls down BAV*, then the slave sets the data lines
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// with the back nibble, pulls down HSK*, then releases HSK*,
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// puts the front nibble on the data lines, pulls down HSK* again,
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// releases it, and this continues until the master releases BAV*
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if (control_bit(REN))
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{
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bool rbusy = m_rq1 || m_rq2;
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set_status(RBUSY, rbusy);
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// Flipflop resets
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if (!rbusy) m_rnib = false;
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if (m_rq2) m_rdset = false;
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bool rdsetin = !control_bit(WBUSY) && m_sbav && m_shsk;
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bool next = (m_rdset && !m_rq2) || (m_shsk && m_rq2);
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bool drq1 = (next && m_rq2) || (m_rq2 && m_rq1 && !m_rnib);
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bool jrq2 = next && !m_rq1;
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bool krq2 = m_rq1 && !m_rnib;
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m_msns = m_rnib && !m_rq1 && m_rq2;
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m_lsns = !m_rnib && !m_rq1 && m_rq2;
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bool rnibc = m_rq1;
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// Next state
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if (!m_rdsetold && rdsetin) m_rdset = true; // raising edge
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m_rdsetold = rdsetin;
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m_rq1 = drq1;
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if (jrq2)
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{
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if (!krq2) m_rq2 = !m_rq2;
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else m_rq2 = true;
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}
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else
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if (!krq2) m_rq2 = false;
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if (m_rnibcold == false && rnibc == true) m_rnib = !m_rnib; // raising edge
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m_rnibcold = rnibc;
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// Raising edge of RQ2*
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if (m_rq2old == true && m_rq2 == false)
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{
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set_status(HSKRD, true);
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m_rdend = true;
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}
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m_rq2old = m_rq2;
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}
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else
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{
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m_wq1 = m_wq2 = m_wrst = m_counting = false;
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m_clkcount = 0;
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m_byteavailable = false;
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}
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// Handshake control
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// Set HSK (Page 6, RHSUS*)
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bool hskwrite = !m_wq1 && m_wq2;
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if (m_rdend) m_byteavailable = true;
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// We can simplify this to a single flag because the CPU read operation
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// is atomic here (starts and immediately terminates)
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m_hsk = hskwrite || m_byteavailable;
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update_hexbus();
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}
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// Actions that occur for Phi3=0
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else
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{
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m_wrst = m_sendbyte;
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m_wrset = m_sendbyte;
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// Only count when one phase is active
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m_counting = !(m_wq1==m_wq2);
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@ -2491,6 +2556,17 @@ WRITE_LINE_MEMBER( oso_device::clock_in )
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m_clkcount = 0; // Reset when not counting
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}
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// Flipflop resets (not related to clock)
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if (!control_bit(WEN))
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{
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m_wq1 = m_wq2 = m_wrset = m_counting = false;
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m_clkcount = 0;
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}
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if (!control_bit(REN))
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{
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m_rq1 = m_rq2 = m_rdset = false;
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}
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// Show some lines in log
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if (TRACE_OSO) {
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if (m_sbav != m_sbavold) {
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@ -2517,7 +2593,7 @@ void oso_device::update_hexbus()
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value = ((m_xmit & 0x0c)<<4) | (m_xmit & 0x03);
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if (!m_hsk) value |= 0x10;
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if (!m_bav) value |= 0x04;
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if (!control_bit(BAVC)) value |= 0x04;
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if (value != m_lasthxvalue)
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{
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if (TRACE_OSO) logerror("Set hexbus = %02x (BAV*=%d, HSK*=%d, data=%01x)\n", value, (value & 0x04)? 1:0, (value & 0x10)? 1:0, ((value>>4)&0x0c) | (value&0x03));
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@ -446,41 +446,52 @@ private:
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void set_status(int bit, bool set) { m_status = (set)? (m_status | bit) : (m_status & ~bit); }
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void update_hexbus();
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// Registers
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uint8_t m_data;
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uint8_t m_status;
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uint8_t m_control;
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uint8_t m_xmit;
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// Last hexbus value; when the new value is different, send it via the hexbus
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uint8_t m_lasthxvalue;
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int m_clkcount;
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bool m_bav; // Bus available; when true, a communication is about to happen
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bool m_sbav; // Stable BAV; the BAV signal is true for two clock cycles
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bool m_sbavold; // Old SBAV state
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bool m_bavhold; // For computing the SBAV signal
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bool m_sbav;
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bool m_sbavold;
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bool m_bav;
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bool m_bavhold;
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bool m_hsk; // Handshake line; when true, a bus member needs more time to process the message
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bool m_shsk; // Stable HSK
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bool m_shskold; // see above
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bool m_hskhold; // see above
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bool m_shsk;
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bool m_shskold;
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bool m_hsk;
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bool m_hskhold;
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// Page 3 in OSO schematics: Write timing
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bool m_wq1; // Flipflop 1
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bool m_wq1old; // Previous state
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bool m_wq2; // Flipflop 2
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bool m_wq2old; // Previous state
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bool m_wnp; // Write nibble selection; true means upper 4 bits
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bool m_wbusyold; // Old state of the WBUSY line
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bool m_sendbyte; // Byte has been loaded into the XMIT register
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bool m_wrset; // Start sending
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bool m_counting; // Counter running
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int m_clkcount; // Counter for 30 cycles
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// Page 3 in OSO schematics
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bool m_wq1;
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bool m_wq1old;
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bool m_wq2;
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bool m_wq2old;
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bool m_wnp;
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bool m_wbusy;
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bool m_wbusyold;
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bool m_sendbyte;
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// Page 4 in OSO schematics: Read timing
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bool m_rq1; // Flipflop 1
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bool m_rq2; // Flipflop 2
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bool m_rq2old; // Previous state
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bool m_rnib; // Read nibble, true means upper 4 bits
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bool m_rnibcold; // Needed to detect the raising edge
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bool m_rdset; // Start reading
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bool m_rdsetold; // Old state
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bool m_msns; // Upper 4 bits
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bool m_lsns; // Lower 4 bits
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bool m_wrst;
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bool m_rdend; // Read completed
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bool m_counting;
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bool m_rq2;
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bool m_rq2old;
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// Page 6
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bool m_byteavailable; // Needed to assert the HSK line until the CPU has read the byte
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};
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class mainboard8_device : public device_t
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