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Fixed compile. (nw)
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@ -368,8 +368,6 @@ UINT8 vic20_final_expansion_3_t::vic20_cd_r(address_space &space, offs_t offset,
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void vic20_final_expansion_3_t::vic20_cd_w(address_space &space, offs_t offset, UINT8 data, int ram1, int ram2, int ram3, int blk1, int blk2, int blk3, int blk5, int io2, int io3)
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{
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offs_t addr = 0;
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switch (m_reg1 & REG1_MODE_MASK)
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{
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case REG1_START:
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@ -389,8 +387,6 @@ void vic20_final_expansion_3_t::vic20_cd_w(address_space &space, offs_t offset,
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break;
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case REG1_SUPER_ROM:
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addr = 0x8000 | offset;
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// write to RAM bank 0
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if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
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{
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