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resolve merge conflicts (nw)

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This commit is contained in:
MetalliC 2017-12-27 14:54:01 +02:00
parent e6635b97b5
commit 46dd902fba
1 changed files with 14 additions and 17 deletions
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31
src/devices/cpu/arm7/arm7thmb.cpp
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@ -977,7 +977,7 @@ void arm7_cpu_device::tg05_0(uint32_t pc, uint32_t op) /* STR Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT; uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT; uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm); uint32_t addr = GetRegister(rn) + GetRegister(rm);
WRITE32(addr & ~3, GetRegister(rd)); WRITE32(addr, GetRegister(rd));
R15 += 2; R15 += 2;
} }
@ -987,7 +987,7 @@ void arm7_cpu_device::tg05_1(uint32_t pc, uint32_t op) /* STRH Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT; uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT; uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm); uint32_t addr = GetRegister(rn) + GetRegister(rm);
WRITE16(addr & ~1, GetRegister(rd)); WRITE16(addr, GetRegister(rd));
R15 += 2; R15 += 2;
} }
@ -1022,9 +1022,8 @@ void arm7_cpu_device::tg05_4(uint32_t pc, uint32_t op) /* LDR Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT; uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT; uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm); uint32_t addr = GetRegister(rn) + GetRegister(rm);
uint32_t tmp = READ32(addr & ~3); uint32_t op2 = READ32(addr);
addr = (addr & 3) << 3; SetRegister(rd, op2);
SetRegister(rd, ROR(tmp, addr));
R15 += 2; R15 += 2;
} }
@ -1034,7 +1033,7 @@ void arm7_cpu_device::tg05_5(uint32_t pc, uint32_t op) /* LDRH Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT; uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT; uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm); uint32_t addr = GetRegister(rn) + GetRegister(rm);
uint32_t op2 = READ16(addr & ~1); uint32_t op2 = READ16(addr);
SetRegister(rd, op2); SetRegister(rd, op2);
R15 += 2; R15 += 2;
} }
@ -1070,7 +1069,7 @@ void arm7_cpu_device::tg06_0(uint32_t pc, uint32_t op) /* Store */
uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT; uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
uint32_t rd = op & THUMB_ADDSUB_RD; uint32_t rd = op & THUMB_ADDSUB_RD;
int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2; int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
WRITE32((GetRegister(rn) + offs) & ~3, GetRegister(rd)); WRITE32(GetRegister(rn) + offs, GetRegister(rd));
R15 += 2; R15 += 2;
} }
@ -1078,10 +1077,8 @@ void arm7_cpu_device::tg06_1(uint32_t pc, uint32_t op) /* Load */
{ {
uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT; uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
uint32_t rd = op & THUMB_ADDSUB_RD; uint32_t rd = op & THUMB_ADDSUB_RD;
uint32_t addr = GetRegister(rn) + (((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2); int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
uint32_t tmp = READ32(addr & ~3); SetRegister(rd, READ32(GetRegister(rn) + offs)); // fix
addr = (addr & 3) << 3;
SetRegister(rd, ROR(tmp, addr));
R15 += 2; R15 += 2;
} }
@ -1112,7 +1109,7 @@ void arm7_cpu_device::tg08_0(uint32_t pc, uint32_t op) /* Store */
uint32_t imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT; uint32_t imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT; uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT; uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
WRITE16((GetRegister(rs) + (imm << 1)) & ~1, GetRegister(rd)); WRITE16(GetRegister(rs) + (imm << 1), GetRegister(rd));
R15 += 2; R15 += 2;
} }
@ -1121,7 +1118,7 @@ void arm7_cpu_device::tg08_1(uint32_t pc, uint32_t op) /* Load */
uint32_t imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT; uint32_t imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT; uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT; uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
SetRegister(rd, READ16((GetRegister(rs) + (imm << 1)) & ~1)); SetRegister(rd, READ16(GetRegister(rs) + (imm << 1)));
R15 += 2; R15 += 2;
} }
@ -1131,7 +1128,7 @@ void arm7_cpu_device::tg09_0(uint32_t pc, uint32_t op) /* Store */
{ {
uint32_t rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT; uint32_t rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
int32_t offs = (uint8_t)(op & THUMB_INSN_IMM); int32_t offs = (uint8_t)(op & THUMB_INSN_IMM);
WRITE32((GetRegister(13) + ((uint32_t)offs << 2)) & ~3, GetRegister(rd)); WRITE32(GetRegister(13) + ((uint32_t)offs << 2), GetRegister(rd));
R15 += 2; R15 += 2;
} }
@ -1194,7 +1191,7 @@ void arm7_cpu_device::tg0b_4(uint32_t pc, uint32_t op) /* PUSH {Rlist} */
if (op & (1 << offs)) if (op & (1 << offs))
{ {
SetRegister(13, GetRegister(13) - 4); SetRegister(13, GetRegister(13) - 4);
WRITE32(GetRegister(13) & ~3, GetRegister(offs)); WRITE32(GetRegister(13), GetRegister(offs));
} }
} }
R15 += 2; R15 += 2;
@ -1203,13 +1200,13 @@ void arm7_cpu_device::tg0b_4(uint32_t pc, uint32_t op) /* PUSH {Rlist} */
void arm7_cpu_device::tg0b_5(uint32_t pc, uint32_t op) /* PUSH {Rlist}{LR} */ void arm7_cpu_device::tg0b_5(uint32_t pc, uint32_t op) /* PUSH {Rlist}{LR} */
{ {
SetRegister(13, GetRegister(13) - 4); SetRegister(13, GetRegister(13) - 4);
WRITE32(GetRegister(13) & ~3, GetRegister(14)); WRITE32(GetRegister(13), GetRegister(14));
for (int32_t offs = 7; offs >= 0; offs--) for (int32_t offs = 7; offs >= 0; offs--)
{ {
if (op & (1 << offs)) if (op & (1 << offs))
{ {
SetRegister(13, GetRegister(13) - 4); SetRegister(13, GetRegister(13) - 4);
WRITE32(GetRegister(13) & ~3, GetRegister(offs)); WRITE32(GetRegister(13), GetRegister(offs));
} }
} }
R15 += 2; R15 += 2;