From 479454ad8fe817bcf6bf898909a880c9f0b51278 Mon Sep 17 00:00:00 2001 From: Robbbert Date: Thu, 9 Oct 2014 03:12:07 +0000 Subject: [PATCH] gts80.c : WIP --- src/mame/drivers/gts80.c | 245 +++++++++++++++++++++++++++++++++++-- src/mame/drivers/spectra.c | 4 +- src/mame/layout/gts80.lay | 39 +++--- 3 files changed, 260 insertions(+), 28 deletions(-) diff --git a/src/mame/drivers/gts80.c b/src/mame/drivers/gts80.c index 03716845d70..aab743f16ef 100644 --- a/src/mame/drivers/gts80.c +++ b/src/mame/drivers/gts80.c @@ -5,7 +5,10 @@ ToDO: -- Everything +- Switches +- Outputs +- Mechanical sounds +- Sound ************************************************************************************************************/ @@ -33,6 +36,10 @@ public: DECLARE_WRITE8_MEMBER(port3a_w); DECLARE_WRITE8_MEMBER(port3b_w); private: + UINT8 m_port2; + UINT8 m_segment; + UINT8 m_row; + UINT8 m_kbdrow; virtual void machine_reset(); required_device m_maincpu; }; @@ -44,37 +51,256 @@ static ADDRESS_MAP_START( gts80_map, AS_PROGRAM, 8, gts80_state ) AM_RANGE(0x0280, 0x02ff) AM_DEVREADWRITE("riot2", riot6532_device, read, write) AM_RANGE(0x0300, 0x037f) AM_DEVREADWRITE("riot3", riot6532_device, read, write) AM_RANGE(0x1000, 0x17ff) AM_ROM - AM_RANGE(0x1800, 0x18ff) AM_RAM AM_MIRROR(0x700) // the existence of this ram isn't confirmed yet + AM_RANGE(0x1800, 0x18ff) AM_RAM AM_SHARE("nvram") // 5101L-1 256x4 AM_RANGE(0x2000, 0x2fff) AM_ROM AM_RANGE(0x3000, 0x3fff) AM_ROM ADDRESS_MAP_END static INPUT_PORTS_START( gts80 ) + PORT_START("DSW.0") + PORT_DIPNAME( 0x80, 0x00, "SW 1") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x80, DEF_STR(On)) + PORT_DIPNAME( 0x40, 0x00, "SW 2") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x40, DEF_STR(On)) + PORT_DIPNAME( 0x20, 0x00, "SW 3") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x20, DEF_STR(On)) + PORT_DIPNAME( 0x10, 0x00, "SW 4") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x10, DEF_STR(On)) + PORT_DIPNAME( 0x08, 0x00, "SW 5") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x08, DEF_STR(On)) + PORT_DIPNAME( 0x04, 0x00, "SW 6") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x04, DEF_STR(On)) + PORT_DIPNAME( 0x02, 0x00, "SW 7") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x02, DEF_STR(On)) + PORT_DIPNAME( 0x01, 0x00, "SW 8") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x01, DEF_STR(On)) + + PORT_START("DSW.1") + PORT_DIPNAME( 0x80, 0x00, "SW 9") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x80, DEF_STR(On)) + PORT_DIPNAME( 0x40, 0x00, "SW 10") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x40, DEF_STR(On)) + PORT_DIPNAME( 0x20, 0x00, "SW 11") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x20, DEF_STR(On)) + PORT_DIPNAME( 0x10, 0x00, "SW 12") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x10, DEF_STR(On)) + PORT_DIPNAME( 0x08, 0x00, "SW 13") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x08, DEF_STR(On)) + PORT_DIPNAME( 0x04, 0x00, "SW 14") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x04, DEF_STR(On)) + PORT_DIPNAME( 0x02, 0x02, "SW 15") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x02, DEF_STR(On)) + PORT_DIPNAME( 0x01, 0x00, "SW 16") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x01, DEF_STR(On)) + + PORT_START("DSW.2") + PORT_DIPNAME( 0x80, 0x80, "SW 17") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x80, DEF_STR(On)) + PORT_DIPNAME( 0x40, 0x40, "SW 18") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x40, DEF_STR(On)) + PORT_DIPNAME( 0x20, 0x00, "SW 19") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x20, DEF_STR(On)) + PORT_DIPNAME( 0x10, 0x00, "SW 20") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x10, DEF_STR(On)) + PORT_DIPNAME( 0x08, 0x00, "SW 21") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x08, DEF_STR(On)) + PORT_DIPNAME( 0x04, 0x00, "SW 22") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x04, DEF_STR(On)) + PORT_DIPNAME( 0x02, 0x02, "SW 23") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x02, DEF_STR(On)) + PORT_DIPNAME( 0x01, 0x01, "SW 24") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x01, DEF_STR(On)) + + PORT_START("DSW.3") + PORT_DIPNAME( 0x80, 0x80, "SW 25") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x80, DEF_STR(On)) + PORT_DIPNAME( 0x40, 0x40, "SW 26") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x40, DEF_STR(On)) + PORT_DIPNAME( 0x20, 0x20, "SW 27") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x20, DEF_STR(On)) + PORT_DIPNAME( 0x10, 0x10, "SW 28") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x10, DEF_STR(On)) + PORT_DIPNAME( 0x08, 0x08, "SW 29") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x08, DEF_STR(On)) + PORT_DIPNAME( 0x04, 0x04, "SW 30") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x04, DEF_STR(On)) + PORT_DIPNAME( 0x02, 0x00, "SW 31") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x02, DEF_STR(On)) + PORT_DIPNAME( 0x01, 0x00, "SW 32") + PORT_DIPSETTING( 0x00, DEF_STR(Off)) + PORT_DIPSETTING( 0x01, DEF_STR(On)) + + PORT_START("X0") + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) + + PORT_START("X1") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN3 ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 ) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) + + PORT_START("X2") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_F) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K) + + PORT_START("X4") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_M) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_COMMA) + + PORT_START("X8") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_STOP) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_SLASH) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_COLON) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_QUOTE) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_MINUS) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_EQUALS) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_BACKSPACE) + + PORT_START("X10") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_OPENBRACE) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_CLOSEBRACE) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_BACKSLASH) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_ENTER) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_LEFT) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_RIGHT) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_UP) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_DOWN) + + PORT_START("X20") +// PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) +// PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) +// PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) +// PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) +// PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) +// PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) +// PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) +// PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_O) + + PORT_START("X40") +// PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) +// PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) +// PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) +// PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) +// PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) +// PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) +// PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) +// PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_O) + + PORT_START("X80") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_O) INPUT_PORTS_END READ8_MEMBER( gts80_state::port1a_r ) { - return 0xff; + char kbdrow[8]; + if ((m_row < 4) && (m_segment==0x80)) + { + sprintf(kbdrow,"DSW.%d",m_row); + return ioport(kbdrow)->read(); + } + else + { + sprintf(kbdrow,"X%X",m_kbdrow); + return ioport(kbdrow)->read() ^ 0xff; // inverted through 7404 + } + + return 0; } READ8_MEMBER( gts80_state::port2a_r ) { - return 0xff; + return m_port2 | 0x80; // slam tilt off } WRITE8_MEMBER( gts80_state::port1b_w ) { + m_kbdrow = data & 15;//printf("%X ",data); } +// schematic and pinmame say '1' is indicated by m_segment !bits 4,5,6, but it is !bit 7 WRITE8_MEMBER( gts80_state::port2a_w ) { -//printf("A:%X ",data); + m_port2 = data; + static const UINT8 patterns[16] = { 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7c,0x07,0x7f,0x67,0x58,0x4c,0x62,0x69,0x78,0 }; // 7448 + UINT16 seg1 = (UINT16)patterns[m_segment & 15]; + UINT16 seg2 = BITSWAP16(seg1, 8, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 4, 3, 2, 1, 0); + switch (data & 0x70) + { + case 0x10: // player 1&2 + if (!BIT(m_segment, 7)) seg2 |= 0x300; // put '1' in the middle + output_set_digit_value(data & 15, seg2); + break; + case 0x20: // player 3&4 + if (!BIT(m_segment, 7)) seg2 |= 0x300; // put '1' in the middle + output_set_digit_value((data & 15)+20, seg2); + break; + case 0x40: // credits & balls + if (!BIT(m_segment, 7)) m_segment = 1; // turn '1' back to normal + output_set_digit_value((data & 15)+40, patterns[m_segment & 15]); + break; + } } +//d0-3 bcd data; d4-6 = centre segment; d7 = dipsw enable WRITE8_MEMBER( gts80_state::port2b_w ) { -//printf("B:%X ",data); + m_segment = data;//printf("%s:%X ",machine().describe_context(),data); } WRITE8_MEMBER( gts80_state::port3a_w ) @@ -83,6 +309,7 @@ WRITE8_MEMBER( gts80_state::port3a_w ) WRITE8_MEMBER( gts80_state::port3b_w ) { + m_row = data >> 4; } void gts80_state::machine_reset() @@ -96,14 +323,16 @@ DRIVER_INIT_MEMBER( gts80_state, gts80 ) /* with Sound Board */ static MACHINE_CONFIG_START( gts80_s, gts80_state ) /* basic machine hardware */ - MCFG_CPU_ADD("maincpu", M6502, 850000) // xtal frequency not shown + MCFG_CPU_ADD("maincpu", M6502, XTAL_3_579545MHz/4) MCFG_CPU_PROGRAM_MAP(gts80_map) + MCFG_NVRAM_ADD_1FILL("nvram") // must be 1 + /* Video */ MCFG_DEFAULT_LAYOUT(layout_gts80) /* Devices */ - MCFG_DEVICE_ADD("riot1", RIOT6532, 850000) + MCFG_DEVICE_ADD("riot1", RIOT6532, XTAL_3_579545MHz/4) MCFG_RIOT6532_IN_PA_CB(READ8(gts80_state, port1a_r)) // sw_r //MCFG_RIOT6532_OUT_PA_CB(WRITE8(gts80_state, port1a_w)) //MCFG_RIOT6532_IN_PB_CB(READ8(gts80_state, port1b_r)) diff --git a/src/mame/drivers/spectra.c b/src/mame/drivers/spectra.c index 8af68831612..d308e11c01e 100644 --- a/src/mame/drivers/spectra.c +++ b/src/mame/drivers/spectra.c @@ -248,10 +248,10 @@ static const sn76477_interface sn76477_intf = static MACHINE_CONFIG_START( spectra, spectra_state ) /* basic machine hardware */ - MCFG_CPU_ADD("maincpu", M6502, 3579545/4) // actually a M6503 + MCFG_CPU_ADD("maincpu", M6502, XTAL_3_579545MHz/4) // actually a M6503 MCFG_CPU_PROGRAM_MAP(spectra_map) - MCFG_DEVICE_ADD("riot", RIOT6532, 3579545/4) + MCFG_DEVICE_ADD("riot", RIOT6532, XTAL_3_579545MHz/4) MCFG_RIOT6532_IN_PA_CB(READ8(spectra_state, porta_r)) MCFG_RIOT6532_OUT_PA_CB(WRITE8(spectra_state, porta_w)) MCFG_RIOT6532_IN_PB_CB(READ8(spectra_state, portb_r)) diff --git a/src/mame/layout/gts80.lay b/src/mame/layout/gts80.lay index 129ca042d2c..aedbbe80ff7 100644 --- a/src/mame/layout/gts80.lay +++ b/src/mame/layout/gts80.lay @@ -9,6 +9,11 @@ + + + + + @@ -56,22 +61,22 @@ - + - + - + - + - + - + @@ -96,36 +101,36 @@ - + - + - + - + - + - + - + - + - + - + @@ -134,7 +139,5 @@ - -