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https://github.com/holub/mame
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tms32025.cpp: devcb instead of memory map for ports (nw)
This commit is contained in:
Ivan Vangelista
parent
597b2417b4
commit
47ac9a7bda
@ -131,8 +131,6 @@ Table 3-2. TMS32025/26 Memory Blocks
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#define P_IN(A) (m_io->read_word((A)<<1))
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#define P_OUT(A,V) (m_io->write_word(((A)<<1),(V)))
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#define S_IN(A) (m_io->read_word((A)<<1))
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#define S_OUT(A,V) (m_io->write_word(((A)<<1),(V)))
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#define M_RDOP(A) ((m_pgmmap[(A) >> 7]) ? (m_pgmmap[(A) >> 7][(A) & 0x7f]) : m_direct->read_word((A)<<1))
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#define M_RDOP_ARG(A) ((m_pgmmap[(A) >> 7]) ? (m_pgmmap[(A) >> 7][(A) & 0x7f]) : m_direct->read_word((A)<<1))
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@ -212,7 +210,13 @@ tms32025_device::tms32025_device(const machine_config &mconfig, const char *tag,
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: cpu_device(mconfig, TMS32025, "TMS32025", tag, owner, clock, "tms32025", __FILE__)
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, m_program_config("program", ENDIANNESS_BIG, 16, 16, -1)
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, m_data_config("data", ENDIANNESS_BIG, 16, 16, -1)
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, m_io_config("io", ENDIANNESS_BIG, 16, 16+1, -1)
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, m_io_config("io", ENDIANNESS_BIG, 16, 16, -1)
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, m_bio_in(*this)
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, m_hold_in(*this)
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, m_hold_ack_out(*this)
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, m_xf_out(*this)
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, m_dr_in(*this)
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, m_dx_out(*this)
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{
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}
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@ -221,7 +225,13 @@ tms32025_device::tms32025_device(const machine_config &mconfig, device_type type
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: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
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, m_program_config("program", ENDIANNESS_BIG, 16, 16, -1)
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, m_data_config("data", ENDIANNESS_BIG, 16, 16, -1)
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, m_io_config("io", ENDIANNESS_BIG, 16, 16+1, -1)
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, m_io_config("io", ENDIANNESS_BIG, 16, 16, -1)
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, m_bio_in(*this)
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, m_hold_in(*this)
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, m_hold_ack_out(*this)
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, m_xf_out(*this)
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, m_dr_in(*this)
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, m_dx_out(*this)
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{
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}
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@ -674,7 +684,7 @@ void tms32025_device::bgz()
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}
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void tms32025_device::bioz()
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{
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if (S_IN(TMS32025_BIO) != CLEAR_LINE) SET_PC(M_RDOP_ARG(m_PC));
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if (m_bio_in() != CLEAR_LINE) SET_PC(M_RDOP_ARG(m_PC));
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else m_PC++ ;
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MODIFY_AR_ARP();
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}
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@ -1276,7 +1286,7 @@ void tms32025_device::rtxm() /** Serial port stuff */
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void tms32025_device::rxf()
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{
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CLR1(XF_FLAG);
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S_OUT(TMS32025_XF,CLEAR_LINE);
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m_xf_out(CLEAR_LINE);
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}
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void tms32025_device::sach()
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{
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@ -1485,7 +1495,7 @@ void tms32025_device::subt()
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void tms32025_device::sxf()
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{
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SET1(XF_FLAG);
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S_OUT(TMS32025_XF,ASSERT_LINE);
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m_xf_out(ASSERT_LINE);
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}
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void tms32025_device::tblr()
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{
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@ -1639,6 +1649,13 @@ void tms32025_device::device_start()
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m_data = &space(AS_DATA);
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m_io = &space(AS_IO);
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m_bio_in.resolve_safe(0xffff);
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m_hold_in.resolve_safe(0xffff);
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m_hold_ack_out.resolve_safe();
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m_xf_out.resolve_safe();
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m_dr_in.resolve_safe(0xffff);
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m_dx_out.resolve_safe();
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m_PREVPC = 0;
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m_PFC = 0;
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m_STR0 = 0;
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@ -1846,7 +1863,7 @@ void tms32025_device::device_reset()
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m_RPTC = 0; /* Reset repeat counter to 0 */
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m_IFR = 0; /* IRQ pending flags */
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S_OUT(TMS32025_XF,ASSERT_LINE); /* XF flag is high. Must set the pin */
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m_xf_out(ASSERT_LINE); /* XF flag is high. Must set the pin */
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/* Set the internal memory mapped registers */
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GREG = 0;
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@ -1941,7 +1958,7 @@ int tms32025_device::process_IRQs()
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}
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if ((m_IFR & 0x10) && (IMR & 0x10)) { /* Serial port receive IRQ (internal) */
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// logerror("TMS32025: Active RINT (Serial receive)\n");
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DRR = S_IN(TMS32025_DR);
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DRR = m_dr_in();
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SET_PC(0x001A);
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m_idle = 0;
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m_IFR &= (~0x10);
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@ -1950,7 +1967,7 @@ int tms32025_device::process_IRQs()
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}
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if ((m_IFR & 0x20) && (IMR & 0x20)) { /* Serial port transmit IRQ (internal) */
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// logerror("TMS32025: Active XINT (Serial transmit)\n");
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S_OUT(TMS32025_DX,DXR);
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m_dx_out(DXR);
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SET_PC(0x001C);
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m_idle = 0;
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m_IFR &= (~0x20);
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@ -2005,9 +2022,9 @@ again:
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void tms32025_device::execute_run()
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{
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/**** Respond to external hold signal */
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if (S_IN(TMS32025_HOLD) == ASSERT_LINE) {
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if (m_hold_in() == ASSERT_LINE) {
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if (m_hold == 0) {
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S_OUT(TMS32025_HOLDA,ASSERT_LINE); /* Hold-Ack (active low) */
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m_hold_ack_out(ASSERT_LINE); /* Hold-Ack (active low) */
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}
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m_hold = 1;
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if (HM) {
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@ -2021,7 +2038,7 @@ void tms32025_device::execute_run()
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}
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else {
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if (m_hold == 1) {
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S_OUT(TMS32025_HOLDA,CLEAR_LINE); /* Hold-Ack (active low) */
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m_hold_ack_out(CLEAR_LINE); /* Hold-Ack (active low) */
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process_timer(3);
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}
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m_hold = 0;
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@ -23,17 +23,25 @@
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#define __TMS32025_H__
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#define MCFG_TMS32025_BIO_IN_CB(_devcb) \
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devcb = &tms32025_device::set_bio_in_cb(*device, DEVCB_##_devcb); /* BIO input */
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#define MCFG_TMS32025_HOLD_IN_CB(_devcb) \
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devcb = &tms32025_device::set_hold_in_cb(*device, DEVCB_##_devcb); /* HOLD input */
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#define TMS32025_BIO 0x10000 /* BIO input */
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#define TMS32025_HOLD 0x10001 /* HOLD input */
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#define TMS32025_HOLDA 0x10001 /* HOLD Acknowledge output */
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#define TMS32025_XF 0x10002 /* XF output */
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#define TMS32025_DR 0x10003 /* Serial Data Receive input */
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#define TMS32025_DX 0x10003 /* Serial Data Transmit output */
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#define MCFG_TMS32025_HOLD_ACK_OUT_CB(_devcb) \
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devcb = &tms32025_device::set_hold_ack_out_cb(*device, DEVCB_##_devcb); /* HOLD Acknowledge output */
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#define MCFG_TMS32025_XF_OUT_CB(_devcb) \
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devcb = &tms32025_device::set_xf_out_cb(*device, DEVCB_##_devcb); /* XF output */
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#define MCFG_TMS32025_DR_IN_CB(_devcb) \
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devcb = &tms32025_device::set_dr_in_cb(*device, DEVCB_##_devcb); /* Serial Data Receive input */
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#define MCFG_TMS32025_DX_OUT_CB(_devcb) \
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devcb = &tms32025_device::set_dx_out_cb(*device, DEVCB_##_devcb); /* Serial Data Transmit output */
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/****************************************************************************
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* Interrupt constants
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*/
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@ -75,6 +83,14 @@ public:
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// construction/destruction
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tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
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// static configuration helpers
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template<class _Object> static devcb_base & set_bio_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_bio_in.set_callback(object); }
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template<class _Object> static devcb_base & set_hold_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_hold_in.set_callback(object); }
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template<class _Object> static devcb_base & set_hold_ack_out_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_hold_ack_out.set_callback(object); }
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template<class _Object> static devcb_base & set_xf_out_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_xf_out.set_callback(object); }
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template<class _Object> static devcb_base & set_dr_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_dr_in.set_callback(object); }
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template<class _Object> static devcb_base & set_dx_out_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_dx_out.set_callback(object); }
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protected:
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// device-level overrides
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@ -119,6 +135,13 @@ private:
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static const tms32025_opcode s_opcode_CE_subset[256];
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static const tms32025_opcode s_opcode_Dx_subset[8];
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devcb_read16 m_bio_in;
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devcb_read16 m_hold_in;
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devcb_write16 m_hold_ack_out;
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devcb_write16 m_xf_out;
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devcb_read16 m_dr_in;
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devcb_write16 m_dx_out;
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/******************** CPU Internal Registers *******************/
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UINT16 m_PREVPC; /* previous program counter */
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@ -681,9 +681,6 @@ static ADDRESS_MAP_START( coolpool_dsp_io_map, AS_IO, 16, coolpool_state )
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AM_RANGE(0x04, 0x04) AM_READ(dsp_rom_r)
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AM_RANGE(0x05, 0x05) AM_READ_PORT("IN0")
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AM_RANGE(0x07, 0x07) AM_READ_PORT("IN1")
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AM_RANGE(TMS32025_BIO, TMS32025_BIO) AM_READ(dsp_bio_line_r)
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AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_hold_line_r)
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// AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE(dsp_HOLDA_signal_w)
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ADDRESS_MAP_END
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@ -837,6 +834,9 @@ static MACHINE_CONFIG_START( coolpool, coolpool_state )
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MCFG_CPU_ADD("dsp", TMS32026,XTAL_40MHz)
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MCFG_CPU_PROGRAM_MAP(coolpool_dsp_pgm_map)
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MCFG_CPU_IO_MAP(coolpool_dsp_io_map)
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MCFG_TMS32025_BIO_IN_CB(READ16(coolpool_state, dsp_bio_line_r))
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MCFG_TMS32025_HOLD_IN_CB(READ16(coolpool_state, dsp_hold_line_r))
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// MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(coolpool_state, dsp_HOLDA_signal_w))
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MCFG_MACHINE_RESET_OVERRIDE(coolpool_state,coolpool)
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MCFG_NVRAM_ADD_0FILL("nvram")
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@ -780,13 +780,6 @@ static ADDRESS_MAP_START( dsp_map_data, AS_DATA, 16, mlanding_state )
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AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("dot_ram")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( dsp_map_io, AS_IO, 16, mlanding_state )
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AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_hold_signal_r)
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AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITENOP
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ADDRESS_MAP_END
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/*************************************
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*
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* Audio CPU memory handlers
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@ -945,7 +938,8 @@ static MACHINE_CONFIG_START( mlanding, mlanding_state )
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MCFG_CPU_ADD("dsp", TMS32025, 32000000) // ?
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MCFG_CPU_PROGRAM_MAP(dsp_map_prog)
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MCFG_CPU_DATA_MAP(dsp_map_data)
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MCFG_CPU_IO_MAP(dsp_map_io)
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MCFG_TMS32025_HOLD_IN_CB(READ16(mlanding_state, dsp_hold_signal_r))
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MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP)
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MCFG_DEVICE_ADD("ctc", Z80CTC, 4000000)
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MCFG_Z80CTC_ZC0_CB(WRITELINE(mlanding_state, z80ctc_to0))
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@ -993,9 +993,6 @@ static ADDRESS_MAP_START( master_dsp_io, AS_IO, 16, namcos21_state )
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AM_RANGE(0x0b,0x0b) AM_READWRITE(dsp_portb_r,dsp_portb_w)
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AM_RANGE(0x0c,0x0c) AM_WRITE(dsp_portc_w)
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AM_RANGE(0x0f,0x0f) AM_READ(dsp_portf_r)
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AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READNOP
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AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITENOP
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AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITE(dsp_xf_w )
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ADDRESS_MAP_END
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/************************************************************************************/
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@ -1111,9 +1108,6 @@ static ADDRESS_MAP_START( slave_dsp_io, AS_IO, 16, namcos21_state )
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AM_RANGE(0x02,0x02) AM_READ(slave_port2_r)
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AM_RANGE(0x03,0x03) AM_READWRITE(slave_port3_r,slave_port3_w)
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AM_RANGE(0x0f,0x0f) AM_READ(slave_portf_r)
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AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READNOP
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AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITENOP
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AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITE(slave_XF_output_w)
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ADDRESS_MAP_END
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/************************************************************************************/
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@ -1424,21 +1418,8 @@ static ADDRESS_MAP_START( winrun_dsp_io, AS_IO, 16, namcos21_state )
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AM_RANGE(0x0a,0x0a) AM_WRITE(winrun_dsp_render_w)
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AM_RANGE(0x0b,0x0b) AM_WRITENOP
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AM_RANGE(0x0c,0x0c) AM_WRITE(winrun_dsp_complete_w)
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AM_RANGE(TMS32025_BIO, TMS32025_BIO) AM_READ(winrun_poly_reset_r )
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AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READNOP
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AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITENOP
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AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITENOP
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ADDRESS_MAP_END
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READ16_MEMBER(namcos21_state::winrun_gpucomram_r)
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{
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return m_winrun_gpucomram[offset];
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}
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WRITE16_MEMBER(namcos21_state::winrun_gpucomram_w)
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{
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COMBINE_DATA( &m_winrun_gpucomram[offset] );
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}
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WRITE16_MEMBER(namcos21_state::winrun_dspbios_w)
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{
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COMBINE_DATA( &m_winrun_dspbios[offset] );
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@ -1491,7 +1472,7 @@ static ADDRESS_MAP_START( am_master_winrun, AS_PROGRAM, 16, namcos21_state )
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AM_RANGE(0x3c0000, 0x3c1fff) AM_READWRITE(winrun_68k_dspcomram_r,winrun_68k_dspcomram_w)
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AM_RANGE(0x400000, 0x400001) AM_WRITE(pointram_control_w)
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AM_RANGE(0x440000, 0x440001) AM_READWRITE(pointram_data_r,pointram_data_w)
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AM_RANGE(0x600000, 0x60ffff) AM_READWRITE(winrun_gpucomram_r,winrun_gpucomram_w)
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AM_RANGE(0x600000, 0x60ffff) AM_RAM AM_SHARE("gpu_comram")
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AM_RANGE(0x800000, 0x87ffff) AM_ROM AM_REGION("data", 0)
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AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("sharedram")
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AM_RANGE(0xa00000, 0xa00fff) AM_READWRITE(namcos2_68k_dualportram_word_r,namcos2_68k_dualportram_word_w)
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@ -1503,7 +1484,7 @@ static ADDRESS_MAP_START( am_slave_winrun, AS_PROGRAM, 16, namcos21_state )
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AM_RANGE(0x000000, 0x03ffff) AM_ROM
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AM_RANGE(0x100000, 0x13ffff) AM_RAM
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AM_RANGE(0x1c0000, 0x1fffff) AM_READWRITE(namcos2_68k_slave_C148_r,namcos2_68k_slave_C148_w)
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AM_RANGE(0x600000, 0x60ffff) AM_READWRITE(winrun_gpucomram_r,winrun_gpucomram_w)
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AM_RANGE(0x600000, 0x60ffff) AM_RAM AM_SHARE("gpu_comram")
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AM_RANGE(0x800000, 0x87ffff) AM_ROM AM_REGION("data", 0)
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AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("sharedram")
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AM_RANGE(0xa00000, 0xa00fff) AM_READWRITE(namcos2_68k_dualportram_word_r,namcos2_68k_dualportram_word_w)
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@ -1516,7 +1497,7 @@ static ADDRESS_MAP_START( am_gpu_winrun, AS_PROGRAM, 16, namcos21_state )
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AM_RANGE(0x100000, 0x100001) AM_READWRITE(winrun_gpu_color_r,winrun_gpu_color_w) /* ? */
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AM_RANGE(0x180000, 0x19ffff) AM_RAM /* work RAM */
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AM_RANGE(0x1c0000, 0x1fffff) AM_READWRITE(namcos21_68k_gpu_C148_r,namcos21_68k_gpu_C148_w)
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AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_SHARE("winrun_comram")
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AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_SHARE("gpu_comram")
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AM_RANGE(0x400000, 0x40ffff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
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AM_RANGE(0x410000, 0x41ffff) AM_RAM_DEVWRITE("palette", palette_device, write_ext) AM_SHARE("palette_ext")
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AM_RANGE(0x600000, 0x6fffff) AM_ROM AM_REGION("gdata", 0)
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@ -1667,11 +1648,17 @@ static MACHINE_CONFIG_START( namcos21, namcos21_state )
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MCFG_CPU_PROGRAM_MAP(master_dsp_program)
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MCFG_CPU_DATA_MAP(master_dsp_data)
|
||||
MCFG_CPU_IO_MAP(master_dsp_io)
|
||||
MCFG_TMS32025_HOLD_IN_CB(NOOP)
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP)
|
||||
MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos21_state, dsp_xf_w))
|
||||
|
||||
MCFG_CPU_ADD("dspslave", TMS32025,24000000*4) /* 24 MHz?; overclocked */
|
||||
MCFG_CPU_PROGRAM_MAP(slave_dsp_program)
|
||||
MCFG_CPU_DATA_MAP(slave_dsp_data)
|
||||
MCFG_CPU_IO_MAP(slave_dsp_io)
|
||||
MCFG_TMS32025_HOLD_IN_CB(NOOP)
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP)
|
||||
MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos21_state, slave_XF_output_w))
|
||||
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(12000))
|
||||
|
||||
@ -1729,6 +1716,10 @@ static MACHINE_CONFIG_START( driveyes, namcos21_state )
|
||||
MCFG_CPU_PROGRAM_MAP(winrun_dsp_program)
|
||||
MCFG_CPU_DATA_MAP(winrun_dsp_data)
|
||||
MCFG_CPU_IO_MAP(winrun_dsp_io)
|
||||
MCFG_TMS32025_BIO_IN_CB(READ16(namcos21_state, winrun_poly_reset_r))
|
||||
MCFG_TMS32025_HOLD_IN_CB(NOOP)
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP)
|
||||
MCFG_TMS32025_XF_OUT_CB(NOOP)
|
||||
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(6000)) /* 100 CPU slices per frame */
|
||||
|
||||
@ -1786,6 +1777,10 @@ static MACHINE_CONFIG_START( winrun, namcos21_state )
|
||||
MCFG_CPU_PROGRAM_MAP(winrun_dsp_program)
|
||||
MCFG_CPU_DATA_MAP(winrun_dsp_data)
|
||||
MCFG_CPU_IO_MAP(winrun_dsp_io)
|
||||
MCFG_TMS32025_BIO_IN_CB(READ16(namcos21_state, winrun_poly_reset_r))
|
||||
MCFG_TMS32025_HOLD_IN_CB(NOOP)
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP)
|
||||
MCFG_TMS32025_XF_OUT_CB(NOOP)
|
||||
|
||||
MCFG_CPU_ADD("gpu", M68000,12288000) /* graphics coprocessor */
|
||||
MCFG_CPU_PROGRAM_MAP(am_gpu_winrun)
|
||||
|
||||
@ -162,7 +162,7 @@
|
||||
*the video board as these are known to run hot and commonly fail, especially now the system is many years old.
|
||||
*
|
||||
*CPU PCB - There are four known revisions of this PCB. Three of them have an extra connector for an
|
||||
* auxillary PCB. One of the others doesn't have that connector but is are otherwise identical.
|
||||
* auxiliary PCB. One of the others doesn't have that connector but is are otherwise identical.
|
||||
* All PCBs can be swapped to any game and it will work. However, ALL required IC's must be swapped.
|
||||
* This includes Program ROM PCB, socketed Keycus IC, socketed DATA ROM and socketed WAVE ROM(s).
|
||||
* On most games the EEPROM will re-init itself on bootup. On the others, the EEPROM can re-init itself
|
||||
@ -242,7 +242,7 @@
|
||||
*Notes:
|
||||
* J6 : Custom Namco connector for plug-in program ROM PCB
|
||||
* J11 : Custom Namco connector for optional plug-in WAVE ROM PCB (holds some SOP44 MASKROMs)
|
||||
* JC410 : Custom Namco connector for Optional plug-in Auxillary PCB (e.g. Gun Control PCB used in Time Crisis
|
||||
* JC410 : Custom Namco connector for Optional plug-in Auxiliary PCB (e.g. Gun Control PCB used in Time Crisis
|
||||
* etc)
|
||||
* The connector is populated only on the 2nd revision CPU (B) PCB 8646962600 (8646972600)
|
||||
* and 3rd Revision CPU (B) PCB 8646962600 (8646972601)
|
||||
@ -963,7 +963,7 @@
|
||||
* C407 : Namco custom C407 (QFP64) NOTE! On Revision A & B, this position is populated by an
|
||||
* Altera EPM7064 PLCC84 FPGA labelled 'SS22V1B'
|
||||
* The Altera chip runs very hot and fails quite often.
|
||||
* Even if a heaksink is added to the chip it still fails.
|
||||
* Even if a heatsink is added to the chip it still fails.
|
||||
* The failure of this chip is the primary cause of
|
||||
* video faults on Namco Super System 22 PCBs.
|
||||
* (Second reason for video faults is generally attributed
|
||||
@ -2562,11 +2562,6 @@ static ADDRESS_MAP_START( master_dsp_io, AS_IO, 16, namcos22_state )
|
||||
AM_RANGE(0xd, 0xd) AM_WRITE(namcos22_dspram16_bank_w)
|
||||
AM_RANGE(0xe, 0xe) AM_WRITE(dsp_led_w)
|
||||
AM_RANGE(0xf, 0xf) AM_READ(dsp_upload_status_r) AM_WRITENOP
|
||||
AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_hold_signal_r)
|
||||
AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE(dsp_hold_ack_w)
|
||||
AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITE(dsp_xf_output_w)
|
||||
AM_RANGE(TMS32025_BIO, TMS32025_BIO) AM_READ(pdp_status_r)
|
||||
AM_RANGE(TMS32025_DR, TMS32025_DR) AM_READ(master_serial_io_r)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
@ -2651,12 +2646,6 @@ static ADDRESS_MAP_START( slave_dsp_io, AS_IO, 16, namcos22_state )
|
||||
AM_RANGE(0xb, 0xb) AM_READWRITE(dsp_slave_portb_r, dsp_slave_portb_w)
|
||||
|
||||
AM_RANGE(0xc, 0xc) AM_WRITE(dsp_slave_portc_w)
|
||||
|
||||
AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_hold_signal_r)
|
||||
AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE(dsp_hold_ack_w)
|
||||
AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITE(dsp_xf_output_w)
|
||||
AM_RANGE(TMS32025_BIO, TMS32025_BIO) AM_READ(dsp_bioz_r)
|
||||
AM_RANGE(TMS32025_DX, TMS32025_DX) AM_WRITE(slave_serial_io_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
@ -3751,12 +3740,22 @@ static MACHINE_CONFIG_START( namcos22, namcos22_state )
|
||||
MCFG_CPU_PROGRAM_MAP(master_dsp_program)
|
||||
MCFG_CPU_DATA_MAP(master_dsp_data)
|
||||
MCFG_CPU_IO_MAP(master_dsp_io)
|
||||
MCFG_TMS32025_BIO_IN_CB(READ16(namcos22_state, pdp_status_r))
|
||||
MCFG_TMS32025_HOLD_IN_CB(READ16(namcos22_state, dsp_hold_signal_r))
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(namcos22_state, dsp_hold_ack_w))
|
||||
MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos22_state, dsp_xf_output_w))
|
||||
MCFG_TMS32025_DR_IN_CB(READ16(namcos22_state, master_serial_io_r))
|
||||
MCFG_TIMER_DRIVER_ADD_SCANLINE("master_st", namcos22_state, dsp_master_serial_irq, "screen", 0, 1)
|
||||
|
||||
MCFG_CPU_ADD("slave", TMS32025,SS22_MASTER_CLOCK) /* ? */
|
||||
MCFG_CPU_PROGRAM_MAP(slave_dsp_program)
|
||||
MCFG_CPU_DATA_MAP(slave_dsp_data)
|
||||
MCFG_CPU_IO_MAP(slave_dsp_io)
|
||||
MCFG_TMS32025_BIO_IN_CB(READ16(namcos22_state, dsp_bioz_r))
|
||||
MCFG_TMS32025_HOLD_IN_CB(READ16(namcos22_state, dsp_hold_signal_r))
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(namcos22_state, dsp_hold_ack_w))
|
||||
MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos22_state, dsp_xf_output_w))
|
||||
MCFG_TMS32025_DX_OUT_CB(WRITE16(namcos22_state, slave_serial_io_w))
|
||||
MCFG_TIMER_DRIVER_ADD_SCANLINE("slave_st", namcos22_state, dsp_slave_serial_irq, "screen", 0, 1)
|
||||
|
||||
MCFG_CPU_ADD("mcu", NAMCO_C74, SS22_MASTER_CLOCK/3) // C74 on the CPU board has no periodic interrupts, it runs entirely off Timer A0
|
||||
@ -3801,12 +3800,22 @@ static MACHINE_CONFIG_START( namcos22s, namcos22_state )
|
||||
MCFG_CPU_PROGRAM_MAP(master_dsp_program)
|
||||
MCFG_CPU_DATA_MAP(master_dsp_data)
|
||||
MCFG_CPU_IO_MAP(master_dsp_io)
|
||||
MCFG_TMS32025_BIO_IN_CB(READ16(namcos22_state, pdp_status_r))
|
||||
MCFG_TMS32025_HOLD_IN_CB(READ16(namcos22_state, dsp_hold_signal_r))
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(namcos22_state, dsp_hold_ack_w))
|
||||
MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos22_state, dsp_xf_output_w))
|
||||
MCFG_TMS32025_DR_IN_CB(READ16(namcos22_state, master_serial_io_r))
|
||||
MCFG_TIMER_DRIVER_ADD_SCANLINE("master_st", namcos22_state, dsp_master_serial_irq, "screen", 0, 1)
|
||||
|
||||
MCFG_CPU_ADD("slave", TMS32025,SS22_MASTER_CLOCK)
|
||||
MCFG_CPU_PROGRAM_MAP(slave_dsp_program)
|
||||
MCFG_CPU_DATA_MAP(slave_dsp_data)
|
||||
MCFG_CPU_IO_MAP(slave_dsp_io)
|
||||
MCFG_TMS32025_BIO_IN_CB(READ16(namcos22_state, dsp_bioz_r))
|
||||
MCFG_TMS32025_HOLD_IN_CB(READ16(namcos22_state, dsp_hold_signal_r))
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(namcos22_state, dsp_hold_ack_w))
|
||||
MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos22_state, dsp_xf_output_w))
|
||||
MCFG_TMS32025_DX_OUT_CB(WRITE16(namcos22_state, slave_serial_io_w))
|
||||
MCFG_TIMER_DRIVER_ADD_SCANLINE("slave_st", namcos22_state, dsp_slave_serial_irq, "screen", 0, 1)
|
||||
|
||||
MCFG_CPU_ADD("mcu", M37710S4, SS22_MASTER_CLOCK/3)
|
||||
|
||||
@ -153,7 +153,7 @@ DIPs
|
||||
----
|
||||
|
||||
They're now correct (including locations) according to the
|
||||
manuals. Nevertherless, ainferno manual states that the coinage
|
||||
manuals. Nevertheless, ainferno manual states that the coinage
|
||||
DIPs are the same as topland, which is clearly wrong if you try
|
||||
them ("SWB:7,8" do not set Coin B to multiple credits for each
|
||||
coin!)
|
||||
@ -536,11 +536,6 @@ static ADDRESS_MAP_START( DSP_map_data, AS_DATA, 16, taitoair_state )
|
||||
AM_RANGE(0x8000, 0xffff) AM_READWRITE(dspram_r, dspram_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( DSP_map_io, AS_IO, 16, taitoair_state )
|
||||
AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_HOLD_signal_r)
|
||||
AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE(dsp_HOLDA_signal_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
/************************************************************
|
||||
INPUT PORTS & DIPS
|
||||
@ -726,7 +721,8 @@ static MACHINE_CONFIG_START( airsys, taitoair_state )
|
||||
MCFG_CPU_ADD("dsp", TMS32025, XTAL_36MHz) // Unverified
|
||||
MCFG_CPU_PROGRAM_MAP(DSP_map_program)
|
||||
MCFG_CPU_DATA_MAP(DSP_map_data)
|
||||
MCFG_CPU_IO_MAP(DSP_map_io)
|
||||
MCFG_TMS32025_HOLD_IN_CB(READ16(taitoair_state, dsp_HOLD_signal_r))
|
||||
MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(taitoair_state, dsp_HOLDA_signal_w))
|
||||
|
||||
MCFG_QUANTUM_PERFECT_CPU("maincpu")
|
||||
|
||||
|
||||
@ -47,7 +47,6 @@ public:
|
||||
: namcos2_shared_state(mconfig, type, tag),
|
||||
m_winrun_dspbios(*this,"winrun_dspbios"),
|
||||
m_winrun_polydata(*this,"winrun_polydata"),
|
||||
m_winrun_gpucomram(*this,"winrun_comram"),
|
||||
m_dspram16(*this,"dspram16"),
|
||||
m_mpDualPortRAM(*this,"mpdualportram"),
|
||||
m_master_dsp_code(*this,"master_dsp_code"),
|
||||
@ -57,7 +56,6 @@ public:
|
||||
|
||||
optional_shared_ptr<UINT16> m_winrun_dspbios;
|
||||
optional_shared_ptr<UINT16> m_winrun_polydata;
|
||||
optional_shared_ptr<UINT16> m_winrun_gpucomram;
|
||||
optional_shared_ptr<UINT16> m_dspram16;
|
||||
required_shared_ptr<UINT8> m_mpDualPortRAM;
|
||||
optional_shared_ptr<UINT16> m_master_dsp_code;
|
||||
@ -146,8 +144,6 @@ public:
|
||||
DECLARE_READ16_MEMBER(winrun_dsp_pointrom_data_r);
|
||||
DECLARE_WRITE16_MEMBER(winrun_dsp_complete_w);
|
||||
DECLARE_READ16_MEMBER(winrun_table_r);
|
||||
DECLARE_READ16_MEMBER(winrun_gpucomram_r);
|
||||
DECLARE_WRITE16_MEMBER(winrun_gpucomram_w);
|
||||
DECLARE_WRITE16_MEMBER(winrun_dspbios_w);
|
||||
DECLARE_READ16_MEMBER(winrun_68k_dspcomram_r);
|
||||
DECLARE_WRITE16_MEMBER(winrun_68k_dspcomram_w);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user