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z80scc: reassert interrupt if conditions persist (fixes MT#9141)

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This commit is contained in:
Patrick Mackinlay 2025-03-14 16:13:51 +07:00
parent dfcb1350c4
commit 47e9f4eee2
2 changed files with 25 additions and 16 deletions
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40
src/devices/machine/z80scc.cpp
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@ -1796,6 +1796,8 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
break;
}
}
// re-assert interrupt if conditions are still present
check_receive_interrupt();
break;
case WR0_ERROR_RESET:
/*Error Reset Command (110). This command resets the error bits in RR1. If interrupt on first Rx
@ -2584,22 +2586,7 @@ void z80scc_channel::receive_data(uint8_t data)
m_rr0 |= RR0_RX_CHAR_AVAILABLE;
check_dma_request();
// receive interrupt on FIRST and ALL character
switch (m_wr1 & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_FIRST:
if (m_rx_first)
{
m_uart->trigger_interrupt(m_index, INT_RECEIVE);
m_rx_first = 0;
}
break;
case WR1_RX_INT_ALL:
m_uart->trigger_interrupt(m_index, INT_RECEIVE);
break;
}
check_receive_interrupt();
}
@ -3005,3 +2992,24 @@ void z80scc_channel::check_dma_request()
}
}
}
void z80scc_channel::check_receive_interrupt()
{
if (m_rr0 & RR0_RX_CHAR_AVAILABLE)
{
switch (m_wr1 & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_FIRST:
if (m_rx_first)
{
m_uart->trigger_interrupt(m_index, INT_RECEIVE);
m_rx_first = 0;
}
break;
case WR1_RX_INT_ALL:
m_uart->trigger_interrupt(m_index, INT_RECEIVE);
break;
}
}
}

1
src/devices/machine/z80scc.h
View File

@ -249,6 +249,7 @@ protected:
int get_tx_word_length();
void safe_transmit_register_reset();
void check_dma_request();
void check_receive_interrupt();
emu_timer *m_baudtimer;
uint16_t m_brg_counter;