From 47eaa73ad6ce7e13fc351b250e52f459ddde0670 Mon Sep 17 00:00:00 2001 From: Quench0 Date: Thu, 2 Jun 2016 01:55:33 +1000 Subject: [PATCH] CPU M6800: CPX (compare X) instruction, fix behaviour of N and V flags. These two flags are only affected by the data comparison of the upper 8 bits, and not the whole 16 bits. --- src/devices/cpu/m6800/6800ops.hxx | 47 ++++++++++++++++--------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/src/devices/cpu/m6800/6800ops.hxx b/src/devices/cpu/m6800/6800ops.hxx index 45a78d1d71f..2138103bd41 100644 --- a/src/devices/cpu/m6800/6800ops.hxx +++ b/src/devices/cpu/m6800/6800ops.hxx @@ -1054,13 +1054,14 @@ OP_HANDLER( adda_im ) /* $8c CMPX immediate -***- */ OP_HANDLER( cmpx_im ) { - UINT32 r,d; - PAIR b; + PAIR r,d,b; IMMWORD(b); - d = X; - r = d - b.d; + d.d = X; + r.d = d.d - b.d; CLR_NZV; - SET_NZ16(r); SET_V16(d,b.d,r); + SET_Z16(r.d); + SET_N8(r.b.h); + SET_V8(d.b.h, b.b.h, r.b.h); } /* $8c CPX immediate -**** (6803) */ @@ -1220,14 +1221,14 @@ OP_HANDLER( adda_di ) /* $9c CMPX direct -***- */ OP_HANDLER( cmpx_di ) { - UINT32 r,d; - PAIR b; + PAIR r,d,b; DIRWORD(b); - d = X; - r = d - b.d; + d.d = X; + r.d = d.d - b.d; CLR_NZV; - SET_NZ16(r); - SET_V16(d,b.d,r); + SET_Z16(r.d); + SET_N8(r.b.h); + SET_V8(d.b.h, b.b.h, r.b.h); } /* $9c CPX direct -**** (6803) */ @@ -1394,14 +1395,14 @@ OP_HANDLER( adda_ix ) /* $ac CMPX indexed -***- */ OP_HANDLER( cmpx_ix ) { - UINT32 r,d; - PAIR b; + PAIR r,d,b; IDXWORD(b); - d = X; - r = d - b.d; + d.d = X; + r.d = d.d - b.d; CLR_NZV; - SET_NZ16(r); - SET_V16(d,b.d,r); + SET_Z16(r.d); + SET_N8(r.b.h); + SET_V8(d.b.h, b.b.h, r.b.h); } /* $ac CPX indexed -**** (6803)*/ @@ -1570,14 +1571,14 @@ OP_HANDLER( adda_ex ) /* $bc CMPX extended -***- */ OP_HANDLER( cmpx_ex ) { - UINT32 r,d; - PAIR b; + PAIR r,d,b; EXTWORD(b); - d = X; - r = d - b.d; + d.d = X; + r.d = d.d - b.d; CLR_NZV; - SET_NZ16(r); - SET_V16(d,b.d,r); + SET_Z16(r.d); + SET_N8(r.b.h); + SET_V8(d.b.h, b.b.h, r.b.h); } /* $bc CPX extended -**** (6803) */