mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
completely eliminate the concrete 68705-without-peripherals class
m6805evs: add proper memory map in comment and note that it needs CPU core support for the 68HC705 family
This commit is contained in:
Vas Crabb
parent
a6afc556b4
commit
48073dbf03
@ -52,7 +52,6 @@ ROM_END
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} // anonymous namespace
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device_type const M68705 = &device_creator<m68705_device>;
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device_type const M68705P3 = &device_creator<m68705p3_device>;
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device_type const M68705P5 = &device_creator<m68705p5_device>;
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device_type const M68705R3 = &device_creator<m68705r3_device>;
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@ -60,79 +59,7 @@ device_type const M68705U3 = &device_creator<m68705u3_device>;
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/****************************************************************************
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* M68705 device (no peripherals)
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****************************************************************************/
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m68705_device::m68705_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
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: m6805_base_device(mconfig, tag, owner, clock, M68705, "M68705", 12, "m68705", __FILE__)
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{
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}
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m68705_device::m68705_device(
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machine_config const &mconfig,
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char const *tag,
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device_t *owner,
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u32 clock,
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device_type type,
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char const *name,
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u32 addr_width,
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address_map_delegate internal_map,
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char const *shortname,
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char const *source)
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: m6805_base_device(mconfig, tag, owner, clock, type, name, addr_width, internal_map, shortname, source)
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{
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}
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/* Generate interrupt - m68705 version */
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void m68705_device::interrupt()
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{
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if ((m_pending_interrupts & ((1 << M6805_IRQ_LINE) | M68705_INT_MASK)) != 0 )
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{
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if ((CC & IFLAG) == 0)
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{
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PUSHWORD(m_pc);
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PUSHBYTE(m_x);
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PUSHBYTE(m_a);
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PUSHBYTE(m_cc);
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SEI;
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standard_irq_callback(0);
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if ((m_pending_interrupts & (1 << M68705_IRQ_LINE)) != 0 )
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{
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m_pending_interrupts &= ~(1 << M68705_IRQ_LINE);
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RM16(0xfffa, &m_pc);
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}
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else if ((m_pending_interrupts & (1 << M68705_INT_TIMER)) != 0)
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{
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m_pending_interrupts &= ~(1 << M68705_INT_TIMER);
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RM16(0xfff8, &m_pc);
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}
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}
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m_icount -= 11;
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}
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}
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void m68705_device::device_reset()
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{
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m6805_base_device::device_reset();
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RM16(0xfffe, &m_pc);
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}
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void m68705_device::execute_set_input(int inputnum, int state)
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{
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if (m_irq_state[inputnum] != state)
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{
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m_irq_state[inputnum] = (state == ASSERT_LINE) ? ASSERT_LINE : CLEAR_LINE;
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if (state != CLEAR_LINE)
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m_pending_interrupts |= 1 << inputnum;
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}
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}
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/****************************************************************************
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* M68705 "new" device
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* MC68705 base device
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****************************************************************************/
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/*
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@ -223,7 +150,7 @@ Ux Parts:
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*/
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m68705_new_device::m68705_new_device(
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m68705_device::m68705_device(
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machine_config const &mconfig,
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char const *tag,
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device_t *owner,
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@ -234,7 +161,7 @@ m68705_new_device::m68705_new_device(
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address_map_delegate internal_map,
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char const *shortname,
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char const *source)
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: m68705_device(mconfig, tag, owner, clock, type, name, addr_width, internal_map, shortname, source)
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: m6805_base_device(mconfig, tag, owner, clock, type, name, addr_width, internal_map, shortname, source)
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, device_nvram_interface(mconfig, *this)
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, m_user_rom(*this, DEVICE_SELF, u32(1) << addr_width)
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, m_port_open_drain{ false, false, false, false }
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@ -254,13 +181,13 @@ m68705_new_device::m68705_new_device(
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{
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}
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template <offs_t B> READ8_MEMBER(m68705_new_device::eprom_r)
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template <offs_t B> READ8_MEMBER(m68705_device::eprom_r)
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{
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// read locked out when /VPON and /PLE are asserted
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return (!pcr_vpon() || !pcr_ple()) ? m_user_rom[B + offset] : 0xff;
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}
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template <offs_t B> WRITE8_MEMBER(m68705_new_device::eprom_w)
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template <offs_t B> WRITE8_MEMBER(m68705_device::eprom_w)
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{
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// programming latch enabled when /VPON and /PLE are asserted
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if (pcr_vpon() && pcr_ple())
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@ -278,23 +205,23 @@ template <offs_t B> WRITE8_MEMBER(m68705_new_device::eprom_w)
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}
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}
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template <std::size_t N> void m68705_new_device::set_port_open_drain(bool value)
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template <std::size_t N> void m68705_device::set_port_open_drain(bool value)
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{
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m_port_open_drain[N] = value;
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}
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template <std::size_t N> void m68705_new_device::set_port_mask(u8 mask)
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template <std::size_t N> void m68705_device::set_port_mask(u8 mask)
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{
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m_port_mask[N] = mask;
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}
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template <std::size_t N> READ8_MEMBER(m68705_new_device::port_r)
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template <std::size_t N> READ8_MEMBER(m68705_device::port_r)
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{
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if (!m_port_cb_r[N].isnull()) m_port_input[N] = m_port_cb_r[N](space, 0, ~m_port_ddr[N]);
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return m_port_mask[N] | (m_port_latch[N] & m_port_ddr[N]) | (m_port_input[N] & ~m_port_ddr[N]);
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}
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template <std::size_t N> WRITE8_MEMBER(m68705_new_device::port_latch_w)
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template <std::size_t N> WRITE8_MEMBER(m68705_device::port_latch_w)
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{
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data &= ~m_port_mask[N];
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u8 const diff = m_port_latch[N] ^ data;
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@ -303,7 +230,7 @@ template <std::size_t N> WRITE8_MEMBER(m68705_new_device::port_latch_w)
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port_cb_w<N>();
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}
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template <std::size_t N> WRITE8_MEMBER(m68705_new_device::port_ddr_w)
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template <std::size_t N> WRITE8_MEMBER(m68705_device::port_ddr_w)
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{
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data &= ~m_port_mask[N];
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if (data != m_port_ddr[N])
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@ -313,30 +240,30 @@ template <std::size_t N> WRITE8_MEMBER(m68705_new_device::port_ddr_w)
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}
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}
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template <std::size_t N> void m68705_new_device::port_cb_w()
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template <std::size_t N> void m68705_device::port_cb_w()
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{
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u8 const data(m_port_open_drain[N] ? m_port_latch[N] | ~m_port_ddr[N] : m_port_latch[N]);
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u8 const mask(m_port_open_drain[N] ? (~m_port_latch[N] & m_port_ddr[N]) : m_port_ddr[N]);
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m_port_cb_w[N](space(AS_PROGRAM), 0, data, mask);
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}
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READ8_MEMBER(m68705_new_device::tdr_r)
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READ8_MEMBER(m68705_device::tdr_r)
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{
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return m_tdr;
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}
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WRITE8_MEMBER(m68705_new_device::tdr_w)
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WRITE8_MEMBER(m68705_device::tdr_w)
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{
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m_tdr = data;
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}
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READ8_MEMBER(m68705_new_device::tcr_r)
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READ8_MEMBER(m68705_device::tcr_r)
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{
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// in MOR controlled mode, only TIR, TIM and TOPT are visible
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return m_tcr | (tcr_topt() ? 0x37 : 0x00);
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}
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WRITE8_MEMBER(m68705_new_device::tcr_w)
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WRITE8_MEMBER(m68705_device::tcr_w)
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{
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// 7 TIR RW Timer Interrupt Request Status
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// 6 TIM RW Timer Interrupt Mask
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@ -379,23 +306,23 @@ WRITE8_MEMBER(m68705_new_device::tcr_w)
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set_input_line(M68705_INT_TIMER, CLEAR_LINE);
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}
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READ8_MEMBER(m68705_new_device::misc_r)
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READ8_MEMBER(m68705_device::misc_r)
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{
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logerror("unsupported read MISC\n");
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return 0xff;
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}
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WRITE8_MEMBER(m68705_new_device::misc_w)
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WRITE8_MEMBER(m68705_device::misc_w)
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{
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logerror("unsupported write MISC = %02X\n", data);
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}
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READ8_MEMBER(m68705_new_device::pcr_r)
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READ8_MEMBER(m68705_device::pcr_r)
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{
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return m_pcr;
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}
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WRITE8_MEMBER(m68705_new_device::pcr_w)
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WRITE8_MEMBER(m68705_device::pcr_w)
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{
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// 7 1
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// 6 1
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@ -416,13 +343,13 @@ WRITE8_MEMBER(m68705_new_device::pcr_w)
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m_pcr = (m_pcr & 0xfc) | (data & 0x03);
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}
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READ8_MEMBER(m68705_new_device::acr_r)
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READ8_MEMBER(m68705_device::acr_r)
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{
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logerror("unsupported read ACR\n");
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return 0xff;
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}
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WRITE8_MEMBER(m68705_new_device::acr_w)
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WRITE8_MEMBER(m68705_device::acr_w)
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{
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// 7 conversion complete
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// 6
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@ -450,20 +377,20 @@ WRITE8_MEMBER(m68705_new_device::acr_w)
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logerror("unsupported write ACR = %02X\n", data);
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}
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READ8_MEMBER(m68705_new_device::arr_r)
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READ8_MEMBER(m68705_device::arr_r)
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{
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logerror("unsupported read ARR\n");
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return 0xff;
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}
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WRITE8_MEMBER(m68705_new_device::arr_w)
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WRITE8_MEMBER(m68705_device::arr_w)
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{
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logerror("unsupported write ARR = %02X\n", data);
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}
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void m68705_new_device::device_start()
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void m68705_device::device_start()
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{
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m68705_device::device_start();
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m6805_base_device::device_start();
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save_item(NAME(m_port_input));
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save_item(NAME(m_port_latch));
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@ -496,9 +423,9 @@ void m68705_new_device::device_start()
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m_pl_addr = 0xffff;
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}
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void m68705_new_device::device_reset()
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void m68705_device::device_reset()
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{
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m68705_device::device_reset();
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m6805_base_device::device_reset();
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// reset digital I/O
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port_ddr_w<0>(space(AS_PROGRAM), 0, 0x00, 0xff);
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@ -519,7 +446,7 @@ void m68705_new_device::device_reset()
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RM16(0xfff6, &m_pc);
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}
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void m68705_new_device::execute_set_input(int inputnum, int state)
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void m68705_device::execute_set_input(int inputnum, int state)
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{
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switch (inputnum)
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{
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@ -531,25 +458,59 @@ void m68705_new_device::execute_set_input(int inputnum, int state)
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m_vihtp = (ASSERT_LINE == state) ? ASSERT_LINE : CLEAR_LINE;
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break;
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default:
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m68705_device::execute_set_input(inputnum, state);
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if (m_irq_state[inputnum] != state)
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{
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m_irq_state[inputnum] = (state == ASSERT_LINE) ? ASSERT_LINE : CLEAR_LINE;
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if (state != CLEAR_LINE)
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m_pending_interrupts |= 1 << inputnum;
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}
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}
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}
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void m68705_new_device::nvram_default()
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void m68705_device::nvram_default()
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{
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}
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void m68705_new_device::nvram_read(emu_file &file)
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void m68705_device::nvram_read(emu_file &file)
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{
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file.read(&m_user_rom[0], m_user_rom.bytes());
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}
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void m68705_new_device::nvram_write(emu_file &file)
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void m68705_device::nvram_write(emu_file &file)
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{
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file.write(&m_user_rom[0], m_user_rom.bytes());
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}
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void m68705_new_device::burn_cycles(unsigned count)
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void m68705_device::interrupt()
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{
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if ((m_pending_interrupts & ((1 << M6805_IRQ_LINE) | M68705_INT_MASK)) != 0 )
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{
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if ((CC & IFLAG) == 0)
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{
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PUSHWORD(m_pc);
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PUSHBYTE(m_x);
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PUSHBYTE(m_a);
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PUSHBYTE(m_cc);
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SEI;
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standard_irq_callback(0);
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if ((m_pending_interrupts & (1 << M68705_IRQ_LINE)) != 0 )
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{
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m_pending_interrupts &= ~(1 << M68705_IRQ_LINE);
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RM16(0xfffa, &m_pc);
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}
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else if ((m_pending_interrupts & (1 << M68705_INT_TIMER)) != 0)
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{
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m_pending_interrupts &= ~(1 << M68705_INT_TIMER);
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RM16(0xfff8, &m_pc);
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}
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}
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m_icount -= 11;
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}
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}
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void m68705_device::burn_cycles(unsigned count)
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{
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// handle internal timer/counter source
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if (!tcr_tin()) // TODO: check tcr_tie() and gate on TIMER if appropriate
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@ -569,24 +530,24 @@ void m68705_new_device::burn_cycles(unsigned count)
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}
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}
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template <std::size_t N> void m68705_new_device::add_port_latch_state()
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template <std::size_t N> void m68705_device::add_port_latch_state()
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{
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state_add(M68705_LATCHA + N, util::string_format("LATCH%c", 'A' + N).c_str(), m_port_latch[N]).mask(~m_port_mask[N] & 0xff);
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}
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template <std::size_t N> void m68705_new_device::add_port_ddr_state()
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template <std::size_t N> void m68705_device::add_port_ddr_state()
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{
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state_add(M68705_DDRA + N, util::string_format("DDR%c", 'A' + N).c_str(), m_port_ddr[N]).mask(~m_port_mask[N] & 0xff);
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}
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void m68705_new_device::add_timer_state()
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void m68705_device::add_timer_state()
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{
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state_add(M68705_PS, "PS", m_prescaler).mask(0x7f);
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state_add(M68705_TDR, "TDR", m_tdr).mask(0xff);
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state_add(M68705_TCR, "TCR", m_tcr).mask(0xff);
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}
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void m68705_new_device::add_eprom_state()
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void m68705_device::add_eprom_state()
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{
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state_add(M68705_PCR, "PCR", m_pcr).mask(0xff);
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state_add(M68705_PLA, "PLA", m_pl_addr).mask(0xffff);
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@ -630,7 +591,7 @@ m68705p_device::m68705p_device(
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char const *name,
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char const *shortname,
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char const *source)
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: m68705_new_device(mconfig, tag, owner, clock, type, name, 11, address_map_delegate(FUNC(m68705p_device::p_map), this), shortname, source)
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: m68705_device(mconfig, tag, owner, clock, type, name, 11, address_map_delegate(FUNC(m68705p_device::p_map), this), shortname, source)
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{
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set_port_open_drain<0>(true); // Port A is open drain with internal pull-ups
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set_port_mask<2>(0xf0); // Port C is four bits wide
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@ -639,7 +600,7 @@ m68705p_device::m68705p_device(
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void m68705p_device::device_start()
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{
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m68705_new_device::device_start();
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m68705_device::device_start();
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add_port_latch_state<0>();
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add_port_latch_state<1>();
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@ -701,7 +662,7 @@ m68705u_device::m68705u_device(
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address_map_delegate internal_map,
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char const *shortname,
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char const *source)
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: m68705_new_device(mconfig, tag, owner, clock, type, name, 12, internal_map, shortname, source)
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: m68705_device(mconfig, tag, owner, clock, type, name, 12, internal_map, shortname, source)
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{
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set_port_open_drain<0>(true); // Port A is open drain with internal pull-ups
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}
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@ -721,7 +682,7 @@ m68705u_device::m68705u_device(
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void m68705u_device::device_start()
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{
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m68705_new_device::device_start();
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m68705_device::device_start();
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add_port_latch_state<0>();
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add_port_latch_state<1>();
|
||||
|
||||
@ -7,11 +7,11 @@
|
||||
|
||||
#include "m6805.h"
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// GLOBAL VARIABLES
|
||||
//**************************************************************************
|
||||
|
||||
extern device_type const M68705;
|
||||
extern device_type const M68705P3;
|
||||
extern device_type const M68705P5;
|
||||
extern device_type const M68705R3;
|
||||
@ -24,10 +24,36 @@ extern device_type const M68705U3;
|
||||
|
||||
// ======================> m68705_device
|
||||
|
||||
class m68705_device : public m6805_base_device
|
||||
#define MCFG_M68705_PORTA_R_CB(obj) \
|
||||
devcb = &m68705_device::set_port_cb_r<0>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTB_R_CB(obj) \
|
||||
devcb = &m68705_device::set_port_cb_r<1>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTC_R_CB(obj) \
|
||||
devcb = &m68705_device::set_port_cb_r<2>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTD_R_CB(obj) \
|
||||
devcb = &m68705_device::set_port_cb_r<3>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTA_W_CB(obj) \
|
||||
devcb = &m68705_device::set_port_cb_w<0>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTB_W_CB(obj) \
|
||||
devcb = &m68705_device::set_port_cb_w<1>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTC_W_CB(obj) \
|
||||
devcb = &m68705_device::set_port_cb_w<2>(*device, DEVCB_##obj);
|
||||
|
||||
|
||||
class m68705_device : public m6805_base_device, public device_nvram_interface
|
||||
{
|
||||
public:
|
||||
m68705_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
|
||||
// static configuration helpers
|
||||
template<std::size_t N, typename Object> static devcb_base &set_port_cb_r(device_t &device, Object &&obj)
|
||||
{ return downcast<m68705_device &>(device).m_port_cb_r[N].set_callback(std::forward<Object>(obj)); }
|
||||
template<std::size_t N, typename Object> static devcb_base &set_port_cb_w(device_t &device, Object &&obj)
|
||||
{ return downcast<m68705_device &>(device).m_port_cb_w[N].set_callback(std::forward<Object>(obj)); }
|
||||
|
||||
protected:
|
||||
enum
|
||||
@ -37,63 +63,8 @@ protected:
|
||||
M68705_S = M6805_S,
|
||||
M68705_X = M6805_X,
|
||||
M68705_CC = M6805_CC,
|
||||
M68705_IRQ_STATE = M6805_IRQ_STATE
|
||||
};
|
||||
M68705_IRQ_STATE = M6805_IRQ_STATE,
|
||||
|
||||
m68705_device(
|
||||
machine_config const &mconfig,
|
||||
char const *tag,
|
||||
device_t *owner,
|
||||
u32 clock,
|
||||
device_type type,
|
||||
char const *name,
|
||||
u32 addr_width,
|
||||
address_map_delegate internal_map,
|
||||
char const *shortname,
|
||||
char const *source);
|
||||
|
||||
virtual void device_reset() override;
|
||||
virtual void execute_set_input(int inputnum, int state) override;
|
||||
virtual void interrupt() override;
|
||||
};
|
||||
|
||||
|
||||
// ======================> m68705_new_device
|
||||
|
||||
#define MCFG_M68705_PORTA_R_CB(obj) \
|
||||
devcb = &m68705_new_device::set_port_cb_r<0>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTB_R_CB(obj) \
|
||||
devcb = &m68705_new_device::set_port_cb_r<1>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTC_R_CB(obj) \
|
||||
devcb = &m68705_new_device::set_port_cb_r<2>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTD_R_CB(obj) \
|
||||
devcb = &m68705_new_device::set_port_cb_r<3>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTA_W_CB(obj) \
|
||||
devcb = &m68705_new_device::set_port_cb_w<0>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTB_W_CB(obj) \
|
||||
devcb = &m68705_new_device::set_port_cb_w<1>(*device, DEVCB_##obj);
|
||||
|
||||
#define MCFG_M68705_PORTC_W_CB(obj) \
|
||||
devcb = &m68705_new_device::set_port_cb_w<2>(*device, DEVCB_##obj);
|
||||
|
||||
|
||||
class m68705_new_device : public m68705_device, public device_nvram_interface
|
||||
{
|
||||
public:
|
||||
// static configuration helpers
|
||||
template<std::size_t N, typename Object> static devcb_base &set_port_cb_r(device_t &device, Object &&obj)
|
||||
{ return downcast<m68705_new_device &>(device).m_port_cb_r[N].set_callback(std::forward<Object>(obj)); }
|
||||
template<std::size_t N, typename Object> static devcb_base &set_port_cb_w(device_t &device, Object &&obj)
|
||||
{ return downcast<m68705_new_device &>(device).m_port_cb_w[N].set_callback(std::forward<Object>(obj)); }
|
||||
|
||||
protected:
|
||||
enum
|
||||
{
|
||||
M68705_LATCHA = 0x10,
|
||||
M68705_LATCHB,
|
||||
M68705_LATCHC,
|
||||
@ -119,7 +90,7 @@ protected:
|
||||
PORT_COUNT = 4
|
||||
};
|
||||
|
||||
m68705_new_device(
|
||||
m68705_device(
|
||||
machine_config const &mconfig,
|
||||
char const *tag,
|
||||
device_t *owner,
|
||||
@ -165,6 +136,7 @@ protected:
|
||||
virtual void nvram_read(emu_file &file) override;
|
||||
virtual void nvram_write(emu_file &file) override;
|
||||
|
||||
virtual void interrupt() override;
|
||||
virtual void burn_cycles(unsigned count) override;
|
||||
|
||||
u8 *const get_user_rom() const { return &m_user_rom[0]; }
|
||||
@ -213,7 +185,7 @@ private:
|
||||
|
||||
// ======================> m68705p_device
|
||||
|
||||
class m68705p_device : public m68705_new_device
|
||||
class m68705p_device : public m68705_device
|
||||
{
|
||||
public:
|
||||
DECLARE_WRITE8_MEMBER(pa_w) { port_input_w<0>(space, offset, data, mem_mask); }
|
||||
@ -246,7 +218,7 @@ protected:
|
||||
|
||||
// ======================> m68705u_device
|
||||
|
||||
class m68705u_device : public m68705_new_device
|
||||
class m68705u_device : public m68705_device
|
||||
{
|
||||
public:
|
||||
DECLARE_WRITE8_MEMBER(pa_w) { port_input_w<0>(space, offset, data, mem_mask); }
|
||||
|
||||
@ -6,28 +6,63 @@ Motorola M68HC05EVS evaluation system
|
||||
|
||||
Chips:
|
||||
Main board: XC68HC26P, R65C52P2, MS62256l-70PC, MS6264L-70PC, eprom. Xtal = 3.6864MHz
|
||||
Emulator board: MC68C705P9CP, undumped 28-pin prom. Xtal = 4MHz
|
||||
Emulator board: MC68HC705P9CP, undumped 28-pin prom. Xtal = 4MHz
|
||||
|
||||
R65C52 = Dual ACIA with inbuilt baud rate divider, uses 8 addresses, uses the 3.6864MHz crystal
|
||||
XC68HC26P = PPI (3 ports), uses 8 addresses.
|
||||
|
||||
2014-01-12 Skeleton driver
|
||||
|
||||
The rom is larger than the available address space, but not all of it is programmed. The code
|
||||
ranges are 800-18FF,1FF0-1FFF. There must be a banking scheme in use.
|
||||
Memory map:
|
||||
0000, 0000 PORTA Port A data register
|
||||
0001, 0001 PORTB Port B data register
|
||||
0002, 0002 PORTC Port C data register
|
||||
0003, 0003 PORTD Port D data register
|
||||
0004, 0004 DDRA Data direction register A
|
||||
0005, 0005 DDRB Data direction register B
|
||||
0006, 0006 DDRC Data direction register C
|
||||
0007, 0007 DDRD Data direction register D
|
||||
0008, 0009 unimplemented
|
||||
000A, 000A SCR SIOP control register
|
||||
000B, 000B SSR SIOP status register
|
||||
0009, 0009 SDR SIOP data register
|
||||
000D, 0011 unimplemented
|
||||
0012, 0012 TCR Timer control register
|
||||
0013, 0013 TDR Timer data register
|
||||
0014, 0014 ICRH Input capture register high
|
||||
0015, 0015 ICRL Input capture register low
|
||||
0016, 0016 OCRH Output compare register high
|
||||
0017, 0017 OCRL Output compare register low
|
||||
0018, 0018 TRH Timer register high
|
||||
0019, 0019 TRL Timer register low
|
||||
001A, 001A ATRH Alternate timer register high
|
||||
001B, 001B ATRL Alternate timer register low
|
||||
001C, 001C EPROG EPROM programming register
|
||||
001D, 001D ADDR ADC data register
|
||||
001E, 001E ADSCR ADC status/control register
|
||||
001F, 001F reserved
|
||||
0020, 004F Page zero user EPROM
|
||||
0050, 007F unimplemented
|
||||
0080, 00FF RAM
|
||||
0100, 08FF User EPROM
|
||||
0900, 0900 MOR Mask option register
|
||||
0901, 1EFF unimplemented
|
||||
1F00, 1FEF Bootloader ROM
|
||||
1FF1, 1FF7 reserved
|
||||
1FF8, 1FF9 Timer interrupt vector
|
||||
1FFA, 1FFB External interrupt vector
|
||||
1FFC, 1FFD Software interrupt vector
|
||||
1FFE, 1FFF Reset vector
|
||||
|
||||
Memory map guess
|
||||
000-07F Stack (and user ram?)
|
||||
080-0FF RAM (or devices?)
|
||||
100-FFF ROM
|
||||
|
||||
ToDo:
|
||||
- Add CMOS family support to M6085 CPU core (different timings, different peripherals)
|
||||
- Everything
|
||||
|
||||
******************************************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/m6805/m68705.h"
|
||||
#include "cpu/m6805/m6805.h"
|
||||
|
||||
|
||||
class m6805evs_state : public driver_device
|
||||
@ -45,10 +80,15 @@ private:
|
||||
|
||||
|
||||
static ADDRESS_MAP_START( m6805evs_mem, AS_PROGRAM, 8, m6805evs_state )
|
||||
AM_RANGE(0x0000, 0x00ff) AM_RAM
|
||||
AM_RANGE(0x0100, 0x07ff) AM_ROM AM_REGION("roms", 0x1100)
|
||||
AM_RANGE(0x0800, 0x0fef) AM_ROM AM_REGION("roms", 0x0800)
|
||||
AM_RANGE(0x0ff0, 0x0fff) AM_ROM AM_REGION("roms", 0x1ff0)
|
||||
ADDRESS_MAP_GLOBAL_MASK(0x1fff)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
|
||||
// AM_RANGE(0x0000, 0x001f) I/O registers live here
|
||||
AM_RANGE(0x0020, 0x004f) AM_ROM AM_REGION("eprom", 0x0020)
|
||||
AM_RANGE(0x0080, 0x00ff) AM_RAM
|
||||
AM_RANGE(0x0100, 0x0900) AM_ROM AM_REGION("eprom", 0x0100)
|
||||
// AM_RANGE(0x1f00, 0x1fef) bootloader ROM lives here
|
||||
AM_RANGE(0x1ff8, 0x1fff) AM_ROM AM_REGION("eprom", 0x1ff0)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static INPUT_PORTS_START( m6805evs )
|
||||
@ -60,12 +100,12 @@ void m6805evs_state::machine_reset()
|
||||
|
||||
static MACHINE_CONFIG_START( m6805evs, m6805evs_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M68705, XTAL_4MHz)
|
||||
MCFG_CPU_ADD("maincpu", M6805, XTAL_4MHz)
|
||||
MCFG_CPU_PROGRAM_MAP(m6805evs_mem)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
ROM_START(m6805evs)
|
||||
ROM_REGION(0x2000, "roms", 0)
|
||||
ROM_REGION(0x2000, "eprom", 0)
|
||||
ROM_LOAD( "evsbug12.bin", 0x0000, 0x2000, CRC(8b581aef) SHA1(eacf425cc8a042085ccc4097cc61570b633b1e38) )
|
||||
ROM_END
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user