From 48390440635f95ee4ec4d958a65e720c4f1f038f Mon Sep 17 00:00:00 2001 From: Laurent Desnogues Date: Sat, 16 Feb 2008 16:35:07 +0000 Subject: [PATCH] cosmetics --- src/emu/cpu/arm7/arm7.c | 533 +++++++++-------- src/emu/cpu/arm7/arm7core.c | 1126 ++++++++++++++++++----------------- src/emu/cpu/arm7/arm7core.h | 377 ++++++------ 3 files changed, 1018 insertions(+), 1018 deletions(-) diff --git a/src/emu/cpu/arm7/arm7.c b/src/emu/cpu/arm7/arm7.c index 1963543f3c4..f7866e74f75 100644 --- a/src/emu/cpu/arm7/arm7.c +++ b/src/emu/cpu/arm7/arm7.c @@ -42,17 +42,17 @@ /* Example for showing how Co-Proc functions work */ #define TEST_COPROC_FUNCS 1 -/*prototypes*/ +/* prototypes */ #if TEST_COPROC_FUNCS static WRITE32_HANDLER(test_do_callback); static READ32_HANDLER(test_rt_r_callback); static WRITE32_HANDLER(test_rt_w_callback); -static void test_dt_r_callback (UINT32 insn, UINT32* prn, UINT32 (*read32)(int addr)); -static void test_dt_w_callback (UINT32 insn, UINT32* prn, void (*write32)(int addr, UINT32 data)); +static void test_dt_r_callback(UINT32 insn, UINT32 *prn, UINT32 (*read32)(UINT32 addr)); +static void test_dt_w_callback(UINT32 insn, UINT32 *prn, void (*write32)(UINT32 addr, UINT32 data)); #ifdef ENABLE_DEBUGGER -static char *Spec_RT( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); -static char *Spec_DT( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); -static char *Spec_DO( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); +static char *Spec_RT(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); +static char *Spec_DT(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); +static char *Spec_DO(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); #endif #endif @@ -76,7 +76,7 @@ static char *Spec_DO( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBu /* CPU Registers */ typedef struct { - ARM7CORE_REGS //these must be included in your cpu specific register implementation + ARM7CORE_REGS // these must be included in your cpu specific register implementation } ARM7_REGS; static ARM7_REGS arm7; @@ -90,80 +90,78 @@ static int ARM7_ICOUNT; **************************************************************************/ static void arm7_init(int index, int clock, const void *config, int (*irqcallback)(int)) { - //must call core - arm7_core_init("arm7", index); + // must call core + arm7_core_init("arm7", index); - ARM7.irq_callback = irqcallback; + ARM7.irq_callback = irqcallback; #if TEST_COPROC_FUNCS - //setup co-proc callbacks example - arm7_coproc_do_callback = test_do_callback; - arm7_coproc_rt_r_callback = test_rt_r_callback; - arm7_coproc_rt_w_callback = test_rt_w_callback; - arm7_coproc_dt_r_callback = test_dt_r_callback; - arm7_coproc_dt_w_callback = test_dt_w_callback; + // setup co-proc callbacks example + arm7_coproc_do_callback = test_do_callback; + arm7_coproc_rt_r_callback = test_rt_r_callback; + arm7_coproc_rt_w_callback = test_rt_w_callback; + arm7_coproc_dt_r_callback = test_dt_r_callback; + arm7_coproc_dt_w_callback = test_dt_w_callback; #ifdef ENABLE_DEBUGGER - //setup dasm callbacks - direct method example - arm7_dasm_cop_dt_callback = Spec_DT; - arm7_dasm_cop_rt_callback = Spec_RT; - arm7_dasm_cop_do_callback = Spec_DO; + // setup dasm callbacks - direct method example + arm7_dasm_cop_dt_callback = Spec_DT; + arm7_dasm_cop_rt_callback = Spec_RT; + arm7_dasm_cop_do_callback = Spec_DO; #endif #endif - - return; } static void arm7_reset(void) { - //must call core reset - arm7_core_reset(); + // must call core reset + arm7_core_reset(); } static void arm7_exit(void) { - /* nothing to do here */ + /* nothing to do here */ } -static int arm7_execute( int cycles ) +static int arm7_execute(int cycles) { -/*include the arm7 core execute code*/ +/* include the arm7 core execute code */ #include "arm7exec.c" -} /* arm7_execute */ +} static void set_irq_line(int irqline, int state) { - //must call core - arm7_core_set_irq_line(irqline,state); + // must call core + arm7_core_set_irq_line(irqline,state); } static void arm7_get_context(void *dst) { - if( dst ) - { - memcpy( dst, &ARM7, sizeof(ARM7) ); - } + if (dst) + { + memcpy(dst, &ARM7, sizeof(ARM7)); + } } static void arm7_set_context(void *src) { - if (src) - { - memcpy( &ARM7, src, sizeof(ARM7) ); - } + if (src) + { + memcpy(&ARM7, src, sizeof(ARM7)); + } } #ifdef ENABLE_DEBUGGER static offs_t arm7_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram) { - if( T_IS_SET(GET_CPSR) ) - { - return thumb_disasm( buffer, pc, oprom[0] | (oprom[1] << 8)) | 2; - } - else - { - return arm7_disasm( buffer, pc, oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24)) | 4; - } + if (T_IS_SET(GET_CPSR)) + { + return thumb_disasm(buffer, pc, oprom[0] | (oprom[1] << 8)) | 2; + } + else + { + return arm7_disasm(buffer, pc, oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24)) | 4; + } } #endif /* ENABLE_DEBUGGER */ @@ -174,70 +172,70 @@ static offs_t arm7_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 static void arm7_set_info(UINT32 state, cpuinfo *info) { - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ + switch (state) + { + /* --- the following bits of info are set as 64-bit signed integers --- */ - /* interrupt lines/exceptions */ - case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(ARM7_IRQ_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(ARM7_FIRQ_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(ARM7_ABORT_EXCEPTION, info->i); break; - case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break; - case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(ARM7_UNDEFINE_EXCEPTION, info->i); break; + /* interrupt lines/exceptions */ + case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(ARM7_IRQ_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(ARM7_FIRQ_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(ARM7_ABORT_EXCEPTION, info->i); break; + case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break; + case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(ARM7_UNDEFINE_EXCEPTION, info->i); break; - /* registers shared by all operating modes */ - case CPUINFO_INT_REGISTER + ARM7_R0: ARM7REG( 0) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R1: ARM7REG( 1) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R2: ARM7REG( 2) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R3: ARM7REG( 3) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R4: ARM7REG( 4) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R5: ARM7REG( 5) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R6: ARM7REG( 6) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R7: ARM7REG( 7) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R8: ARM7REG( 8) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R9: ARM7REG( 9) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R10: ARM7REG(10) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R11: ARM7REG(11) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R12: ARM7REG(12) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R13: ARM7REG(13) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R14: ARM7REG(14) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_R15: ARM7REG(15) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_CPSR: SET_CPSR(info->i); break; + /* registers shared by all operating modes */ + case CPUINFO_INT_REGISTER + ARM7_R0: ARM7REG( 0) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R1: ARM7REG( 1) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R2: ARM7REG( 2) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R3: ARM7REG( 3) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R4: ARM7REG( 4) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R5: ARM7REG( 5) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R6: ARM7REG( 6) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R7: ARM7REG( 7) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R8: ARM7REG( 8) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R9: ARM7REG( 9) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R10: ARM7REG(10) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R11: ARM7REG(11) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R12: ARM7REG(12) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R13: ARM7REG(13) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R14: ARM7REG(14) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_R15: ARM7REG(15) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_CPSR: SET_CPSR(info->i); break; - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + ARM7_PC: R15 = info->i; break; - case CPUINFO_INT_SP: SetRegister(13,info->i); break; + case CPUINFO_INT_PC: + case CPUINFO_INT_REGISTER + ARM7_PC: R15 = info->i; break; + case CPUINFO_INT_SP: SetRegister(13,info->i); break; - /* FIRQ Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_FR8: ARM7REG(eR8_FIQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_FR9: ARM7REG(eR9_FIQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_FR10: ARM7REG(eR10_FIQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_FR11: ARM7REG(eR11_FIQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_FR12: ARM7REG(eR12_FIQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_FR13: ARM7REG(eR13_FIQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_FR14: ARM7REG(eR14_FIQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_FSPSR: ARM7REG(eSPSR_FIQ) = info->i; break; + /* FIRQ Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_FR8: ARM7REG(eR8_FIQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_FR9: ARM7REG(eR9_FIQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_FR10: ARM7REG(eR10_FIQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_FR11: ARM7REG(eR11_FIQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_FR12: ARM7REG(eR12_FIQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_FR13: ARM7REG(eR13_FIQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_FR14: ARM7REG(eR14_FIQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_FSPSR: ARM7REG(eSPSR_FIQ) = info->i; break; - /* IRQ Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_IR13: ARM7REG(eR13_IRQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_IR14: ARM7REG(eR14_IRQ) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_ISPSR: ARM7REG(eSPSR_IRQ) = info->i; break; + /* IRQ Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_IR13: ARM7REG(eR13_IRQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_IR14: ARM7REG(eR14_IRQ) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_ISPSR: ARM7REG(eSPSR_IRQ) = info->i; break; - /* Supervisor Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_SR13: ARM7REG(eR13_SVC) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_SR14: ARM7REG(eR14_SVC) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_SSPSR: ARM7REG(eSPSR_SVC) = info->i; break; + /* Supervisor Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_SR13: ARM7REG(eR13_SVC) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_SR14: ARM7REG(eR14_SVC) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_SSPSR: ARM7REG(eSPSR_SVC) = info->i; break; - /* Abort Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_AR13: ARM7REG(eR13_ABT) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_AR14: ARM7REG(eR14_ABT) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_ASPSR: ARM7REG(eSPSR_ABT) = info->i; break; + /* Abort Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_AR13: ARM7REG(eR13_ABT) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_AR14: ARM7REG(eR14_ABT) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_ASPSR: ARM7REG(eSPSR_ABT) = info->i; break; - /* Undefined Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_UR13: ARM7REG(eR13_UND) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_UR14: ARM7REG(eR14_UND) = info->i; break; - case CPUINFO_INT_REGISTER + ARM7_USPSR: ARM7REG(eSPSR_UND) = info->i; break; - } + /* Undefined Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_UR13: ARM7REG(eR13_UND) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_UR14: ARM7REG(eR14_UND) = info->i; break; + case CPUINFO_INT_REGISTER + ARM7_USPSR: ARM7REG(eSPSR_UND) = info->i; break; + } } @@ -248,174 +246,174 @@ static void arm7_set_info(UINT32 state, cpuinfo *info) void arm7_get_info(UINT32 state, cpuinfo *info) { - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ + switch (state) + { + /* --- the following bits of info are returned as 64-bit signed integers --- */ - /* cpu implementation data */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(ARM7); break; - case CPUINFO_INT_INPUT_LINES: info->i = ARM7_NUM_LINES; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 3; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 4; break; + /* cpu implementation data */ + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(ARM7); break; + case CPUINFO_INT_INPUT_LINES: info->i = ARM7_NUM_LINES; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; + case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 3; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 4; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; - /* interrupt lines/exceptions */ - case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = ARM7.pendingIrq; break; - case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = ARM7.pendingFiq; break; - case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = ARM7.pendingAbtD; break; - case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = ARM7.pendingAbtP; break; - case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = ARM7.pendingUnd; break; + /* interrupt lines/exceptions */ + case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = ARM7.pendingIrq; break; + case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = ARM7.pendingFiq; break; + case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = ARM7.pendingAbtD; break; + case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = ARM7.pendingAbtP; break; + case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = ARM7.pendingUnd; break; - /* registers shared by all operating modes */ - case CPUINFO_INT_REGISTER + ARM7_R0: info->i = ARM7REG( 0); break; - case CPUINFO_INT_REGISTER + ARM7_R1: info->i = ARM7REG( 1); break; - case CPUINFO_INT_REGISTER + ARM7_R2: info->i = ARM7REG( 2); break; - case CPUINFO_INT_REGISTER + ARM7_R3: info->i = ARM7REG( 3); break; - case CPUINFO_INT_REGISTER + ARM7_R4: info->i = ARM7REG( 4); break; - case CPUINFO_INT_REGISTER + ARM7_R5: info->i = ARM7REG( 5); break; - case CPUINFO_INT_REGISTER + ARM7_R6: info->i = ARM7REG( 6); break; - case CPUINFO_INT_REGISTER + ARM7_R7: info->i = ARM7REG( 7); break; - case CPUINFO_INT_REGISTER + ARM7_R8: info->i = ARM7REG( 8); break; - case CPUINFO_INT_REGISTER + ARM7_R9: info->i = ARM7REG( 9); break; - case CPUINFO_INT_REGISTER + ARM7_R10: info->i = ARM7REG(10); break; - case CPUINFO_INT_REGISTER + ARM7_R11: info->i = ARM7REG(11); break; - case CPUINFO_INT_REGISTER + ARM7_R12: info->i = ARM7REG(12); break; - case CPUINFO_INT_REGISTER + ARM7_R13: info->i = ARM7REG(13); break; - case CPUINFO_INT_REGISTER + ARM7_R14: info->i = ARM7REG(14); break; - case CPUINFO_INT_REGISTER + ARM7_R15: info->i = ARM7REG(15); break; + /* registers shared by all operating modes */ + case CPUINFO_INT_REGISTER + ARM7_R0: info->i = ARM7REG( 0); break; + case CPUINFO_INT_REGISTER + ARM7_R1: info->i = ARM7REG( 1); break; + case CPUINFO_INT_REGISTER + ARM7_R2: info->i = ARM7REG( 2); break; + case CPUINFO_INT_REGISTER + ARM7_R3: info->i = ARM7REG( 3); break; + case CPUINFO_INT_REGISTER + ARM7_R4: info->i = ARM7REG( 4); break; + case CPUINFO_INT_REGISTER + ARM7_R5: info->i = ARM7REG( 5); break; + case CPUINFO_INT_REGISTER + ARM7_R6: info->i = ARM7REG( 6); break; + case CPUINFO_INT_REGISTER + ARM7_R7: info->i = ARM7REG( 7); break; + case CPUINFO_INT_REGISTER + ARM7_R8: info->i = ARM7REG( 8); break; + case CPUINFO_INT_REGISTER + ARM7_R9: info->i = ARM7REG( 9); break; + case CPUINFO_INT_REGISTER + ARM7_R10: info->i = ARM7REG(10); break; + case CPUINFO_INT_REGISTER + ARM7_R11: info->i = ARM7REG(11); break; + case CPUINFO_INT_REGISTER + ARM7_R12: info->i = ARM7REG(12); break; + case CPUINFO_INT_REGISTER + ARM7_R13: info->i = ARM7REG(13); break; + case CPUINFO_INT_REGISTER + ARM7_R14: info->i = ARM7REG(14); break; + case CPUINFO_INT_REGISTER + ARM7_R15: info->i = ARM7REG(15); break; - case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* not implemented */ break; - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + ARM7_PC: info->i = R15; break; - case CPUINFO_INT_SP: info->i = GetRegister(13); break; + case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* not implemented */ break; + case CPUINFO_INT_PC: + case CPUINFO_INT_REGISTER + ARM7_PC: info->i = R15; break; + case CPUINFO_INT_SP: info->i = GetRegister(13); break; - /* FIRQ Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_FR8: info->i = ARM7REG(eR8_FIQ); break; - case CPUINFO_INT_REGISTER + ARM7_FR9: info->i = ARM7REG(eR9_FIQ); break; - case CPUINFO_INT_REGISTER + ARM7_FR10: info->i = ARM7REG(eR10_FIQ); break; - case CPUINFO_INT_REGISTER + ARM7_FR11: info->i = ARM7REG(eR11_FIQ); break; - case CPUINFO_INT_REGISTER + ARM7_FR12: info->i = ARM7REG(eR12_FIQ); break; - case CPUINFO_INT_REGISTER + ARM7_FR13: info->i = ARM7REG(eR13_FIQ); break; - case CPUINFO_INT_REGISTER + ARM7_FR14: info->i = ARM7REG(eR14_FIQ); break; - case CPUINFO_INT_REGISTER + ARM7_FSPSR: info->i = ARM7REG(eSPSR_FIQ); break; + /* FIRQ Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_FR8: info->i = ARM7REG(eR8_FIQ); break; + case CPUINFO_INT_REGISTER + ARM7_FR9: info->i = ARM7REG(eR9_FIQ); break; + case CPUINFO_INT_REGISTER + ARM7_FR10: info->i = ARM7REG(eR10_FIQ); break; + case CPUINFO_INT_REGISTER + ARM7_FR11: info->i = ARM7REG(eR11_FIQ); break; + case CPUINFO_INT_REGISTER + ARM7_FR12: info->i = ARM7REG(eR12_FIQ); break; + case CPUINFO_INT_REGISTER + ARM7_FR13: info->i = ARM7REG(eR13_FIQ); break; + case CPUINFO_INT_REGISTER + ARM7_FR14: info->i = ARM7REG(eR14_FIQ); break; + case CPUINFO_INT_REGISTER + ARM7_FSPSR: info->i = ARM7REG(eSPSR_FIQ); break; - /* IRQ Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_IR13: info->i = ARM7REG(eR13_IRQ); break; - case CPUINFO_INT_REGISTER + ARM7_IR14: info->i = ARM7REG(eR14_IRQ); break; - case CPUINFO_INT_REGISTER + ARM7_ISPSR: info->i = ARM7REG(eSPSR_IRQ); break; + /* IRQ Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_IR13: info->i = ARM7REG(eR13_IRQ); break; + case CPUINFO_INT_REGISTER + ARM7_IR14: info->i = ARM7REG(eR14_IRQ); break; + case CPUINFO_INT_REGISTER + ARM7_ISPSR: info->i = ARM7REG(eSPSR_IRQ); break; - /* Supervisor Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_SR13: info->i = ARM7REG(eR13_SVC); break; - case CPUINFO_INT_REGISTER + ARM7_SR14: info->i = ARM7REG(eR14_SVC); break; - case CPUINFO_INT_REGISTER + ARM7_SSPSR: info->i = ARM7REG(eSPSR_SVC); break; + /* Supervisor Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_SR13: info->i = ARM7REG(eR13_SVC); break; + case CPUINFO_INT_REGISTER + ARM7_SR14: info->i = ARM7REG(eR14_SVC); break; + case CPUINFO_INT_REGISTER + ARM7_SSPSR: info->i = ARM7REG(eSPSR_SVC); break; - /* Abort Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_AR13: info->i = ARM7REG(eR13_ABT); break; - case CPUINFO_INT_REGISTER + ARM7_AR14: info->i = ARM7REG(eR14_ABT); break; - case CPUINFO_INT_REGISTER + ARM7_ASPSR: info->i = ARM7REG(eSPSR_ABT); break; + /* Abort Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_AR13: info->i = ARM7REG(eR13_ABT); break; + case CPUINFO_INT_REGISTER + ARM7_AR14: info->i = ARM7REG(eR14_ABT); break; + case CPUINFO_INT_REGISTER + ARM7_ASPSR: info->i = ARM7REG(eSPSR_ABT); break; - /* Undefined Mode Shadowed Registers */ - case CPUINFO_INT_REGISTER + ARM7_UR13: info->i = ARM7REG(eR13_UND); break; - case CPUINFO_INT_REGISTER + ARM7_UR14: info->i = ARM7REG(eR14_UND); break; - case CPUINFO_INT_REGISTER + ARM7_USPSR: info->i = ARM7REG(eSPSR_UND); break; + /* Undefined Mode Shadowed Registers */ + case CPUINFO_INT_REGISTER + ARM7_UR13: info->i = ARM7REG(eR13_UND); break; + case CPUINFO_INT_REGISTER + ARM7_UR14: info->i = ARM7REG(eR14_UND); break; + case CPUINFO_INT_REGISTER + ARM7_USPSR: info->i = ARM7REG(eSPSR_UND); break; - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_PTR_SET_INFO: info->setinfo = arm7_set_info; break; - case CPUINFO_PTR_GET_CONTEXT: info->getcontext = arm7_get_context; break; - case CPUINFO_PTR_SET_CONTEXT: info->setcontext = arm7_set_context; break; - case CPUINFO_PTR_INIT: info->init = arm7_init; break; - case CPUINFO_PTR_RESET: info->reset = arm7_reset; break; - case CPUINFO_PTR_EXIT: info->exit = arm7_exit; break; - case CPUINFO_PTR_EXECUTE: info->execute = arm7_execute; break; - case CPUINFO_PTR_BURN: info->burn = NULL; break; + /* --- the following bits of info are returned as pointers to data or functions --- */ + case CPUINFO_PTR_SET_INFO: info->setinfo = arm7_set_info; break; + case CPUINFO_PTR_GET_CONTEXT: info->getcontext = arm7_get_context; break; + case CPUINFO_PTR_SET_CONTEXT: info->setcontext = arm7_set_context; break; + case CPUINFO_PTR_INIT: info->init = arm7_init; break; + case CPUINFO_PTR_RESET: info->reset = arm7_reset; break; + case CPUINFO_PTR_EXIT: info->exit = arm7_exit; break; + case CPUINFO_PTR_EXECUTE: info->execute = arm7_execute; break; + case CPUINFO_PTR_BURN: info->burn = NULL; break; #ifdef ENABLE_DEBUGGER - case CPUINFO_PTR_DISASSEMBLE: info->disassemble = arm7_dasm; break; + case CPUINFO_PTR_DISASSEMBLE: info->disassemble = arm7_dasm; break; #endif /* ENABLE_DEBUGGER */ - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &ARM7_ICOUNT; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &ARM7_ICOUNT; break; - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "ARM7"); break; - case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Acorn Risc Machine"); break; - case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.3"); break; - case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff, sellenoff@hotmail.com"); break; + /* --- the following bits of info are returned as NULL-terminated strings --- */ + case CPUINFO_STR_NAME: strcpy(info->s, "ARM7"); break; + case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Acorn Risc Machine"); break; + case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.3"); break; + case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff, sellenoff@hotmail.com"); break; - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c %s", - (ARM7REG(eCPSR) & N_MASK) ? 'N' : '-', - (ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-', - (ARM7REG(eCPSR) & C_MASK) ? 'C' : '-', - (ARM7REG(eCPSR) & V_MASK) ? 'V' : '-', - (ARM7REG(eCPSR) & I_MASK) ? 'I' : '-', - (ARM7REG(eCPSR) & F_MASK) ? 'F' : '-', - (ARM7REG(eCPSR) & T_MASK) ? 'T' : '-', - GetModeText(ARM7REG(eCPSR))); - break; + case CPUINFO_STR_FLAGS: + sprintf(info->s, "%c%c%c%c%c%c%c %s", + (ARM7REG(eCPSR) & N_MASK) ? 'N' : '-', + (ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-', + (ARM7REG(eCPSR) & C_MASK) ? 'C' : '-', + (ARM7REG(eCPSR) & V_MASK) ? 'V' : '-', + (ARM7REG(eCPSR) & I_MASK) ? 'I' : '-', + (ARM7REG(eCPSR) & F_MASK) ? 'F' : '-', + (ARM7REG(eCPSR) & T_MASK) ? 'T' : '-', + GetModeText(ARM7REG(eCPSR))); + break; - /* registers shared by all operating modes */ - case CPUINFO_STR_REGISTER + ARM7_PC: sprintf(info->s, "PC :%08x", R15 ); break; - case CPUINFO_STR_REGISTER + ARM7_R0: sprintf(info->s, "R0 :%08x", ARM7REG( 0) ); break; - case CPUINFO_STR_REGISTER + ARM7_R1: sprintf(info->s, "R1 :%08x", ARM7REG( 1) ); break; - case CPUINFO_STR_REGISTER + ARM7_R2: sprintf(info->s, "R2 :%08x", ARM7REG( 2) ); break; - case CPUINFO_STR_REGISTER + ARM7_R3: sprintf(info->s, "R3 :%08x", ARM7REG( 3) ); break; - case CPUINFO_STR_REGISTER + ARM7_R4: sprintf(info->s, "R4 :%08x", ARM7REG( 4) ); break; - case CPUINFO_STR_REGISTER + ARM7_R5: sprintf(info->s, "R5 :%08x", ARM7REG( 5) ); break; - case CPUINFO_STR_REGISTER + ARM7_R6: sprintf(info->s, "R6 :%08x", ARM7REG( 6) ); break; - case CPUINFO_STR_REGISTER + ARM7_R7: sprintf(info->s, "R7 :%08x", ARM7REG( 7) ); break; - case CPUINFO_STR_REGISTER + ARM7_R8: sprintf(info->s, "R8 :%08x", ARM7REG( 8) ); break; - case CPUINFO_STR_REGISTER + ARM7_R9: sprintf(info->s, "R9 :%08x", ARM7REG( 9) ); break; - case CPUINFO_STR_REGISTER + ARM7_R10: sprintf(info->s, "R10 :%08x", ARM7REG(10) ); break; - case CPUINFO_STR_REGISTER + ARM7_R11: sprintf(info->s, "R11 :%08x", ARM7REG(11) ); break; - case CPUINFO_STR_REGISTER + ARM7_R12: sprintf(info->s, "R12 :%08x", ARM7REG(12) ); break; - case CPUINFO_STR_REGISTER + ARM7_R13: sprintf(info->s, "R13 :%08x", ARM7REG(13) ); break; - case CPUINFO_STR_REGISTER + ARM7_R14: sprintf(info->s, "R14 :%08x", ARM7REG(14) ); break; - case CPUINFO_STR_REGISTER + ARM7_R15: sprintf(info->s, "R15 :%08x", ARM7REG(15) ); break; + /* registers shared by all operating modes */ + case CPUINFO_STR_REGISTER + ARM7_PC: sprintf(info->s, "PC :%08x", R15); break; + case CPUINFO_STR_REGISTER + ARM7_R0: sprintf(info->s, "R0 :%08x", ARM7REG( 0)); break; + case CPUINFO_STR_REGISTER + ARM7_R1: sprintf(info->s, "R1 :%08x", ARM7REG( 1)); break; + case CPUINFO_STR_REGISTER + ARM7_R2: sprintf(info->s, "R2 :%08x", ARM7REG( 2)); break; + case CPUINFO_STR_REGISTER + ARM7_R3: sprintf(info->s, "R3 :%08x", ARM7REG( 3)); break; + case CPUINFO_STR_REGISTER + ARM7_R4: sprintf(info->s, "R4 :%08x", ARM7REG( 4)); break; + case CPUINFO_STR_REGISTER + ARM7_R5: sprintf(info->s, "R5 :%08x", ARM7REG( 5)); break; + case CPUINFO_STR_REGISTER + ARM7_R6: sprintf(info->s, "R6 :%08x", ARM7REG( 6)); break; + case CPUINFO_STR_REGISTER + ARM7_R7: sprintf(info->s, "R7 :%08x", ARM7REG( 7)); break; + case CPUINFO_STR_REGISTER + ARM7_R8: sprintf(info->s, "R8 :%08x", ARM7REG( 8)); break; + case CPUINFO_STR_REGISTER + ARM7_R9: sprintf(info->s, "R9 :%08x", ARM7REG( 9)); break; + case CPUINFO_STR_REGISTER + ARM7_R10: sprintf(info->s, "R10 :%08x", ARM7REG(10)); break; + case CPUINFO_STR_REGISTER + ARM7_R11: sprintf(info->s, "R11 :%08x", ARM7REG(11)); break; + case CPUINFO_STR_REGISTER + ARM7_R12: sprintf(info->s, "R12 :%08x", ARM7REG(12)); break; + case CPUINFO_STR_REGISTER + ARM7_R13: sprintf(info->s, "R13 :%08x", ARM7REG(13)); break; + case CPUINFO_STR_REGISTER + ARM7_R14: sprintf(info->s, "R14 :%08x", ARM7REG(14)); break; + case CPUINFO_STR_REGISTER + ARM7_R15: sprintf(info->s, "R15 :%08x", ARM7REG(15)); break; - /* FIRQ Mode Shadowed Registers */ - case CPUINFO_STR_REGISTER + ARM7_FR8: sprintf(info->s, "FR8 :%08x", ARM7REG(eR8_FIQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_FR9: sprintf(info->s, "FR9 :%08x", ARM7REG(eR9_FIQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_FR10: sprintf(info->s, "FR10:%08x", ARM7REG(eR10_FIQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_FR11: sprintf(info->s, "FR11:%08x", ARM7REG(eR11_FIQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_FR12: sprintf(info->s, "FR12:%08x", ARM7REG(eR12_FIQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_FR13: sprintf(info->s, "FR13:%08x", ARM7REG(eR13_FIQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_FR14: sprintf(info->s, "FR14:%08x", ARM7REG(eR14_FIQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_FSPSR: sprintf(info->s, "FR16:%08x", ARM7REG(eSPSR_FIQ)); break; + /* FIRQ Mode Shadowed Registers */ + case CPUINFO_STR_REGISTER + ARM7_FR8: sprintf(info->s, "FR8 :%08x", ARM7REG(eR8_FIQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_FR9: sprintf(info->s, "FR9 :%08x", ARM7REG(eR9_FIQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_FR10: sprintf(info->s, "FR10:%08x", ARM7REG(eR10_FIQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_FR11: sprintf(info->s, "FR11:%08x", ARM7REG(eR11_FIQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_FR12: sprintf(info->s, "FR12:%08x", ARM7REG(eR12_FIQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_FR13: sprintf(info->s, "FR13:%08x", ARM7REG(eR13_FIQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_FR14: sprintf(info->s, "FR14:%08x", ARM7REG(eR14_FIQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_FSPSR: sprintf(info->s, "FR16:%08x", ARM7REG(eSPSR_FIQ)); break; - /* IRQ Mode Shadowed Registers */ - case CPUINFO_STR_REGISTER + ARM7_IR13: sprintf(info->s, "IR13:%08x", ARM7REG(eR13_IRQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_IR14: sprintf(info->s, "IR14:%08x", ARM7REG(eR14_IRQ) ); break; - case CPUINFO_STR_REGISTER + ARM7_ISPSR: sprintf(info->s, "IR16:%08x", ARM7REG(eSPSR_IRQ)); break; + /* IRQ Mode Shadowed Registers */ + case CPUINFO_STR_REGISTER + ARM7_IR13: sprintf(info->s, "IR13:%08x", ARM7REG(eR13_IRQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_IR14: sprintf(info->s, "IR14:%08x", ARM7REG(eR14_IRQ) ); break; + case CPUINFO_STR_REGISTER + ARM7_ISPSR: sprintf(info->s, "IR16:%08x", ARM7REG(eSPSR_IRQ)); break; - /* Supervisor Mode Shadowed Registers */ - case CPUINFO_STR_REGISTER + ARM7_SR13: sprintf(info->s, "SR13:%08x", ARM7REG(eR13_SVC) ); break; - case CPUINFO_STR_REGISTER + ARM7_SR14: sprintf(info->s, "SR14:%08x", ARM7REG(eR14_SVC) ); break; - case CPUINFO_STR_REGISTER + ARM7_SSPSR: sprintf(info->s, "SR16:%08x", ARM7REG(eSPSR_SVC)); break; + /* Supervisor Mode Shadowed Registers */ + case CPUINFO_STR_REGISTER + ARM7_SR13: sprintf(info->s, "SR13:%08x", ARM7REG(eR13_SVC) ); break; + case CPUINFO_STR_REGISTER + ARM7_SR14: sprintf(info->s, "SR14:%08x", ARM7REG(eR14_SVC) ); break; + case CPUINFO_STR_REGISTER + ARM7_SSPSR: sprintf(info->s, "SR16:%08x", ARM7REG(eSPSR_SVC)); break; - /* Abort Mode Shadowed Registers */ - case CPUINFO_STR_REGISTER + ARM7_AR13: sprintf(info->s, "AR13:%08x", ARM7REG(eR13_ABT) ); break; - case CPUINFO_STR_REGISTER + ARM7_AR14: sprintf(info->s, "AR14:%08x", ARM7REG(eR14_ABT) ); break; - case CPUINFO_STR_REGISTER + ARM7_ASPSR: sprintf(info->s, "AR16:%08x", ARM7REG(eSPSR_ABT)); break; + /* Abort Mode Shadowed Registers */ + case CPUINFO_STR_REGISTER + ARM7_AR13: sprintf(info->s, "AR13:%08x", ARM7REG(eR13_ABT) ); break; + case CPUINFO_STR_REGISTER + ARM7_AR14: sprintf(info->s, "AR14:%08x", ARM7REG(eR14_ABT) ); break; + case CPUINFO_STR_REGISTER + ARM7_ASPSR: sprintf(info->s, "AR16:%08x", ARM7REG(eSPSR_ABT)); break; - /* Undefined Mode Shadowed Registers */ - case CPUINFO_STR_REGISTER + ARM7_UR13: sprintf(info->s, "UR13:%08x", ARM7REG(eR13_UND) ); break; - case CPUINFO_STR_REGISTER + ARM7_UR14: sprintf(info->s, "UR14:%08x", ARM7REG(eR14_UND) ); break; - case CPUINFO_STR_REGISTER + ARM7_USPSR: sprintf(info->s, "UR16:%08x", ARM7REG(eSPSR_UND)); break; - } + /* Undefined Mode Shadowed Registers */ + case CPUINFO_STR_REGISTER + ARM7_UR13: sprintf(info->s, "UR13:%08x", ARM7REG(eR13_UND) ); break; + case CPUINFO_STR_REGISTER + ARM7_UR14: sprintf(info->s, "UR14:%08x", ARM7REG(eR14_UND) ); break; + case CPUINFO_STR_REGISTER + ARM7_USPSR: sprintf(info->s, "UR16:%08x", ARM7REG(eSPSR_UND)); break; + } } /* TEST COPROC CALLBACK HANDLERS - Used for example on how to implement only */ @@ -423,44 +421,43 @@ void arm7_get_info(UINT32 state, cpuinfo *info) static WRITE32_HANDLER(test_do_callback) { - LOG(("test_do_callback opcode=%x, =%x\n",offset,data)); + LOG(("test_do_callback opcode=%x, =%x\n", offset, data)); } static READ32_HANDLER(test_rt_r_callback) { - UINT32 data=0; - LOG(("test_rt_r_callback opcode=%x\n",offset)); - return data; + UINT32 data=0; + LOG(("test_rt_r_callback opcode=%x\n", offset)); + return data; } static WRITE32_HANDLER(test_rt_w_callback) { - LOG(("test_rt_w_callback opcode=%x, data from ARM7 register=%x\n",offset,data)); + LOG(("test_rt_w_callback opcode=%x, data from ARM7 register=%x\n", offset, data)); } -static void test_dt_r_callback (UINT32 insn, UINT32* prn, UINT32 (*read32)(int addr)) +static void test_dt_r_callback(UINT32 insn, UINT32 *prn, UINT32 (*read32)(UINT32 addr)) { - LOG(("test_dt_r_callback: insn = %x\n",insn)); + LOG(("test_dt_r_callback: insn = %x\n", insn)); } -static void test_dt_w_callback (UINT32 insn, UINT32* prn, void (*write32)(int addr, UINT32 data)) +static void test_dt_w_callback(UINT32 insn, UINT32 *prn, void (*write32)(UINT32 addr, UINT32 data)) { - LOG(("test_dt_w_callback: opcode = %x\n",insn)); + LOG(("test_dt_w_callback: opcode = %x\n", insn)); } /* Custom Co-proc DASM handlers */ #ifdef ENABLE_DEBUGGER -static char *Spec_RT( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0) +static char *Spec_RT(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0) { - pBuf += sprintf( pBuf, "SPECRT"); - return pBuf; + pBuf += sprintf(pBuf, "SPECRT"); + return pBuf; } -static char *Spec_DT( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0) +static char *Spec_DT(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0) { - pBuf += sprintf( pBuf, "SPECDT"); - return pBuf; + pBuf += sprintf(pBuf, "SPECDT"); + return pBuf; } -static char *Spec_DO( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0) +static char *Spec_DO(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0) { - pBuf += sprintf( pBuf, "SPECDO"); - return pBuf; + pBuf += sprintf(pBuf, "SPECDO"); + return pBuf; } #endif #endif - diff --git a/src/emu/cpu/arm7/arm7core.c b/src/emu/cpu/arm7/arm7core.c index a843f7ffa4a..81230e40cf1 100644 --- a/src/emu/cpu/arm7/arm7core.c +++ b/src/emu/cpu/arm7/arm7core.c @@ -89,103 +89,103 @@ /* Prototypes */ -//SJE: should these be inline? or are they too big to see any benefit? +// SJE: should these be inline? or are they too big to see any benefit? static void HandleCoProcDO(UINT32 insn); static void HandleCoProcRT(UINT32 insn); static void HandleCoProcDT(UINT32 insn); static void HandleHalfWordDT(UINT32 insn); static void HandleSwap(UINT32 insn); -static void HandlePSRTransfer( UINT32 insn ); -static void HandleALU( UINT32 insn); -static void HandleMul( UINT32 insn); -static void HandleUMulLong( UINT32 insn); -static void HandleSMulLong( UINT32 insn); -//static void HandleBranch( UINT32 insn); -INLINE void HandleBranch( UINT32 insn); //pretty short, so inline should be ok -static void HandleMemSingle( UINT32 insn); -static void HandleMemBlock( UINT32 insn); -static UINT32 decodeShift( UINT32 insn, UINT32 *pCarry); -INLINE void SwitchMode( int ); +static void HandlePSRTransfer(UINT32 insn); +static void HandleALU(UINT32 insn); +static void HandleMul(UINT32 insn); +static void HandleUMulLong(UINT32 insn); +static void HandleSMulLong(UINT32 insn); +INLINE void HandleBranch(UINT32 insn); // pretty short, so inline should be ok +static void HandleMemSingle(UINT32 insn); +static void HandleMemBlock(UINT32 insn); +static UINT32 decodeShift(UINT32 insn, UINT32 *pCarry); +INLINE void SwitchMode(int); static void arm7_check_irq_state(void); -INLINE void arm7_cpu_write32( int addr, UINT32 data ); -INLINE void arm7_cpu_write16( int addr, UINT16 data ); -INLINE void arm7_cpu_write8( int addr, UINT8 data ); -INLINE UINT32 arm7_cpu_read32( int addr ); -INLINE UINT16 arm7_cpu_read16( int addr ); -INLINE UINT8 arm7_cpu_read8( offs_t addr ); +INLINE void arm7_cpu_write32(UINT32 addr, UINT32 data); +INLINE void arm7_cpu_write16(UINT32 addr, UINT16 data); +INLINE void arm7_cpu_write8(UINT32 addr, UINT8 data); +INLINE UINT32 arm7_cpu_read32(UINT32 addr); +INLINE UINT16 arm7_cpu_read16(UINT32 addr); +INLINE UINT8 arm7_cpu_read8(offs_t addr); /* Static Vars */ -//Note: for multi-cpu implementation, this approach won't work w/o modification -WRITE32_HANDLER((*arm7_coproc_do_callback)); //holder for the co processor Data Operations Callback func. -READ32_HANDLER((*arm7_coproc_rt_r_callback)); //holder for the co processor Register Transfer Read Callback func. -WRITE32_HANDLER((*arm7_coproc_rt_w_callback)); //holder for the co processor Register Transfer Write Callback Callback func. -//holder for the co processor Data Transfer Read & Write Callback funcs -void (*arm7_coproc_dt_r_callback)(UINT32 insn, UINT32* prn, UINT32 (*read32)(int addr)); -void (*arm7_coproc_dt_w_callback)(UINT32 insn, UINT32* prn, void (*write32)(int addr, UINT32 data)); +// Note: for multi-cpu implementation, this approach won't work w/o modification +WRITE32_HANDLER((*arm7_coproc_do_callback)); // holder for the co processor Data Operations Callback func. +READ32_HANDLER((*arm7_coproc_rt_r_callback)); // holder for the co processor Register Transfer Read Callback func. +WRITE32_HANDLER((*arm7_coproc_rt_w_callback)); // holder for the co processor Register Transfer Write Callback Callback func. +// holder for the co processor Data Transfer Read & Write Callback funcs +void (*arm7_coproc_dt_r_callback)(UINT32 insn, UINT32 *prn, UINT32 (*read32)(UINT32 addr)); +void (*arm7_coproc_dt_w_callback)(UINT32 insn, UINT32 *prn, void (*write32)(UINT32 addr, UINT32 data)); #ifdef ENABLE_DEBUGGER -//custom dasm callback handlers for co-processor instructions -char *(*arm7_dasm_cop_dt_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 ); -char *(*arm7_dasm_cop_rt_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 ); -char *(*arm7_dasm_cop_do_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 ); +// custom dasm callback handlers for co-processor instructions +char *(*arm7_dasm_cop_dt_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); +char *(*arm7_dasm_cop_rt_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); +char *(*arm7_dasm_cop_do_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); #endif /*************************************************************************** * Default Memory Handlers ***************************************************************************/ -INLINE void arm7_cpu_write32( int addr, UINT32 data ) +INLINE void arm7_cpu_write32(UINT32 addr, UINT32 data) { - addr &= ~3; - program_write_dword_32le(addr,data); + addr &= ~3; + program_write_dword_32le(addr, data); } -INLINE void arm7_cpu_write16( int addr, UINT16 data ) +INLINE void arm7_cpu_write16(UINT32 addr, UINT16 data) { - addr &= ~1; - program_write_word_32le(addr,data); + addr &= ~1; + program_write_word_32le(addr, data); } -INLINE void arm7_cpu_write8( int addr, UINT8 data ) +INLINE void arm7_cpu_write8(UINT32 addr, UINT8 data) { - program_write_byte_32le(addr,data); + program_write_byte_32le(addr, data); } -INLINE UINT32 arm7_cpu_read32( int addr ) +INLINE UINT32 arm7_cpu_read32(offs_t addr) { UINT32 result; - if (addr&3) + if (addr & 3) { result = program_read_dword_32le(addr); - result = ( result >> ( 8 * ( addr & 3 ) ) ) | ( result << ( 32 - ( 8 * ( addr & 3 ) ) ) ); + result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3)))); } else { - result = program_read_dword_32le(addr); + result = program_read_dword_32le(addr); } + return result; } -INLINE UINT16 arm7_cpu_read16( int addr ) +INLINE UINT16 arm7_cpu_read16(offs_t addr) { - UINT16 result; + UINT16 result; - result = program_read_word_32le(addr & ~1); + result = program_read_word_32le(addr & ~1); - if (addr & 1) - { - result = ((result>>8) & 0xff) | ((result&0xff)<<8); - } + if (addr & 1) + { + result = ((result >> 8) & 0xff) | ((result & 0xff) << 8); + } - return result; + return result; } -INLINE UINT8 arm7_cpu_read8( offs_t addr ) +INLINE UINT8 arm7_cpu_read8(offs_t addr) { - //Handle through normal 8 bit handler ( for 32 bit cpu ) + // Handle through normal 8 bit handler (for 32 bit cpu) return program_read_byte_32le(addr); } @@ -193,83 +193,81 @@ INLINE UINT8 arm7_cpu_read8( offs_t addr ) * helper funcs ***************/ +// TODO LD: +// - SIGN_BITS_DIFFER = THUMB_SIGN_BITS_DIFFER +// - do while (0) +// - HandleALUAddFlags = HandleThumbALUAddFlags except for PC incr +// - HandleALUSubFlags = HandleThumbALUSubFlags except for PC incr + /* Set NZCV flags for ADDS / SUBS */ -#define HandleALUAddFlags(rd, rn, op2) \ - if (insn & INSN_S) \ - SET_CPSR( \ - ((GET_CPSR &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ - | (((!SIGN_BITS_DIFFER(rn, op2)) && SIGN_BITS_DIFFER(rn, rd)) \ - << V_BIT) \ - | (((~(rn)) < (op2)) << C_BIT) \ - | HandleALUNZFlags(rd))); \ +#define HandleALUAddFlags(rd, rn, op2) \ + if (insn & INSN_S) \ + SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ + | (((!SIGN_BITS_DIFFER(rn, op2)) && SIGN_BITS_DIFFER(rn, rd)) << V_BIT) \ + | (((~(rn)) < (op2)) << C_BIT) \ + | HandleALUNZFlags(rd))); \ R15 += 4; -#define HandleThumbALUAddFlags(rd, rn, op2) \ - SET_CPSR( \ - ((GET_CPSR &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ - | (((!THUMB_SIGN_BITS_DIFFER(rn, op2)) && THUMB_SIGN_BITS_DIFFER(rn, rd)) \ - << V_BIT) \ - | (((~(rn)) < (op2)) << C_BIT) \ - | HandleALUNZFlags(rd))); \ - R15 += 2; +#define HandleThumbALUAddFlags(rd, rn, op2) \ + SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ + | (((!THUMB_SIGN_BITS_DIFFER(rn, op2)) && THUMB_SIGN_BITS_DIFFER(rn, rd)) << V_BIT) \ + | (((~(rn)) < (op2)) << C_BIT) \ + | HandleALUNZFlags(rd))); \ + R15 += 2; #define IsNeg(i) ((i) >> 31) #define IsPos(i) ((~(i)) >> 31) -#define HandleALUSubFlags(rd, rn, op2) \ - if (insn & INSN_S) \ - SET_CPSR( \ - ((GET_CPSR &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ - | ((SIGN_BITS_DIFFER(rn, op2) && SIGN_BITS_DIFFER(rn, rd)) \ - << V_BIT) \ - | (((IsNeg(rn) & IsPos(op2)) | (IsNeg(rn) & IsPos(rd)) | (IsPos(op2) & IsPos(rd))) ? C_MASK : 0) \ - | HandleALUNZFlags(rd))); \ +#define HandleALUSubFlags(rd, rn, op2) \ + if (insn & INSN_S) \ + SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ + | ((SIGN_BITS_DIFFER(rn, op2) && SIGN_BITS_DIFFER(rn, rd)) << V_BIT) \ + | (((IsNeg(rn) & IsPos(op2)) | (IsNeg(rn) & IsPos(rd)) | (IsPos(op2) & IsPos(rd))) ? C_MASK : 0) \ + | HandleALUNZFlags(rd))); \ R15 += 4; -#define HandleThumbALUSubFlags(rd, rn, op2) \ - SET_CPSR( \ - ((GET_CPSR &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ - | ((THUMB_SIGN_BITS_DIFFER(rn, op2) && THUMB_SIGN_BITS_DIFFER(rn, rd)) \ - << V_BIT) \ - | (((IsNeg(rn) & IsPos(op2)) | (IsNeg(rn) & IsPos(rd)) | (IsPos(op2) & IsPos(rd))) ? C_MASK : 0) \ - | HandleALUNZFlags(rd))); \ - R15 += 2; +#define HandleThumbALUSubFlags(rd, rn, op2) \ + SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ + | ((THUMB_SIGN_BITS_DIFFER(rn, op2) && THUMB_SIGN_BITS_DIFFER(rn, rd)) << V_BIT) \ + | (((IsNeg(rn) & IsPos(op2)) | (IsNeg(rn) & IsPos(rd)) | (IsPos(op2) & IsPos(rd))) ? C_MASK : 0) \ + | HandleALUNZFlags(rd))); \ + R15 += 2; /* Set NZC flags for logical operations. */ -//This macro (which I didn't write) - doesn't make it obvious that the SIGN BIT = 31, just as the N Bit does, -//therfore, N is set by default -#define HandleALUNZFlags(rd) \ +// This macro (which I didn't write) - doesn't make it obvious that the SIGN BIT = 31, just as the N Bit does, +// therefore, N is set by default +#define HandleALUNZFlags(rd) \ (((rd) & SIGN_BIT) | ((!(rd)) << Z_BIT)) -//Long ALU Functions use bit 63 -#define HandleLongALUNZFlags(rd) \ - ((((rd) & ((UINT64)1<<63))>>32) | ((!(rd)) << Z_BIT)) +// Long ALU Functions use bit 63 +#define HandleLongALUNZFlags(rd) \ + ((((rd) & ((UINT64)1 << 63)) >> 32) | ((!(rd)) << Z_BIT)) -#define HandleALULogicalFlags(rd, sc) \ - if (insn & INSN_S) \ - SET_CPSR( ((GET_CPSR &~ (N_MASK | Z_MASK | C_MASK)) \ - | HandleALUNZFlags(rd) \ - | (((sc) != 0) << C_BIT)));\ +#define HandleALULogicalFlags(rd, sc) \ + if (insn & INSN_S) \ + SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | C_MASK)) \ + | HandleALUNZFlags(rd) \ + | (((sc) != 0) << C_BIT))); \ R15 += 4; -//convert cpsr mode num into to text +// convert cpsr mode num into to text static const char modetext[ARM7_NUM_MODES][5] = { - "USER","FIRQ","IRQ","SVC","ILL1","ILL2","ILL3","ABT", - "ILL4","ILL5","ILL6","UND","ILL7","ILL8","ILL9","SYS" + "USER", "FIRQ", "IRQ", "SVC", "ILL1", "ILL2", "ILL3", "ABT", + "ILL4", "ILL5", "ILL6", "UND", "ILL7", "ILL8", "ILL9", "SYS" }; -static const char* GetModeText( int cpsr ) +static const char *GetModeText(int cpsr) { return modetext[cpsr & MODE_FLAG]; } -//used to be functions, but no longer a need, so we'll use define for better speed. -#define GetRegister(rIndex) ARM7REG(sRegisterTable[GET_MODE][rIndex]) -#define SetRegister(rIndex,value) ARM7REG(sRegisterTable[GET_MODE][rIndex]) = value +// used to be functions, but no longer a need, so we'll use define for better speed. +#define GetRegister(rIndex) ARM7REG(sRegisterTable[GET_MODE][rIndex]) +#define SetRegister(rIndex, value) ARM7REG(sRegisterTable[GET_MODE][rIndex]) = value -//I could prob. convert to macro, but Switchmode shouldn't occur that often in emulated code.. -INLINE void SwitchMode (int cpsr_mode_val) +// I could prob. convert to macro, but Switchmode shouldn't occur that often in emulated code.. +INLINE void SwitchMode(int cpsr_mode_val) { UINT32 cspr = GET_CPSR & ~MODE_FLAG; SET_CPSR(cspr | cpsr_mode_val); @@ -294,37 +292,38 @@ INLINE void SwitchMode (int cpsr_mode_val) ROR >32 = Same result as ROR n-32 until amount in range of 1-32 then follow rules */ -static UINT32 decodeShift( UINT32 insn, UINT32 *pCarry) +static UINT32 decodeShift(UINT32 insn, UINT32 *pCarry) { - UINT32 k = (insn & INSN_OP2_SHIFT) >> INSN_OP2_SHIFT_SHIFT; //Bits 11-7 - UINT32 rm = GET_REGISTER( insn & INSN_OP2_RM ); + UINT32 k = (insn & INSN_OP2_SHIFT) >> INSN_OP2_SHIFT_SHIFT; // Bits 11-7 + UINT32 rm = GET_REGISTER(insn & INSN_OP2_RM); UINT32 t = (insn & INSN_OP2_SHIFT_TYPE) >> INSN_OP2_SHIFT_TYPE_SHIFT; - if ((insn & INSN_OP2_RM)==0xf) { - rm+=8; + if ((insn & INSN_OP2_RM) == 0xf) { + rm += 8; } /* All shift types ending in 1 are Rk, not #k */ - if( t & 1 ) + if (t & 1) { -// LOG(("%08x: RegShift %02x %02x\n",R15, k>>1,GET_REGISTER(k >> 1))); - #if ARM7_DEBUG_CORE - if((insn&0x80)==0x80) - LOG(("%08x: RegShift ERROR (p36)\n",R15)); - #endif +// LOG(("%08x: RegShift %02x %02x\n", R15, k >> 1, GET_REGISTER(k >> 1))); +#if ARM7_DEBUG_CORE + if ((insn & 0x80) == 0x80) + LOG(("%08x: RegShift ERROR (p36)\n", R15)); +#endif - //see p35 for check on this - //k = GET_REGISTER(k >> 1)&0x1f; + // see p35 for check on this + //k = GET_REGISTER(k >> 1) & 0x1f; - //Keep only the bottom 8 bits for a Register Shift - k = GET_REGISTER(k >> 1)&0xff; + // Keep only the bottom 8 bits for a Register Shift + k = GET_REGISTER(k >> 1) & 0xff; - if( k == 0 ) /* Register shift by 0 is a no-op */ + if (k == 0) /* Register shift by 0 is a no-op */ { -// LOG(("%08x: NO-OP Regshift\n",R15)); - /* TODO this is wrong for at least ROR by reg with with lower +// LOG(("%08x: NO-OP Regshift\n", R15)); + /* TODO this is wrong for at least ROR by reg with lower * 5 bits 0 but lower 8 bits non zero */ - if (pCarry) *pCarry = GET_CPSR & C_MASK; + if (pCarry) + *pCarry = GET_CPSR & C_MASK; return rm; } } @@ -332,19 +331,20 @@ static UINT32 decodeShift( UINT32 insn, UINT32 *pCarry) switch (t >> 1) { case 0: /* LSL */ - //LSL 32 = Result of 0, Carry = Bit 0 of RM - //LSL >32 = Result of 0, Carry out 0 - if(k>=32) + // LSL 32 = Result of 0, Carry = Bit 0 of RM + // LSL >32 = Result of 0, Carry out 0 + if (k >= 32) { - if(pCarry) *pCarry = (k==32)?rm&1:0; + if (pCarry) + *pCarry = (k == 32) ? rm & 1 : 0; return 0; } else { if (pCarry) { - //LSL 0 = Result = RM, Carry = Old Contents of CPSR C Bit - //LSL (0,31) = Result shifted, least significant bit is in carry out + // LSL 0 = Result = RM, Carry = Old Contents of CPSR C Bit + // LSL (0,31) = Result shifted, least significant bit is in carry out *pCarry = k ? (rm & (1 << (32 - k))) : (GET_CPSR & C_MASK); } return k ? LSL(rm, k) : rm; @@ -354,17 +354,20 @@ static UINT32 decodeShift( UINT32 insn, UINT32 *pCarry) case 1: /* LSR */ if (k == 0 || k == 32) { - if (pCarry) *pCarry = rm & SIGN_BIT; + if (pCarry) + *pCarry = rm & SIGN_BIT; return 0; } else if (k > 32) { - if (pCarry) *pCarry = 0; + if (pCarry) + *pCarry = 0; return 0; } else { - if (pCarry) *pCarry = (rm & (1 << (k - 1))); + if (pCarry) + *pCarry = (rm & (1 << (k - 1))); return LSR(rm, k); } break; @@ -373,7 +376,8 @@ static UINT32 decodeShift( UINT32 insn, UINT32 *pCarry) if (k == 0 || k > 32) k = 32; - if (pCarry) *pCarry = (rm & (1 << (k - 1))); + if (pCarry) + *pCarry = (rm & (1 << (k - 1))); if (k >= 32) return rm & SIGN_BIT ? 0xffffffffu : 0; else @@ -388,41 +392,44 @@ static UINT32 decodeShift( UINT32 insn, UINT32 *pCarry) case 3: /* ROR and RRX */ if (k) { - while (k > 32) k -= 32; - if (pCarry) *pCarry = rm & (1 << (k - 1)); + while (k > 32) + k -= 32; + if (pCarry) + *pCarry = rm & (1 << (k - 1)); return ROR(rm, k); } else { /* RRX */ - if (pCarry) *pCarry = (rm & 1); + if (pCarry) + *pCarry = (rm & 1); return LSR(rm, 1) | ((GET_CPSR & C_MASK) << 2); } break; } - LOG(("%08x: Decodeshift error\n",R15)); + LOG(("%08x: Decodeshift error\n", R15)); return 0; } /* decodeShift */ -static int loadInc ( UINT32 pat, UINT32 rbv, UINT32 s) +static int loadInc(UINT32 pat, UINT32 rbv, UINT32 s) { - int i,result; + int i, result; result = 0; rbv &= ~3; - for( i=0; i<16; i++ ) + for (i = 0; i < 16; i++) { - if( (pat>>i)&1 ) + if ((pat >> i) & 1) { - if (i==15) { + if (i == 15) { if (s) /* Pull full contents from stack */ - SET_REGISTER( 15, READ32(rbv+=4) ); + SET_REGISTER(15, READ32(rbv += 4)); else /* Pull only address, preserve mode & status flags */ - SET_REGISTER( 15, READ32(rbv+=4) ); + SET_REGISTER(15, READ32(rbv += 4)); } else - SET_REGISTER( i, READ32(rbv+=4) ); + SET_REGISTER(i, READ32(rbv += 4)); result++; } @@ -430,64 +437,64 @@ static int loadInc ( UINT32 pat, UINT32 rbv, UINT32 s) return result; } -static int loadDec( UINT32 pat, UINT32 rbv, UINT32 s) +static int loadDec(UINT32 pat, UINT32 rbv, UINT32 s) { - int i,result; + int i, result; result = 0; rbv &= ~3; - for( i=15; i>=0; i-- ) + for (i = 15; i >= 0; i--) { - if( (pat>>i)&1 ) + if ((pat >> i) & 1) { - if (i==15) { + if (i == 15) { if (s) /* Pull full contents from stack */ - SET_REGISTER( 15, READ32(rbv-=4) ); + SET_REGISTER(15, READ32(rbv -= 4)); else /* Pull only address, preserve mode & status flags */ - SET_REGISTER( 15, READ32(rbv-=4) ); + SET_REGISTER(15, READ32(rbv -= 4)); } else - SET_REGISTER( i, READ32(rbv -=4) ); + SET_REGISTER(i, READ32(rbv -= 4)); result++; } } return result; } -static int storeInc( UINT32 pat, UINT32 rbv) +static int storeInc(UINT32 pat, UINT32 rbv) { - int i,result; + int i, result; result = 0; - for( i=0; i<16; i++ ) + for (i = 0; i < 16; i++) { - if( (pat>>i)&1 ) + if ((pat >> i) & 1) { - #if ARM7_DEBUG_CORE - if(i==15) /* R15 is plus 12 from address of STM */ - LOG(("%08x: StoreInc on R15\n",R15)); - #endif - WRITE32( rbv += 4, GET_REGISTER(i) ); +#if ARM7_DEBUG_CORE + if (i == 15) /* R15 is plus 12 from address of STM */ + LOG(("%08x: StoreInc on R15\n", R15)); +#endif + WRITE32(rbv += 4, GET_REGISTER(i)); result++; } } return result; } /* storeInc */ -static int storeDec( UINT32 pat, UINT32 rbv) +static int storeDec(UINT32 pat, UINT32 rbv) { - int i,result; + int i, result; result = 0; - for( i=15; i>=0; i-- ) + for (i = 15; i >= 0; i--) { - if( (pat>>i)&1 ) + if ((pat >> i) & 1) { - #if ARM7_DEBUG_CORE - if(i==15) /* R15 is plus 12 from address of STM */ - LOG(("%08x: StoreDec on R15\n",R15)); - #endif - WRITE32( rbv -= 4, GET_REGISTER(i) ); +#if ARM7_DEBUG_CORE + if (i == 15) /* R15 is plus 12 from address of STM */ + LOG(("%08x: StoreDec on R15\n", R15)); +#endif + WRITE32(rbv -= 4, GET_REGISTER(i)); result++; } } @@ -498,7 +505,7 @@ static int storeDec( UINT32 pat, UINT32 rbv) * Main CPU Funcs ***************************************************************************/ -//CPU INIT +// CPU INIT static void arm7_core_init(const char *cpuname, int index) { state_save_register_item_array(cpuname, index, ARM7.sArmRegister); @@ -510,10 +517,11 @@ static void arm7_core_init(const char *cpuname, int index) state_save_register_item(cpuname, index, ARM7.pendingSwi); } -//CPU RESET +// CPU RESET static void arm7_core_reset(void) { - int (*save_irqcallback)(int) = ARM7.irq_callback; + int (*save_irqcallback)(int) = ARM7.irq_callback; + memset(&ARM7, 0, sizeof(ARM7)); ARM7.irq_callback = save_irqcallback; @@ -521,17 +529,17 @@ static void arm7_core_reset(void) SwitchMode(eARM7_MODE_SVC); SET_CPSR(GET_CPSR | I_MASK | F_MASK | 0x10); R15 = 0; - change_pc(R15); + change_pc(R15); } -//Execute used to be here.. moved to separate file (arm7exec.c) to be included by cpu cores separately +// Execute used to be here.. moved to separate file (arm7exec.c) to be included by cpu cores separately -//CPU CHECK IRQ STATE -//Note: couldn't find any exact cycle counts for most of these exceptions +// CPU CHECK IRQ STATE +// Note: couldn't find any exact cycle counts for most of these exceptions static void arm7_check_irq_state(void) { UINT32 cpsr = GET_CPSR; /* save current CPSR */ - UINT32 pc = R15+4; /* save old pc (already incremented in pipeline) */; + UINT32 pc = R15 + 4; /* save old pc (already incremented in pipeline) */; /* Exception priorities: @@ -544,113 +552,113 @@ static void arm7_check_irq_state(void) Software Interrupt */ - //Data Abort + // Data Abort if (ARM7.pendingAbtD) { SwitchMode(eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */ - SET_REGISTER( 14, pc ); /* save PC to R14 */ - SET_REGISTER( SPSR, cpsr ); /* Save current CPSR */ + SET_REGISTER(14, pc); /* save PC to R14 */ + SET_REGISTER(SPSR, cpsr); /* Save current CPSR */ SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ SET_CPSR(GET_CPSR & ~T_MASK); R15 = 0x10; /* IRQ Vector address */ - change_pc(R15); + change_pc(R15); ARM7.pendingAbtD = 0; return; } - //FIQ - if (ARM7.pendingFiq && (cpsr & F_MASK)==0) { + // FIQ + if (ARM7.pendingFiq && (cpsr & F_MASK) == 0) { SwitchMode(eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */ - SET_REGISTER( 14, pc ); /* save PC to R14 */ - SET_REGISTER( SPSR, cpsr ); /* Save current CPSR */ + SET_REGISTER(14, pc); /* save PC to R14 */ + SET_REGISTER(SPSR, cpsr); /* Save current CPSR */ SET_CPSR(GET_CPSR | I_MASK | F_MASK); /* Mask both IRQ & FIQ */ SET_CPSR(GET_CPSR & ~T_MASK); R15 = 0x1c; /* IRQ Vector address */ - change_pc(R15); + change_pc(R15); return; } - //IRQ - if (ARM7.pendingIrq && (cpsr & I_MASK)==0) { + // IRQ + if (ARM7.pendingIrq && (cpsr & I_MASK) == 0) { SwitchMode(eARM7_MODE_IRQ); /* Set IRQ mode so PC is saved to correct R14 bank */ - SET_REGISTER( 14, pc ); /* save PC to R14 */ - SET_REGISTER( SPSR, cpsr ); /* Save current CPSR */ + SET_REGISTER(14, pc); /* save PC to R14 */ + SET_REGISTER(SPSR, cpsr); /* Save current CPSR */ SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ SET_CPSR(GET_CPSR & ~T_MASK); R15 = 0x18; /* IRQ Vector address */ - change_pc(R15); + change_pc(R15); return; } - //Prefetch Abort + // Prefetch Abort if (ARM7.pendingAbtP) { SwitchMode(eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */ - SET_REGISTER( 14, pc ); /* save PC to R14 */ - SET_REGISTER( SPSR, cpsr ); /* Save current CPSR */ + SET_REGISTER(14, pc); /* save PC to R14 */ + SET_REGISTER(SPSR, cpsr); /* Save current CPSR */ SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ SET_CPSR(GET_CPSR & ~T_MASK); R15 = 0x0c; /* IRQ Vector address */ - change_pc(R15); + change_pc(R15); ARM7.pendingAbtP = 0; return; } - //Undefined instruction + // Undefined instruction if (ARM7.pendingUnd) { SwitchMode(eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */ - SET_REGISTER( 14, pc ); /* save PC to R14 */ - SET_REGISTER( SPSR, cpsr ); /* Save current CPSR */ + SET_REGISTER(14, pc); /* save PC to R14 */ + SET_REGISTER(SPSR, cpsr); /* Save current CPSR */ SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ SET_CPSR(GET_CPSR & ~T_MASK); R15 = 0x04; /* IRQ Vector address */ - change_pc(R15); + change_pc(R15); ARM7.pendingUnd = 0; return; } - //Software Interrupt + // Software Interrupt if (ARM7.pendingSwi) { SwitchMode(eARM7_MODE_SVC); /* Set SVC mode so PC is saved to correct R14 bank */ - // compensate for prefetch (should this also be done for normal IRQ?) - if (T_IS_SET(GET_CPSR)) - { - SET_REGISTER( 14, pc-2 ); /* save PC to R14 */ - } - else - { - SET_REGISTER( 14, pc ); /* save PC to R14 */ - } - SET_REGISTER( SPSR, cpsr ); /* Save current CPSR */ + // compensate for prefetch (should this also be done for normal IRQ?) + if (T_IS_SET(GET_CPSR)) + { + SET_REGISTER(14, pc-2); /* save PC to R14 */ + } + else + { + SET_REGISTER(14, pc); /* save PC to R14 */ + } + SET_REGISTER(SPSR, cpsr); /* Save current CPSR */ SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ - SET_CPSR(GET_CPSR & ~T_MASK); /* Go to ARM mode */ - R15 = 0x08; /* Jump to the SWI vector */ - change_pc(R15); + SET_CPSR(GET_CPSR & ~T_MASK); /* Go to ARM mode */ + R15 = 0x08; /* Jump to the SWI vector */ + change_pc(R15); ARM7.pendingSwi = 0; return; } } -//CPU - SET IRQ LINE +// CPU - SET IRQ LINE static void arm7_core_set_irq_line(int irqline, int state) { switch (irqline) { case ARM7_IRQ_LINE: /* IRQ */ - ARM7.pendingIrq= (state & 1); + ARM7.pendingIrq = state & 1; break; case ARM7_FIRQ_LINE: /* FIRQ */ - ARM7.pendingFiq= (state & 1); + ARM7.pendingFiq = state & 1; break; case ARM7_ABORT_EXCEPTION: - ARM7.pendingAbtD= (state & 1); + ARM7.pendingAbtD = state & 1; break; case ARM7_ABORT_PREFETCH_EXCEPTION: - ARM7.pendingAbtP= (state & 1); + ARM7.pendingAbtP = state & 1; break; case ARM7_UNDEFINE_EXCEPTION: - ARM7.pendingUnd= (state & 1); + ARM7.pendingUnd = state & 1; break; } @@ -665,40 +673,40 @@ static void arm7_core_set_irq_line(int irqline, int state) static void HandleCoProcDO(UINT32 insn) { // This instruction simply instructs the co-processor to do something, no data is returned to ARM7 core - if(arm7_coproc_do_callback) - arm7_coproc_do_callback(insn,0,0); //simply pass entire opcode to callback - since data format is actually dependent on co-proc implementation + if (arm7_coproc_do_callback) + arm7_coproc_do_callback(insn, 0, 0); // simply pass entire opcode to callback - since data format is actually dependent on co-proc implementation else - LOG(("%08x: Co-Processor Data Operation executed, but no callback defined!\n",R15)); + LOG(("%08x: Co-Processor Data Operation executed, but no callback defined!\n", R15)); } -//Co-Processor Register Transfer - To/From Arm to Co-Proc +// Co-Processor Register Transfer - To/From Arm to Co-Proc static void HandleCoProcRT(UINT32 insn) { /* xxxx 1110 oooL nnnn dddd cccc ppp1 mmmm */ // Load (MRC) data from Co-Proc to ARM7 register - if( insn&0x00100000 ) //Bit 20 = Load or Store + if (insn & 0x00100000) // Bit 20 = Load or Store + { + if (arm7_coproc_rt_r_callback) { - if(arm7_coproc_rt_r_callback) - { - UINT32 res = arm7_coproc_rt_r_callback(insn,0); //RT Read handler must parse opcode & return appropriate result - SET_REGISTER((insn>>12)&0xf,res); - } - else - LOG(("%08x: Co-Processor Register Transfer executed, but no RT Read callback defined!\n",R15)); + UINT32 res = arm7_coproc_rt_r_callback(insn, 0); // RT Read handler must parse opcode & return appropriate result + SET_REGISTER((insn >> 12) & 0xf, res); } + else + LOG(("%08x: Co-Processor Register Transfer executed, but no RT Read callback defined!\n", R15)); + } // Store (MCR) data from ARM7 to Co-Proc register else - { - if(arm7_coproc_rt_r_callback) - arm7_coproc_rt_w_callback(insn,GET_REGISTER((insn>>12)&0xf),0); + { + if (arm7_coproc_rt_r_callback) + arm7_coproc_rt_w_callback(insn, GET_REGISTER((insn >> 12) & 0xf), 0); else - LOG(("%08x: Co-Processor Register Transfer executed, but no RT Write callback defined!\n",R15)); - } + LOG(("%08x: Co-Processor Register Transfer executed, but no RT Write callback defined!\n", R15)); + } } -/*Data Transfer - To/From Arm to Co-Proc +/* Data Transfer - To/From Arm to Co-Proc Loading or Storing, the co-proc function is responsible to read/write from the base register supplied + offset 8 bit immediate value Base Offset address is << 2 to get the actual # @@ -709,66 +717,66 @@ static void HandleCoProcRT(UINT32 insn) address supplied in that case, is simply the base. I suppose this is irrelevant if write back not set but if co-proc reads multiple address, it must handle the offset adjustment itself. */ -//todo: test with valid instructions +// todo: test with valid instructions static void HandleCoProcDT(UINT32 insn) { - UINT32 rn = (insn>>16)&0xf; + UINT32 rn = (insn >> 16) & 0xf; UINT32 rnv = GET_REGISTER(rn); // Get Address Value stored from Rn UINT32 ornv = rnv; // Keep value of Rn - UINT32 off = (insn&0xff)<<2; // Offset is << 2 according to manual - UINT32* prn = &ARM7REG(rn); // Pointer to our register, so it can be changed in the callback + UINT32 off = (insn & 0xff) << 2; // Offset is << 2 according to manual + UINT32 *prn = &ARM7REG(rn); // Pointer to our register, so it can be changed in the callback - //Pointers to read32/write32 functions - void (*write32)(int addr, UINT32 data); - UINT32 (*read32)(int addr); + // Pointers to read32/write32 functions + void (*write32)(UINT32 addr, UINT32 data); + UINT32 (*read32)(UINT32 addr); write32 = PTR_WRITE32; read32 = PTR_READ32; - #if ARM7_DEBUG_CORE - if(((insn>>16)&0xf)==15 && (insn & 0x200000)) - LOG(("%08x: Illegal use of R15 as base for write back value!\n",R15)); - #endif +#if ARM7_DEBUG_CORE + if (((insn >> 16) & 0xf) == 15 && (insn & 0x200000)) + LOG(("%08x: Illegal use of R15 as base for write back value!\n", R15)); +#endif - //Pre-Increment base address (IF POST INCREMENT - CALL BACK FUNCTION MUST DO IT) - if(insn&0x1000000 && off) + // Pre-Increment base address (IF POST INCREMENT - CALL BACK FUNCTION MUST DO IT) + if ((insn & 0x1000000) && off) { - //Up - Down bit - if(insn&0x800000) - rnv+=off; + // Up - Down bit + if (insn & 0x800000) + rnv += off; else - rnv-=off; + rnv -= off; } // Load (LDC) data from ARM7 memory to Co-Proc memory - if( insn&0x00100000 ) - { - if(arm7_coproc_dt_r_callback) - arm7_coproc_dt_r_callback(insn,prn,read32); - else - LOG(("%08x: Co-Processer Data Transfer executed, but no READ callback defined!\n",R15)); - } + if (insn & 0x00100000) + { + if (arm7_coproc_dt_r_callback) + arm7_coproc_dt_r_callback(insn, prn, read32); + else + LOG(("%08x: Co-Processer Data Transfer executed, but no READ callback defined!\n", R15)); + } // Store (STC) data from Co-Proc to ARM7 memory else - { - if(arm7_coproc_dt_w_callback) - arm7_coproc_dt_w_callback(insn,prn,write32); - else - LOG(("%08x: Co-Processer Data Transfer executed, but no WRITE callback defined!\n",R15)); - } + { + if (arm7_coproc_dt_w_callback) + arm7_coproc_dt_w_callback(insn, prn, write32); + else + LOG(("%08x: Co-Processer Data Transfer executed, but no WRITE callback defined!\n", R15)); + } - //If writeback not used - ensure the original value of RN is restored in case co-proc callback changed value - if((insn & 0x200000)==0) - SET_REGISTER(rn,ornv); + // If writeback not used - ensure the original value of RN is restored in case co-proc callback changed value + if ((insn & 0x200000) == 0) + SET_REGISTER(rn, ornv); } -static void HandleBranch( UINT32 insn ) +static void HandleBranch(UINT32 insn) { UINT32 off = (insn & INSN_BRANCH) << 2; /* Save PC into LR if this is a branch with link */ if (insn & INSN_BL) { - SET_REGISTER(14,R15 + 4); + SET_REGISTER(14, R15 + 4); } /* Sign-extend the 24-bit offset in our calculations */ @@ -781,10 +789,10 @@ static void HandleBranch( UINT32 insn ) R15 += off + 8; } - change_pc(R15); + change_pc(R15); } -static void HandleMemSingle( UINT32 insn ) +static void HandleMemSingle(UINT32 insn) { UINT32 rn, rnv, off, rd; @@ -817,9 +825,9 @@ static void HandleMemSingle( UINT32 insn ) if (insn & INSN_SDT_W) { - SET_REGISTER(rn,rnv); + SET_REGISTER(rn, rnv); - //check writeback??? + // check writeback??? } else if (rn == eR15) { @@ -846,7 +854,7 @@ static void HandleMemSingle( UINT32 insn ) /* Load */ if (insn & INSN_SDT_B) { - SET_REGISTER(rd,(UINT32) READ8(rnv)); + SET_REGISTER(rd, (UINT32)READ8(rnv)); } else { @@ -854,13 +862,13 @@ static void HandleMemSingle( UINT32 insn ) { R15 = READ32(rnv); R15 -= 4; - change_pc(R15); - //LDR, PC takes 2S + 2N + 1I (5 total cycles) + change_pc(R15); + // LDR, PC takes 2S + 2N + 1I (5 total cycles) ARM7_ICOUNT -= 2; } else { - SET_REGISTER(rd,READ32(rnv)); + SET_REGISTER(rd, READ32(rnv)); } } } @@ -869,58 +877,58 @@ static void HandleMemSingle( UINT32 insn ) /* Store */ if (insn & INSN_SDT_B) { - #if ARM7_DEBUG_CORE - if(rd==eR15) +#if ARM7_DEBUG_CORE + if (rd == eR15) LOG(("Wrote R15 in byte mode\n")); - #endif +#endif WRITE8(rnv, (UINT8) GET_REGISTER(rd) & 0xffu); } else { - #if ARM7_DEBUG_CORE - if(rd==eR15) +#if ARM7_DEBUG_CORE + if (rd == eR15) LOG(("Wrote R15 in 32bit mode\n")); - #endif +#endif //WRITE32(rnv, rd == eR15 ? R15 + 8 : GET_REGISTER(rd)); - WRITE32(rnv, rd == eR15 ? R15 + 8 + 4 : GET_REGISTER(rd)); //manual says STR rd = PC, +12 + WRITE32(rnv, rd == eR15 ? R15 + 8 + 4 : GET_REGISTER(rd)); // manual says STR rd = PC, +12 } - //Store takes only 2 N Cycles, so add + 1 + // Store takes only 2 N Cycles, so add + 1 ARM7_ICOUNT += 1; } /* Do post-indexing writeback */ - if (!(insn & INSN_SDT_P)/* && (insn&INSN_SDT_W)*/) + if (!(insn & INSN_SDT_P)/* && (insn & INSN_SDT_W)*/) { if (insn & INSN_SDT_U) { /* Writeback is applied in pipeline, before value is read from mem, so writeback is effectively ignored */ - if (rd==rn) { - SET_REGISTER(rn,GET_REGISTER(rd)); - //todo: check for offs... ? + if (rd == rn) { + SET_REGISTER(rn, GET_REGISTER(rd)); + // todo: check for offs... ? } else { - if ((insn&INSN_SDT_W)!=0) - LOG(("%08x: RegisterWritebackIncrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0)); + if ((insn & INSN_SDT_W) != 0) + LOG(("%08x: RegisterWritebackIncrement %d %d %d\n", R15, (insn & INSN_SDT_P) != 0, (insn & INSN_SDT_W) != 0, (insn & INSN_SDT_U) != 0)); - SET_REGISTER(rn,(rnv + off)); + SET_REGISTER(rn, (rnv + off)); } } else { /* Writeback is applied in pipeline, before value is read from mem, so writeback is effectively ignored */ - if (rd==rn) { - SET_REGISTER(rn,GET_REGISTER(rd)); + if (rd == rn) { + SET_REGISTER(rn, GET_REGISTER(rd)); } else { - SET_REGISTER(rn,(rnv - off)); + SET_REGISTER(rn, (rnv - off)); - if ((insn&INSN_SDT_W)!=0) - LOG(("%08x: RegisterWritebackDecrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0)); + if ((insn & INSN_SDT_W) != 0) + LOG(("%08x: RegisterWritebackDecrement %d %d %d\n", R15, (insn & INSN_SDT_P) != 0, (insn & INSN_SDT_W) != 0, (insn & INSN_SDT_U) != 0)); } } } @@ -933,13 +941,13 @@ static void HandleHalfWordDT(UINT32 insn) { UINT32 rn, rnv, off, rd; - //Immediate or Register Offset? - if(insn & 0x400000) { //Bit 22 - 1 = immediate, 0 = register - //imm. value in high nibble (bits 8-11) and lo nibble (bit 0-3) - off = (((insn>>8)&0x0f)<<4) | (insn&0x0f); + // Immediate or Register Offset? + if (insn & 0x400000) { // Bit 22 - 1 = immediate, 0 = register + // imm. value in high nibble (bits 8-11) and lo nibble (bit 0-3) + off = (((insn >> 8) & 0x0f) << 4) | (insn & 0x0f); } else { - //register + // register off = GET_REGISTER(insn & 0x0f); } @@ -960,9 +968,9 @@ static void HandleHalfWordDT(UINT32 insn) if (insn & INSN_SDT_W) { - SET_REGISTER(rn,rnv); + SET_REGISTER(rn, rnv); - //check writeback??? + // check writeback??? } else if (rn == eR15) { @@ -988,42 +996,42 @@ static void HandleHalfWordDT(UINT32 insn) /* Load */ if (insn & INSN_SDT_L) { - //Signed? - if(insn & 0x40) + // Signed? + if (insn & 0x40) { UINT32 newval = 0; - //Signed Half Word? - if(insn & 0x20) { - UINT16 signbyte,databyte; + // Signed Half Word? + if (insn & 0x20) { + UINT16 signbyte, databyte; databyte = READ16(rnv) & 0xFFFF; signbyte = (databyte & 0x8000) ? 0xffff : 0; - newval = (UINT32)(signbyte<<16)|databyte; + newval = (UINT32)(signbyte << 16)|databyte; } - //Signed Byte + // Signed Byte else { UINT8 databyte; UINT32 signbyte; databyte = READ8(rnv) & 0xff; signbyte = (databyte & 0x80) ? 0xffffff : 0; - newval = (UINT32)(signbyte<<8)|databyte; + newval = (UINT32)(signbyte << 8)|databyte; } - //PC? - if(rd == eR15) + // PC? + if (rd == eR15) { R15 = newval + 8; - //LDR(H,SH,SB) PC takes 2S + 2N + 1I (5 total cycles) + // LDR(H,SH,SB) PC takes 2S + 2N + 1I (5 total cycles) ARM7_ICOUNT -= 2; } else { - SET_REGISTER(rd,newval); + SET_REGISTER(rd, newval); R15 += 4; } } - //Unsigned Half Word + // Unsigned Half Word else { if (rd == eR15) @@ -1032,7 +1040,7 @@ static void HandleHalfWordDT(UINT32 insn) } else { - SET_REGISTER(rd,READ16(rnv)); + SET_REGISTER(rd, READ16(rnv)); R15 += 4; } } @@ -1042,185 +1050,185 @@ static void HandleHalfWordDT(UINT32 insn) /* Store */ else { - //WRITE16(rnv, rd == eR15 ? R15 + 8 : GET_REGISTER(rd)); - WRITE16(rnv, rd == eR15 ? R15 + 8 + 4 : GET_REGISTER(rd)); //manual says STR RD=PC, +12 of address - if(rn != eR15) + // WRITE16(rnv, rd == eR15 ? R15 + 8 : GET_REGISTER(rd)); + WRITE16(rnv, rd == eR15 ? R15 + 8 + 4 : GET_REGISTER(rd)); // manual says STR RD=PC, +12 of address + if (rn != eR15) R15 += 4; - //STRH takes 2 cycles, so we add + 1 + // STRH takes 2 cycles, so we add + 1 ARM7_ICOUNT += 1; } - //SJE: No idea if this writeback code works or makes sense here.. + // SJE: No idea if this writeback code works or makes sense here.. /* Do post-indexing writeback */ - if (!(insn & INSN_SDT_P)/* && (insn&INSN_SDT_W)*/) + if (!(insn & INSN_SDT_P)/* && (insn & INSN_SDT_W)*/) { if (insn & INSN_SDT_U) { /* Writeback is applied in pipeline, before value is read from mem, so writeback is effectively ignored */ - if (rd==rn) { - SET_REGISTER(rn,GET_REGISTER(rd)); - //todo: check for offs... ? + if (rd == rn) { + SET_REGISTER(rn, GET_REGISTER(rd)); + // todo: check for offs... ? } else { - if ((insn&INSN_SDT_W)!=0) - LOG(("%08x: RegisterWritebackIncrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0)); + if ((insn & INSN_SDT_W) != 0) + LOG(("%08x: RegisterWritebackIncrement %d %d %d\n", R15, (insn & INSN_SDT_P) != 0, (insn & INSN_SDT_W) != 0, (insn & INSN_SDT_U) != 0)); - SET_REGISTER(rn,(rnv + off)); + SET_REGISTER(rn, (rnv + off)); } } else { /* Writeback is applied in pipeline, before value is read from mem, so writeback is effectively ignored */ - if (rd==rn) { - SET_REGISTER(rn,GET_REGISTER(rd)); + if (rd == rn) { + SET_REGISTER(rn, GET_REGISTER(rd)); } else { - SET_REGISTER(rn,(rnv - off)); + SET_REGISTER(rn, (rnv - off)); - if ((insn&INSN_SDT_W)!=0) - LOG(("%08x: RegisterWritebackDecrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0)); + if ((insn & INSN_SDT_W) != 0) + LOG(("%08x: RegisterWritebackDecrement %d %d %d\n", R15, (insn & INSN_SDT_P) != 0, (insn & INSN_SDT_W) != 0, (insn & INSN_SDT_U) != 0)); } } } - change_pc(R15); + change_pc(R15); } static void HandleSwap(UINT32 insn) { UINT32 rn, rm, rd, tmp; - rn = GET_REGISTER((insn>>16)&0xf); // reg. w/read address - rm = GET_REGISTER(insn&0xf); // reg. w/write address - rd = (insn>>12)&0xf; // dest reg + rn = GET_REGISTER((insn >> 16) & 0xf); // reg. w/read address + rm = GET_REGISTER(insn & 0xf); // reg. w/write address + rd = (insn >> 12) & 0xf; // dest reg - #if ARM7_DEBUG_CORE - if(rn == 15 || rm == 15 || rd == 15) - LOG(("%08x: Illegal use of R15 in Swap Instruction\n",R15)); - #endif +#if ARM7_DEBUG_CORE + if (rn == 15 || rm == 15 || rd == 15) + LOG(("%08x: Illegal use of R15 in Swap Instruction\n", R15)); +#endif // can be byte or word - if(insn & 0x400000) + if (insn & 0x400000) { - tmp = READ8(rn); - WRITE8(rn, rm); - SET_REGISTER(rd, tmp); + tmp = READ8(rn); + WRITE8(rn, rm); + SET_REGISTER(rd, tmp); } else { tmp = READ32(rn); - WRITE32(rn, rm); - SET_REGISTER(rd, tmp); + WRITE32(rn, rm); + SET_REGISTER(rd, tmp); } R15 += 4; - //Instruction takes 1S+2N+1I cycles - so we subtract one more.. - ARM7_ICOUNT -=1; + // Instruction takes 1S+2N+1I cycles - so we subtract one more.. + ARM7_ICOUNT -= 1; } -static void HandlePSRTransfer( UINT32 insn ) +static void HandlePSRTransfer(UINT32 insn) { - int reg = (insn & 0x400000) ? SPSR : eCPSR; //Either CPSR or SPSR + int reg = (insn & 0x400000) ? SPSR : eCPSR; // Either CPSR or SPSR UINT32 newval, val = 0; int oldmode = GET_CPSR & MODE_FLAG; // get old value of CPSR/SPSR newval = GET_REGISTER(reg); - //MSR ( bit 21 set ) - Copy value to CPSR/SPSR - if( (insn & 0x00200000) ) + // MSR (bit 21 set) - Copy value to CPSR/SPSR + if ((insn & 0x00200000)) { - //Immediate Value? - if(insn & INSN_I) { - //Value can be specified for a Right Rotate, 2x the value specified. + // Immediate Value? + if (insn & INSN_I) { + // Value can be specified for a Right Rotate, 2x the value specified. int by = (insn & INSN_OP2_ROTATE) >> INSN_OP2_ROTATE_SHIFT; if (by) val = ROR(insn & INSN_OP2_IMM, by << 1); else val = insn & INSN_OP2_IMM; } - //Value from Register + // Value from Register else - { + { val = GET_REGISTER(insn & 0x0f); } - // apply field code bits - if (reg == eCPSR) - { - if (oldmode != eARM7_MODE_USER) - { - if (insn & 0x00010000) - { - newval = (newval & 0xffffff00) | (val & 0xff); - } - if (insn & 0x00020000) - { - newval = (newval & 0xffff00ff) | (val & 0xff00); - } - if (insn & 0x00040000) - { - newval = (newval & 0xff00ffff) | (val & 0xff0000); - } - } + // apply field code bits + if (reg == eCPSR) + { + if (oldmode != eARM7_MODE_USER) + { + if (insn & 0x00010000) + { + newval = (newval & 0xffffff00) | (val & 0x000000ff); + } + if (insn & 0x00020000) + { + newval = (newval & 0xffff00ff) | (val & 0x0000ff00); + } + if (insn & 0x00040000) + { + newval = (newval & 0xff00ffff) | (val & 0x00ff0000); + } + } - // status flags can be modified regardless of mode - if (insn & 0x00080000) - { - // TODO for non ARMv5E mask should be 0xf0000000 (ie mask Q bit) - newval = (newval & 0x00ffffff) | (val & 0xf8000000); - } - } - else // SPSR has stricter requirements - { - if (((GET_CPSR & 0x1f) > 0x10) && ((GET_CPSR & 0x1f) < 0x1f)) - { - if (insn & 0x00010000) - { - newval = (newval & 0xffffff00) | (val & 0xff); - } - if (insn & 0x00020000) - { - newval = (newval & 0xffff00ff) | (val & 0xff00); - } - if (insn & 0x00040000) - { - newval = (newval & 0xff00ffff) | (val & 0xff0000); - } - if (insn & 0x00080000) - { - // TODO for non ARMv5E mask should be 0xf0000000 (ie mask Q bit) - newval = (newval & 0x00ffffff) | (val & 0xf8000000); - } - } - } + // status flags can be modified regardless of mode + if (insn & 0x00080000) + { + // TODO for non ARMv5E mask should be 0xf0000000 (ie mask Q bit) + newval = (newval & 0x00ffffff) | (val & 0xf8000000); + } + } + else // SPSR has stricter requirements + { + if (((GET_CPSR & 0x1f) > 0x10) && ((GET_CPSR & 0x1f) < 0x1f)) + { + if (insn & 0x00010000) + { + newval = (newval & 0xffffff00) | (val & 0xff); + } + if (insn & 0x00020000) + { + newval = (newval & 0xffff00ff) | (val & 0xff00); + } + if (insn & 0x00040000) + { + newval = (newval & 0xff00ffff) | (val & 0xff0000); + } + if (insn & 0x00080000) + { + // TODO for non ARMv5E mask should be 0xf0000000 (ie mask Q bit) + newval = (newval & 0x00ffffff) | (val & 0xf8000000); + } + } + } - // force valid mode - newval |= 0x10; + // force valid mode + newval |= 0x10; - //Update the Register + // Update the Register SET_REGISTER(reg, newval); - //Switch to new mode if changed - if( (newval & MODE_FLAG) != oldmode) + // Switch to new mode if changed + if ((newval & MODE_FLAG) != oldmode) SwitchMode(GET_MODE); } - //MRS ( bit 21 clear ) - Copy CPSR or SPSR to specified Register + // MRS (bit 21 clear) - Copy CPSR or SPSR to specified Register else { - SET_REGISTER( (insn>>12)& 0x0f ,GET_REGISTER(reg)); + SET_REGISTER((insn >> 12)& 0x0f, GET_REGISTER(reg)); } } -static void HandleALU( UINT32 insn ) +static void HandleALU(UINT32 insn) { - UINT32 op2, sc=0, rd, rn, opcode; + UINT32 op2, sc = 0, rd, rn, opcode; UINT32 by, rdn; UINT32 oldR15 = R15; @@ -1244,7 +1252,7 @@ static void HandleALU( UINT32 insn ) } else { - op2 = insn & INSN_OP2; //SJE: Shouldn't this be INSN_OP2_IMM? + op2 = insn & INSN_OP2; // SJE: Shouldn't this be INSN_OP2_IMM? sc = GET_CPSR & C_MASK; } } @@ -1253,19 +1261,21 @@ static void HandleALU( UINT32 insn ) { op2 = decodeShift(insn, (insn & INSN_S) ? &sc : NULL); + // LD TODO sc will always be 0 if this applies if (!(insn & INSN_S)) - sc=0; + sc = 0; } + // LD TODO this comment is wrong /* Calculate Rn to account for pipelining */ if ((opcode & 0xd) != 0xd) /* No Rn in MOV */ { if ((rn = (insn & INSN_RN) >> INSN_RN_SHIFT) == eR15) { - #if ARM7_DEBUG_CORE - LOG(("%08x: Pipelined R15 (Shift %d)\n",R15,(insn&INSN_I?8:insn&0x10u?12:12))); - #endif - rn=R15+8; +#if ARM7_DEBUG_CORE + LOG(("%08x: Pipelined R15 (Shift %d)\n", R15, (insn & INSN_I ? 8 : insn & 0x10u ? 12 : 12))); +#endif + rn = R15 + 8; } else { @@ -1312,7 +1322,7 @@ static void HandleALU( UINT32 insn ) HandleALULogicalFlags(rd, sc); break; case OPCODE_BIC: - rd = rn &~ op2; + rd = rn & ~op2; HandleALULogicalFlags(rd, sc); break; case OPCODE_TEQ: @@ -1338,17 +1348,17 @@ static void HandleALU( UINT32 insn ) rdn = (insn & INSN_RD) >> INSN_RD_SHIFT; if ((opcode & 0xc) != 0x8) { - //If Rd = R15, but S Flag not set, Result is placed in R15, but CPSR is not affected (page 44) + // If Rd = R15, but S Flag not set, Result is placed in R15, but CPSR is not affected (page 44) if (rdn == eR15 && !(insn & INSN_S)) { R15 = rd; } else { - //Rd = 15 and S Flag IS set, Result is placed in R15, and current mode SPSR moved to CPSR - if (rdn==eR15) { + // Rd = 15 and S Flag IS set, Result is placed in R15, and current mode SPSR moved to CPSR + if (rdn == eR15) { - //Update CPSR from SPSR + // Update CPSR from SPSR SET_CPSR(GET_REGISTER(SPSR)); SwitchMode(GET_MODE); @@ -1359,17 +1369,17 @@ static void HandleALU( UINT32 insn ) } else /* S Flag is set - Write results to register & update CPSR (which was already handled using HandleALU flag macros) */ - SET_REGISTER(rdn,rd); + SET_REGISTER(rdn, rd); } } - //SJE: Don't think this applies any more.. (see page 44 at bottom) + // SJE: Don't think this applies any more.. (see page 44 at bottom) /* TST & TEQ can affect R15 (the condition code register) with the S bit set */ - else if (rdn==eR15) + else if (rdn == eR15) { if (insn & INSN_S) { - #if ARM7_DEBUG_CORE - LOG(("%08x: TST class on R15 s bit set\n",R15)); - #endif +#if ARM7_DEBUG_CORE + LOG(("%08x: TST class on R15 s bit set\n", R15)); +#endif R15 = rd; /* IRQ masks may have changed in this instruction */ @@ -1377,65 +1387,63 @@ static void HandleALU( UINT32 insn ) } else { - #if ARM7_DEBUG_CORE - LOG(("%08x: TST class on R15 no s bit set\n",R15)); - #endif +#if ARM7_DEBUG_CORE + LOG(("%08x: TST class on R15 no s bit set\n", R15)); +#endif } } if (oldR15 != R15) - change_pc(R15); + change_pc(R15); } -static void HandleMul( UINT32 insn) +static void HandleMul(UINT32 insn) { UINT32 r; /* Do the basic multiply of Rm and Rs */ - r = GET_REGISTER( insn&INSN_MUL_RM ) * - GET_REGISTER( (insn&INSN_MUL_RS)>>INSN_MUL_RS_SHIFT ); + r = GET_REGISTER(insn & INSN_MUL_RM) * + GET_REGISTER((insn & INSN_MUL_RS) >> INSN_MUL_RS_SHIFT); - #if ARM7_DEBUG_CORE - if( - ((insn&INSN_MUL_RM)==0xf) || - (((insn&INSN_MUL_RS)>>INSN_MUL_RS_SHIFT )==0xf) || - (((insn&INSN_MUL_RN)>>INSN_MUL_RN_SHIFT)==0xf) - ) - LOG(("%08x: R15 used in mult\n",R15)); - #endif +#if ARM7_DEBUG_CORE + if ((insn & INSN_MUL_RM) == 0xf || + ((insn & INSN_MUL_RS) >> INSN_MUL_RS_SHIFT) == 0xf || + ((insn & INSN_MUL_RN) >> INSN_MUL_RN_SHIFT) == 0xf) + LOG(("%08x: R15 used in mult\n", R15)); +#endif /* Add on Rn if this is a MLA */ if (insn & INSN_MUL_A) { - r += GET_REGISTER((insn&INSN_MUL_RN)>>INSN_MUL_RN_SHIFT); + r += GET_REGISTER((insn & INSN_MUL_RN) >> INSN_MUL_RN_SHIFT); } /* Write the result */ - SET_REGISTER((insn&INSN_MUL_RD)>>INSN_MUL_RD_SHIFT,r); + SET_REGISTER((insn & INSN_MUL_RD) >> INSN_MUL_RD_SHIFT, r); /* Set N and Z if asked */ - if( insn & INSN_S ) + if (insn & INSN_S) { - SET_CPSR ( (GET_CPSR &~ (N_MASK | Z_MASK)) | HandleALUNZFlags(r)); + SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleALUNZFlags(r)); } } -//todo: add proper cycle counts -static void HandleSMulLong( UINT32 insn) +// todo: add proper cycle counts +static void HandleSMulLong(UINT32 insn) { INT32 rm, rs; - UINT32 rhi,rlo; - INT64 res=0; + UINT32 rhi, rlo; + INT64 res = 0; - rm = (INT32)GET_REGISTER(insn&0xf); - rs = (INT32)GET_REGISTER(((insn>>8)&0xf)); - rhi = (insn>>16)&0xf; - rlo = (insn>>12)&0xf; + rm = (INT32)GET_REGISTER(insn & 0xf); + rs = (INT32)GET_REGISTER(((insn >> 8) & 0xf)); + rhi = (insn >> 16) & 0xf; + rlo = (insn >> 12) & 0xf; - #if ARM7_DEBUG_CORE - if( ((insn&0xf) == 15) || (((insn>>8)&0xf) == 15) || (((insn>>16)&0xf) == 15) || (((insn>>12)&0xf) == 15) - LOG(("%08x: Illegal use of PC as a register in SMULL opcode\n",R15)); - #endif +#if ARM7_DEBUG_CORE + if ((insn & 0xf) == 15 || ((insn >> 8) & 0xf) == 15 || ((insn >> 16) & 0xf) == 15 || ((insn >> 12) & 0xf) == 15) + LOG(("%08x: Illegal use of PC as a register in SMULL opcode\n", R15)); +#endif /* Perform the multiplication */ res = (INT64)rm * rs; @@ -1443,37 +1451,37 @@ static void HandleSMulLong( UINT32 insn) /* Add on Rn if this is a MLA */ if (insn & INSN_MUL_A) { - INT64 acum = (INT64)((((INT64)(GET_REGISTER(rhi)))<<32) | GET_REGISTER(rlo)); + INT64 acum = (INT64)((((INT64)(GET_REGISTER(rhi))) << 32) | GET_REGISTER(rlo)); res += acum; } /* Write the result (upper dword goes to RHi, lower to RLo) */ - SET_REGISTER(rhi, res>>32); + SET_REGISTER(rhi, res >> 32); SET_REGISTER(rlo, res & 0xFFFFFFFF); /* Set N and Z if asked */ - if( insn & INSN_S ) + if (insn & INSN_S) { - SET_CPSR ( (GET_CPSR &~ (N_MASK | Z_MASK)) | HandleLongALUNZFlags(res)); + SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleLongALUNZFlags(res)); } } -//todo: add proper cycle counts -static void HandleUMulLong( UINT32 insn) +// todo: add proper cycle counts +static void HandleUMulLong(UINT32 insn) { UINT32 rm, rs; - UINT32 rhi,rlo; - UINT64 res=0; + UINT32 rhi, rlo; + UINT64 res = 0; - rm = (INT32)GET_REGISTER(insn&0xf); - rs = (INT32)GET_REGISTER(((insn>>8)&0xf)); - rhi = (insn>>16)&0xf; - rlo = (insn>>12)&0xf; + rm = (INT32)GET_REGISTER(insn & 0xf); + rs = (INT32)GET_REGISTER(((insn >> 8) & 0xf)); + rhi = (insn >> 16) & 0xf; + rlo = (insn >> 12) & 0xf; - #if ARM7_DEBUG_CORE - if( ((insn&0xf) == 15) || (((insn>>8)&0xf) == 15) || (((insn>>16)&0xf) == 15) || (((insn>>12)&0xf) == 15) - LOG(("%08x: Illegal use of PC as a register in SMULL opcode\n",R15)); - #endif +#if ARM7_DEBUG_CORE + if (((insn & 0xf) == 15) || (((insn >> 8) & 0xf) == 15) || (((insn >> 16) & 0xf) == 15) || (((insn >> 12) & 0xf) == 15) + LOG(("%08x: Illegal use of PC as a register in SMULL opcode\n", R15)); +#endif /* Perform the multiplication */ res = (UINT64)rm * rs; @@ -1481,22 +1489,22 @@ static void HandleUMulLong( UINT32 insn) /* Add on Rn if this is a MLA */ if (insn & INSN_MUL_A) { - UINT64 acum = (UINT64)((((UINT64)(GET_REGISTER(rhi)))<<32) | GET_REGISTER(rlo)); + UINT64 acum = (UINT64)((((UINT64)(GET_REGISTER(rhi))) << 32) | GET_REGISTER(rlo)); res += acum; } /* Write the result (upper dword goes to RHi, lower to RLo) */ - SET_REGISTER(rhi, res>>32); + SET_REGISTER(rhi, res >> 32); SET_REGISTER(rlo, res & 0xFFFFFFFF); /* Set N and Z if asked */ - if( insn & INSN_S ) + if (insn & INSN_S) { - SET_CPSR ( (GET_CPSR &~ (N_MASK | Z_MASK)) | HandleLongALUNZFlags(res)); + SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleLongALUNZFlags(res)); } } -static void HandleMemBlock( UINT32 insn) +static void HandleMemBlock(UINT32 insn) { UINT32 rb = (insn & INSN_RN) >> INSN_RN_SHIFT; UINT32 rbp = GET_REGISTER(rb); @@ -1504,12 +1512,12 @@ static void HandleMemBlock( UINT32 insn) int result; #if ARM7_DEBUG_CORE - if(rbp & 3) - LOG(("%08x: Unaligned Mem Transfer @ %08x\n",R15,rbp)); + if (rbp & 3) + LOG(("%08x: Unaligned Mem Transfer @ %08x\n", R15, rbp)); #endif - //We will specify the cycle count for each case, so remove the -3 that occurs at the end - ARM7_ICOUNT +=3; + // We will specify the cycle count for each case, so remove the -3 that occurs at the end + ARM7_ICOUNT += 3; if (insn & INSN_BDT_L) { @@ -1522,40 +1530,40 @@ static void HandleMemBlock( UINT32 insn) rbp = rbp + (- 4); } - //S Flag Set, but R15 not in list = User Bank Transfer - if(insn & INSN_BDT_S && ((insn & 0x8000)==0)) + // S Flag Set, but R15 not in list = User Bank Transfer + if (insn & INSN_BDT_S && (insn & 0x8000) == 0) { - //set to user mode - then do the transfer, and set back + // set to user mode - then do the transfer, and set back int curmode = GET_MODE; SwitchMode(eARM7_MODE_USER); - LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n",R15)); - result = loadInc( insn & 0xffff, rbp, insn&INSN_BDT_S ); - //todo - not sure if Writeback occurs on User registers also.. + LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15)); + result = loadInc(insn & 0xffff, rbp, insn & INSN_BDT_S); + // todo - not sure if Writeback occurs on User registers also.. SwitchMode(curmode); } else - result = loadInc( insn & 0xffff, rbp, insn&INSN_BDT_S ); + result = loadInc(insn & 0xffff, rbp, insn & INSN_BDT_S); if (insn & INSN_BDT_W) { - #if ARM7_DEBUG_CORE - if(rb==15) - LOG(("%08x: Illegal LDRM writeback to r15\n",R15)); - #endif - SET_REGISTER(rb,GET_REGISTER(rb)+result*4); +#if ARM7_DEBUG_CORE + if (rb == 15) + LOG(("%08x: Illegal LDRM writeback to r15\n", R15)); +#endif + SET_REGISTER(rb, GET_REGISTER(rb) + result * 4); } - //R15 included? (NOTE: CPSR restore must occur LAST otherwise wrong registers restored!) + // R15 included? (NOTE: CPSR restore must occur LAST otherwise wrong registers restored!) if (insn & 0x8000) { - R15-=4; //SJE: I forget why i did this? - //S - Flag Set? Signals transfer of current mode SPSR->CPSR - if(insn & INSN_BDT_S) { + R15 -= 4; // SJE: I forget why i did this? + // S - Flag Set? Signals transfer of current mode SPSR->CPSR + if (insn & INSN_BDT_S) { SET_CPSR(GET_REGISTER(SPSR)); SwitchMode(GET_MODE); } } - //LDM PC - takes 1 extra cycle - ARM7_ICOUNT -=1; + // LDM PC - takes 1 extra cycle + ARM7_ICOUNT -= 1; } else { @@ -1565,51 +1573,51 @@ static void HandleMemBlock( UINT32 insn) rbp = rbp - (- 4); } - //S Flag Set, but R15 not in list = User Bank Transfer - if(insn & INSN_BDT_S && ((insn & 0x8000)==0)) + // S Flag Set, but R15 not in list = User Bank Transfer + if (insn & INSN_BDT_S && ((insn & 0x8000) == 0)) { - //set to user mode - then do the transfer, and set back + // set to user mode - then do the transfer, and set back int curmode = GET_MODE; SwitchMode(eARM7_MODE_USER); - LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n",R15)); - result = loadDec( insn&0xffff, rbp, insn&INSN_BDT_S ); - //todo - not sure if Writeback occurs on User registers also.. + LOG(("%08x: User Bank Transfer not fully tested - please check if working properly!\n", R15)); + result = loadDec(insn & 0xffff, rbp, insn & INSN_BDT_S); + // todo - not sure if Writeback occurs on User registers also.. SwitchMode(curmode); } else - result = loadDec( insn&0xffff, rbp, insn&INSN_BDT_S ); + result = loadDec(insn & 0xffff, rbp, insn & INSN_BDT_S); if (insn & INSN_BDT_W) { - if (rb==0xf) - LOG(("%08x: Illegal LDRM writeback to r15\n",R15)); - SET_REGISTER(rb,GET_REGISTER(rb)-result*4); + if (rb == 0xf) + LOG(("%08x: Illegal LDRM writeback to r15\n", R15)); + SET_REGISTER(rb, GET_REGISTER(rb)-result*4); } - //R15 included? (NOTE: CPSR restore must occur LAST otherwise wrong registers restored!) + // R15 included? (NOTE: CPSR restore must occur LAST otherwise wrong registers restored!) if (insn & 0x8000) { - R15-=4; //SJE: I forget why i did this? - //S - Flag Set? Signals transfer of current mode SPSR->CPSR - if(insn & INSN_BDT_S) { + R15 -= 4; // SJE: I forget why i did this? + // S - Flag Set? Signals transfer of current mode SPSR->CPSR + if (insn & INSN_BDT_S) { SET_CPSR(GET_REGISTER(SPSR)); SwitchMode(GET_MODE); } - //LDM PC - takes 1 extra cycle - ARM7_ICOUNT -=1; + // LDM PC - takes 1 extra cycle + ARM7_ICOUNT -= 1; } - //LDM (NO PC) takes nS + 1n + 1I cycles (n = # of register transfers) - ARM7_ICOUNT -= (result+1+1); + // LDM (NO PC) takes nS + 1n + 1I cycles (n = # of register transfers) + ARM7_ICOUNT -= result + 1 + 1; } } /* Loading */ else { /* Storing */ - if (insn & (1<> (s)) -#define ROL(v,s) (LSL((v),(s)) | (LSR((v),32u - (s)))) -#define ROR(v,s) (LSR((v),(s)) | (LSL((v),32u - (s)))) +#define LSL(v, s) ((v) << (s)) +#define LSR(v, s) ((v) >> (s)) +#define ROL(v, s) (LSL((v), (s)) | (LSR((v), 32u - (s)))) +#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s)))) /* Convenience Macros */ #define R15 ARM7REG(eR15) -#define SPSR 17 //SPSR is always the 18th register in our 0 based array sRegisterTable[][18] +#define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18] #define GET_CPSR ARM7REG(eCPSR) #define SET_CPSR(v) (GET_CPSR = (v)) -#define MODE_FLAG 0xF //Mode bits are 4:0 of CPSR, but we ignore bit 4. +#define MODE_FLAG 0xF // Mode bits are 4:0 of CPSR, but we ignore bit 4. #define GET_MODE (GET_CPSR & MODE_FLAG) -#define SIGN_BIT ((UINT32)(1<<31)) -#define SIGN_BITS_DIFFER(a,b) (((a)^(b)) >> 31) +#define SIGN_BIT ((UINT32)(1 << 31)) +#define SIGN_BITS_DIFFER(a, b) (((a) ^ (b)) >> 31) /* I really don't know why these were set to 16-bit, the thumb registers are still 32-bit ... */ -#define THUMB_SIGN_BIT ((UINT32)(1<<31)) -#define THUMB_SIGN_BITS_DIFFER(a,b) (((a)^(b)) >> 31) +#define THUMB_SIGN_BIT ((UINT32)(1 << 31)) +#define THUMB_SIGN_BITS_DIFFER(a, b) (((a)^(b)) >> 31) /* At one point I thought these needed to be cpu implementation specific, but they don't.. */ #define GET_REGISTER(reg) GetRegister(reg) -#define SET_REGISTER(reg,val) SetRegister(reg,val) +#define SET_REGISTER(reg, val) SetRegister(reg, val) #define ARM7_CHECKIRQ arm7_check_irq_state() extern WRITE32_HANDLER((*arm7_coproc_do_callback)); extern READ32_HANDLER((*arm7_coproc_rt_r_callback)); extern WRITE32_HANDLER((*arm7_coproc_rt_w_callback)); -extern void (*arm7_coproc_dt_r_callback)(UINT32 insn, UINT32* prn, UINT32 (*read32)(int addr)); -extern void (*arm7_coproc_dt_w_callback)(UINT32 insn, UINT32* prn, void (*write32)(int addr, UINT32 data)); +extern void (*arm7_coproc_dt_r_callback)(UINT32 insn, UINT32* prn, UINT32 (*read32)(UINT32 addr)); +extern void (*arm7_coproc_dt_w_callback)(UINT32 insn, UINT32* prn, void (*write32)(UINT32 addr, UINT32 data)); #ifdef ENABLE_DEBUGGER -extern UINT32 arm7_disasm( char *pBuf, UINT32 pc, UINT32 opcode ); -extern UINT32 thumb_disasm( char *pBuf, UINT32 pc, UINT16 opcode ); +extern UINT32 arm7_disasm(char *pBuf, UINT32 pc, UINT32 opcode); +extern UINT32 thumb_disasm(char *pBuf, UINT32 pc, UINT16 opcode); -extern char *(*arm7_dasm_cop_dt_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 ); -extern char *(*arm7_dasm_cop_rt_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 ); -extern char *(*arm7_dasm_cop_do_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 ); +extern char *(*arm7_dasm_cop_dt_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); +extern char *(*arm7_dasm_cop_rt_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); +extern char *(*arm7_dasm_cop_do_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0); #endif #endif /* ARM7CORE_H */ -