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Netlist: code maintenance

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- rename netlist_analog_t to analog_t 
- straighten object model
- reduce access to member variables
- use pvector<analog_net_t::list_t> for groups.
- simple coverity fixes.
This commit is contained in:
couriersud 2016-03-17 01:24:52 +01:00
parent c22a27df81
commit 489e2919db
24 changed files with 263 additions and 285 deletions
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34
nl_examples/kidniki.c
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@ -4,22 +4,27 @@
#include "netlist/devices/nld_system.h"
#include "netlist/analog/nld_bjt.h"
#define USE_FRONTIERS 0
#define USE_FIXED_STV 0
#define USE_FRONTIERS 1
#define USE_FIXED_STV 1
NETLIST_START(dummy)
SOLVER(Solver, 12000)
PARAM(Solver.ACCURACY, 1e-7)
#if (USE_FRONTIERS)
SOLVER(Solver, 18000)
PARAM(Solver.ACCURACY, 1e-8)
PARAM(Solver.NR_LOOPS, 300)
PARAM(Solver.GS_LOOPS, 23)
//PARAM(Solver.GS_THRESHOLD, 99) // Force Gaussian elimination here
PARAM(Solver.SOR_FACTOR, 1.05)
PARAM(Solver.GS_LOOPS, 1)
PARAM(Solver.GS_THRESHOLD, 6)
PARAM(Solver.ITERATIVE, "SOR")
PARAM(Solver.PARALLEL, 0)
PARAM(Solver.SOR_FACTOR, 1.00)
#else
SOLVER(Solver, 12000)
PARAM(Solver.ACCURACY, 1e-8)
PARAM(Solver.NR_LOOPS, 300)
PARAM(Solver.GS_LOOPS, 20)
PARAM(Solver.ITERATIVE, "GMRES")
#if 0
//PARAM(Solver.SOR_FACTOR, 1)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.LTE, 1e-1)
#endif
PARAM(Solver.PARALLEL, 0)
#endif
//FIXME proper models!
//NET_MODEL("2SC945 NPN(Is=2.04f Xti=3 Eg=1.11 Vaf=6 Bf=400 Ikf=20m Xtb=1.5 Br=3.377 Rc=1 Cjc=1p Mjc=.3333 Vjc=.75 Fc=.5 Cje=25p Mje=.3333 Vje=.75 Tr=450n Tf=20n Itf=0 Vtf=0 Xtf=0 VCEO=45V ICrating=150M MFG=Toshiba)")
//NET_MODEL("1S1588 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
@ -70,6 +75,11 @@ NETLIST_START(dummy)
OPTIMIZE_FRONTIER(C63.2, RES_K(27), RES_K(1))
OPTIMIZE_FRONTIER(R31.2, RES_K(5.1), 50)
OPTIMIZE_FRONTIER(R29.2, RES_K(2.7), 50)
OPTIMIZE_FRONTIER(R87.2, RES_K(68), 50)
OPTIMIZE_FRONTIER(R50.1, RES_K(2.2), 50)
OPTIMIZE_FRONTIER(R55.1, RES_K(510), 50)
OPTIMIZE_FRONTIER(R84.2, RES_K(50), RES_K(5))
#endif
NETLIST_END()

2
scripts/src/netlist.lua
View File

@ -86,8 +86,6 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_4020.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7400.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7400.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7402.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7402.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7404.cpp",

2
src/lib/netlist/analog/nld_fourterm.cpp
View File

@ -108,7 +108,7 @@ NETLIB_UPDATE(LVCCS)
NETLIB_UPDATE_TERMINALS(LVCCS)
{
const nl_double m_mult = m_G.Value() * m_gfac; // 1.0 ==> 1V ==> 1A
const nl_double vi = m_IP.net().m_cur_Analog - m_IN.net().m_cur_Analog;
const nl_double vi = m_IP.net().Q_Analog() - m_IN.net().Q_Analog();
if (std::abs(m_mult / m_cur_limit * vi) > 0.5)
m_vi = m_vi + 0.2*std::tanh((vi - m_vi)/0.2);

2
src/lib/netlist/analog/nld_twoterm.cpp
View File

@ -20,6 +20,8 @@ ATTR_COLD generic_diode::generic_diode()
{
m_Vd = 0.7;
set_param(1e-15, 1, 1e-15);
m_G = m_gmin;
m_Id = 0.0;
}
ATTR_COLD void generic_diode::set_param(const nl_double Is, const nl_double n, nl_double gmin)

3
src/lib/netlist/devices/net_lib.cpp
View File

@ -52,6 +52,7 @@ NETLIST_START(family_models)
NET_MODEL("OPAMP _()")
NET_MODEL("74XXOC FAMILY(IVL=0.8 IVH=2.0 OVL=0.1 OVH=4.95 ORL=10.0 ORH=1.0e8)")
NET_MODEL("74XX FAMILY(TYPE=TTL)")
NET_MODEL("CD4XXX FAMILY(TYPE=CD4XXX)")
NETLIST_END()
@ -97,7 +98,6 @@ void initialize_factory(factory_list_t &factory)
ENTRY(switch2, SWITCH2, "-")
ENTRY(nicRSFF, NETDEV_RSFF, "+S,R")
ENTRY(nicDelay, NETDEV_DELAY, "-")
ENTRY(7400, TTL_7400_NAND, "+A,B")
ENTRY(7402, TTL_7402_NOR, "+A,B")
ENTRY(7404, TTL_7404_INVERT, "+A")
ENTRY(7408, TTL_7408_AND, "+A,B")
@ -137,7 +137,6 @@ void initialize_factory(factory_list_t &factory)
ENTRY(NE555, NE555, "-")
ENTRY(r2r_dac, R2R_DAC, "+VIN,R,N")
ENTRY(4538_dip, CD4538_DIP, "-")
ENTRY(7400_dip, TTL_7400_DIP, "-")
ENTRY(7402_dip, TTL_7402_DIP, "-")
ENTRY(7404_dip, TTL_7404_DIP, "-")
ENTRY(7408_dip, TTL_7408_DIP, "-")

1
src/lib/netlist/devices/net_lib.h
View File

@ -17,7 +17,6 @@
#include "nld_4020.h"
#include "nld_4066.h"
#include "nld_7400.h"
#include "nld_7402.h"
#include "nld_7404.h"
#include "nld_7408.h"

65
src/lib/netlist/devices/nld_7400.cpp
View File

@ -1,65 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7400.c
*
*/
#include "nld_7400.h"
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)
nld_7400::truthtable_t nld_7400::m_ttbl;
const char *nld_7400::m_desc[] = {
"A , B | Q ",
"0,X|1|22",
"X,0|1|22",
"1,1|0|15",
""
};
#endif
NETLIB_START(7400_dip)
{
register_sub("1", m_1);
register_sub("2", m_2);
register_sub("3", m_3);
register_sub("4", m_4);
register_subalias("1", m_1.m_I[0]);
register_subalias("2", m_1.m_I[1]);
register_subalias("3", m_1.m_Q[0]);
register_subalias("4", m_2.m_I[0]);
register_subalias("5", m_2.m_I[1]);
register_subalias("6", m_2.m_Q[0]);
register_subalias("9", m_3.m_I[0]);
register_subalias("10", m_3.m_I[1]);
register_subalias("8", m_3.m_Q[0]);
register_subalias("12", m_4.m_I[0]);
register_subalias("13", m_4.m_I[1]);
register_subalias("11", m_4.m_Q[0]);
}
NETLIB_UPDATE(7400_dip)
{
/* only called during startup */
m_1.update_dev();
m_2.update_dev();
m_3.update_dev();
m_4.update_dev();
}
NETLIB_RESET(7400_dip)
{
m_1.do_reset();
m_2.do_reset();
m_3.do_reset();
m_4.do_reset();
}
NETLIB_NAMESPACE_DEVICES_END()

64
src/lib/netlist/devices/nld_7400.h
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@ -1,64 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7400.h
*
* DM7400: Quad 2-Input NAND Gates
*
* +--------------+
* A1 |1 ++ 14| VCC
* B1 |2 13| B4
* Y1 |3 12| A4
* A2 |4 7400 11| Y4
* B2 |5 10| B3
* Y2 |6 9| A3
* GND |7 8| Y3
* +--------------+
* __
* Y = AB
* +---+---++---+
* | A | B || Y |
* +===+===++===+
* | 0 | 0 || 1 |
* | 0 | 1 || 1 |
* | 1 | 0 || 1 |
* | 1 | 1 || 0 |
* +---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
#ifndef NLD_7400_H_
#define NLD_7400_H_
#include "nld_signal.h"
#include "nld_truthtable.h"
#define TTL_7400_NAND(_name, _A, _B) \
NET_REGISTER_DEV(TTL_7400_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_CONNECT(_name, B, _B)
#define TTL_7400_DIP(_name) \
NET_REGISTER_DEV(TTL_7400_DIP, _name)
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)
NETLIB_TRUTHTABLE(7400, 2, 1, 0);
#else
NETLIB_SIGNAL(7400, 2, 0, 0);
#endif
NETLIB_DEVICE(7400_dip,
NETLIB_NAME(7400) m_1;
NETLIB_NAME(7400) m_2;
NETLIB_NAME(7400) m_3;
NETLIB_NAME(7400) m_4;
);
NETLIB_NAMESPACE_DEVICES_END()
#endif /* NLD_7400_H_ */

2
src/lib/netlist/devices/nld_mm5837.cpp
View File

@ -45,7 +45,7 @@ NETLIB_RESET(MM5837_dip)
m_RV.set(NL_FCONST(1.0) / R_LOW, 0.0, 0.0);
m_shift = 0x1ffff;
m_is_timestep = m_RV.m_P.net().as_analog().solver()->is_timestep();
m_is_timestep = m_RV.m_P.net().solver()->is_timestep();
}
NETLIB_UPDATE(MM5837_dip)

2
src/lib/netlist/devices/nld_system.cpp
View File

@ -212,7 +212,7 @@ void nld_d_to_a_proxy::reset()
m_Q.initial(0.0);
m_last_state = -1;
m_RV.do_reset();
m_is_timestep = m_RV.m_P.net().as_analog().solver()->is_timestep();
m_is_timestep = m_RV.m_P.net().solver()->is_timestep();
m_RV.set(NL_FCONST(1.0) / logic_family().m_R_low, logic_family().m_low_V, 0.0);
}

2
src/lib/netlist/devices/nld_truthtable.h
View File

@ -298,7 +298,7 @@ class netlist_base_factory_truthtable_t : public base_factory_t
public:
netlist_base_factory_truthtable_t(const pstring &name, const pstring &classname,
const pstring &def_param)
: base_factory_t(name, classname, def_param), m_family(netlist_family_TTL)
: base_factory_t(name, classname, def_param), m_family(family_TTL)
{}
virtual ~netlist_base_factory_truthtable_t()

71
src/lib/netlist/macro/nlm_ttl74xx.cpp
View File

@ -9,16 +9,6 @@
* DM7416: Hex Inverting Buffers with
* High Voltage Open-Collector Outputs
*
* +--------------+
* A1 |1 ++ 14| VCC
* Y1 |2 13| A6
* A2 |3 12| Y6
* Y2 |4 7416 11| A5
* A3 |5 10| Y5
* Y3 |6 9| A4
* GND |7 8| Y4
* +--------------+
*
*/
NETLIST_START(TTL_7416_DIP)
@ -40,11 +30,69 @@ NETLIST_START(TTL_7416_DIP)
s3.A, /* A3 |5 10| Y5 */ s5.Q,
s3.Q, /* Y3 |6 9| A4 */ s4.A,
GND.I, /* GND |7 8| Y4 */ s4.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
/*
* DM7400: Quad 2-Input NAND Gates
*
* __
* Y = AB
* +---+---++---+
* | A | B || Y |
* +===+===++===+
* | 0 | 0 || 1 |
* | 0 | 1 || 1 |
* | 1 | 0 || 1 |
* | 1 | 1 || 0 |
* +---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
NETLIST_START(TTL_7400_DIP)
TTL_7400_GATE(s1)
TTL_7400_GATE(s2)
TTL_7400_GATE(s3)
TTL_7400_GATE(s4)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VCC.I,
s1.B, /* B1 |2 13| B4 */ s4.B,
s1.Q, /* Y1 |3 12| A4 */ s4.A,
s2.A, /* A2 |4 7400 11| Y4 */ s4.Q,
s2.B, /* B2 |5 10| B3 */ s3.B,
s2.Q, /* Y2 |6 9| A3 */ s3.A,
GND.I, /* GND |7 8| Y3 */ s3.Q
/* +--------------+ */
)
NETLIST_END()
NETLIST_START(TTL74XX_lib)
TRUTHTABLE_START(TTL_7400_GATE, 2, 1, 0, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|1|22")
TT_LINE("X,0|1|22")
TT_LINE("1,1|0|15")
/* Open Collector */
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7400_NAND, 2, 1, 0, "+A,B")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|1|22")
TT_LINE("X,0|1|22")
TT_LINE("1,1|0|15")
/* Open Collector */
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7416_GATE, 1, 1, 0, "")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |15")
@ -54,4 +102,5 @@ NETLIST_START(TTL74XX_lib)
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(TTL_7416_DIP)
LOCAL_LIB_ENTRY(TTL_7400_DIP)
NETLIST_END()

11
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -11,6 +11,17 @@
* Netlist Macros
* ---------------------------------------------------------------------------*/
#define TTL_7400_GATE(_name) \
NET_REGISTER_DEV(TTL_7400_GATE, _name) \
#define TTL_7400_NAND(_name, _A, _B) \
NET_REGISTER_DEV(TTL_7400_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_CONNECT(_name, B, _B)
#define TTL_7400_DIP(_name) \
NET_REGISTER_DEV(TTL_7400_DIP, _name)
#define TTL_7416_GATE(_name) \
NET_REGISTER_DEV(TTL_7416_GATE, _name)

66
src/lib/netlist/nl_base.cpp
View File

@ -64,11 +64,11 @@ public:
}
};
logic_family_desc_t *netlist_family_TTL = palloc(logic_family_ttl_t);
logic_family_desc_t *netlist_family_CD4XXX = palloc(logic_family_cd4xxx_t);
logic_family_desc_t *family_TTL = palloc(logic_family_ttl_t);
logic_family_desc_t *family_CD4XXX = palloc(logic_family_cd4xxx_t);
// ----------------------------------------------------------------------------------------
// netlist_queue_t
// queue_t
// ----------------------------------------------------------------------------------------
queue_t::queue_t(netlist_t &nl)
@ -121,7 +121,7 @@ void queue_t::on_post_load()
}
// ----------------------------------------------------------------------------------------
// netlist_object_t
// object_t
// ----------------------------------------------------------------------------------------
ATTR_COLD object_t::object_t(const type_t atype, const family_t afamily)
@ -149,7 +149,7 @@ ATTR_COLD const pstring &object_t::name() const
}
// ----------------------------------------------------------------------------------------
// netlist_owned_object_t
// device_object_t
// ----------------------------------------------------------------------------------------
ATTR_COLD device_object_t::device_object_t(const type_t atype,
@ -167,7 +167,7 @@ ATTR_COLD void device_object_t::init_object(core_device_t &dev,
}
// ----------------------------------------------------------------------------------------
// netlist_base_t
// netlist_t
// ----------------------------------------------------------------------------------------
netlist_t::netlist_t()
@ -179,6 +179,7 @@ netlist_t::netlist_t()
m_mainclock(NULL),
m_solver(NULL),
m_gnd(NULL),
m_params(NULL),
m_setup(NULL),
m_log(this)
{
@ -425,7 +426,7 @@ ATTR_HOT netlist_sig_t core_device_t::INPLOGIC_PASSIVE(logic_input_t &inp)
// ----------------------------------------------------------------------------------------
// netlist_device_t
// device_t
// ----------------------------------------------------------------------------------------
device_t::device_t()
@ -555,7 +556,7 @@ template ATTR_COLD void device_t::register_param(const pstring &sname, param_mod
// ----------------------------------------------------------------------------------------
// netlist_net_t
// net_t
// ----------------------------------------------------------------------------------------
ATTR_COLD net_t::net_t(const family_t afamily)
@ -742,7 +743,7 @@ ATTR_COLD void net_t::merge_net(net_t *othernet)
// ----------------------------------------------------------------------------------------
// netlist_logic_net_t
// logic_net_t
// ----------------------------------------------------------------------------------------
ATTR_COLD logic_net_t::logic_net_t()
@ -762,7 +763,7 @@ ATTR_COLD void logic_net_t::save_register()
}
// ----------------------------------------------------------------------------------------
// netlist_analog_net_t
// analog_net_t
// ----------------------------------------------------------------------------------------
ATTR_COLD analog_net_t::analog_net_t()
@ -785,39 +786,39 @@ ATTR_COLD void analog_net_t::save_register()
net_t::save_register();
}
ATTR_COLD bool analog_net_t::already_processed(list_t *groups, int cur_group)
ATTR_COLD bool analog_net_t::already_processed(pvector_t<list_t> &groups)
{
if (isRailNet())
return true;
for (int i = 0; i <= cur_group; i++)
for (auto & grp : groups)
{
if (groups[i].contains(this))
if (grp.contains(this))
return true;
}
return false;
}
ATTR_COLD void analog_net_t::process_net(list_t *groups, int &cur_group)
ATTR_COLD void analog_net_t::process_net(pvector_t<list_t> &groups)
{
if (num_cons() == 0)
return;
/* add the net */
groups[cur_group].push_back(this);
groups.back().push_back(this);
for (core_terminal_t *p : m_core_terms)
{
if (p->isType(terminal_t::TERMINAL))
{
terminal_t *pt = static_cast<terminal_t *>(p);
analog_net_t *other_net = &pt->m_otherterm->net().as_analog();
if (!other_net->already_processed(groups, cur_group))
other_net->process_net(groups, cur_group);
analog_net_t *other_net = &pt->m_otherterm->net();
if (!other_net->already_processed(groups))
other_net->process_net(groups);
}
}
}
// ----------------------------------------------------------------------------------------
// netlist_core_terminal_t
// core_terminal_t
// ----------------------------------------------------------------------------------------
ATTR_COLD core_terminal_t::core_terminal_t(const type_t atype, const family_t afamily)
@ -834,11 +835,11 @@ ATTR_COLD void core_terminal_t::set_net(net_t &anet)
}
// ----------------------------------------------------------------------------------------
// netlist_terminal_t
// terminal_t
// ----------------------------------------------------------------------------------------
ATTR_COLD terminal_t::terminal_t()
: core_terminal_t(TERMINAL, ANALOG)
: analog_t(TERMINAL)
, m_Idr1(NULL)
, m_go1(NULL)
, m_gt1(NULL)
@ -846,18 +847,19 @@ ATTR_COLD terminal_t::terminal_t()
{
}
ATTR_HOT void terminal_t::schedule_solve()
{
// FIXME: Remove this after we found a way to remove *ALL* twoterms connected to railnets only.
if (net().as_analog().solver() != NULL)
net().as_analog().solver()->update_forced();
if (net().solver() != NULL)
net().solver()->update_forced();
}
ATTR_HOT void terminal_t::schedule_after(const netlist_time &after)
{
// FIXME: Remove this after we found a way to remove *ALL* twoterms connected to railnets only.
if (net().as_analog().solver() != NULL)
net().as_analog().solver()->update_after(after);
if (net().solver() != NULL)
net().solver()->update_after(after);
}
ATTR_COLD void terminal_t::reset()
@ -886,7 +888,7 @@ ATTR_COLD void terminal_t::save_register()
// ----------------------------------------------------------------------------------------
// ----------------------------------------------------------------------------------------
// netlist_logic_output_t
// logic_output_t
// ----------------------------------------------------------------------------------------
ATTR_COLD logic_output_t::logic_output_t()
@ -910,32 +912,32 @@ ATTR_COLD void logic_output_t::initial(const netlist_sig_t val)
// ----------------------------------------------------------------------------------------
// netlist_analog_output_t
// analog_output_t
// ----------------------------------------------------------------------------------------
ATTR_COLD analog_output_t::analog_output_t()
: netlist_analog_t(OUTPUT), m_proxied_net(NULL)
: analog_t(OUTPUT), m_proxied_net(NULL)
{
this->set_net(m_my_net);
set_state(STATE_OUT);
net().as_analog().m_cur_Analog = NL_FCONST(0.99);
net().m_cur_Analog = NL_FCONST(0.99);
}
ATTR_COLD void analog_output_t::init_object(core_device_t &dev, const pstring &aname)
{
core_terminal_t::init_object(dev, aname);
analog_t::init_object(dev, aname);
net().init_object(dev.netlist(), aname + ".net");
net().register_railterminal(*this);
}
ATTR_COLD void analog_output_t::initial(const nl_double val)
{
net().as_analog().m_cur_Analog = val;
net().m_cur_Analog = val;
}
// ----------------------------------------------------------------------------------------
// netlist_param_t & friends
// param_t & friends
// ----------------------------------------------------------------------------------------
ATTR_COLD param_t::param_t(const param_type_t atype)

120
src/lib/netlist/nl_base.h
View File

@ -253,7 +253,7 @@ typedef unsigned int netlist_sig_t;
#define NETLIB_LOGIC_FAMILY(_fam) \
virtual logic_family_desc_t *default_logic_family() override \
{ \
return netlist_family_ ## _fam; \
return family_ ## _fam; \
}
@ -317,7 +317,7 @@ namespace netlist
typedef phashmap_t<pstring, pstring> model_map_t;
// -----------------------------------------------------------------------------
// netlist_output_family_t
// logic_family_t
// -----------------------------------------------------------------------------
class logic_family_desc_t
@ -351,7 +351,7 @@ namespace netlist
logic_family_desc_t *m_logic_family;
};
/* Terminals inherit the family description from the netlist_device
/* Terminals inherit the family description from the device
* The default is the ttl family, but any device can override the family.
* For individual terminals, these can be overwritten as well.
*
@ -359,12 +359,12 @@ namespace netlist
*/
extern logic_family_desc_t *netlist_family_TTL;
extern logic_family_desc_t *netlist_family_CD4XXX;
extern logic_family_desc_t *family_TTL;
extern logic_family_desc_t *family_CD4XXX;
// -----------------------------------------------------------------------------
// netlist_object_t
// object_t
// -----------------------------------------------------------------------------
class object_t
@ -443,7 +443,7 @@ namespace netlist
};
// -----------------------------------------------------------------------------
// netlist_owned_object_t
// device_object_t
// -----------------------------------------------------------------------------
class device_object_t : public object_t
@ -461,7 +461,7 @@ namespace netlist
// -----------------------------------------------------------------------------
// netlist_core_terminal_t
// core_terminal_t
// -----------------------------------------------------------------------------
class core_terminal_t : public device_object_t, public plinkedlist_element_t<core_terminal_t>
@ -485,8 +485,6 @@ namespace netlist
ATTR_COLD core_terminal_t(const type_t atype, const family_t afamily);
//ATTR_COLD void init_object(netlist_core_device_t &dev, const pstring &aname);
ATTR_COLD void set_net(net_t &anet);
ATTR_COLD void clear_net() { m_net = NULL; }
ATTR_HOT bool has_net() const { return (m_net != NULL); }
@ -514,7 +512,37 @@ namespace netlist
state_e m_state;
};
class terminal_t : public core_terminal_t
// -----------------------------------------------------------------------------
// analog_t
// -----------------------------------------------------------------------------
class analog_t : public core_terminal_t
{
public:
ATTR_COLD analog_t(const type_t atype)
: core_terminal_t(atype, ANALOG)
{
}
virtual void reset() override
{
}
ATTR_HOT inline const analog_net_t & net() const;
ATTR_HOT inline analog_net_t & net();
protected:
private:
};
// -----------------------------------------------------------------------------
// terminal_t
// -----------------------------------------------------------------------------
class terminal_t : public analog_t
{
P_PREVENT_COPYING(terminal_t)
public:
@ -527,6 +555,8 @@ namespace netlist
nl_double *m_go1; // conductance for Voltage from other term
nl_double *m_gt1; // conductance for total conductance
terminal_t *m_otherterm;
ATTR_HOT void set(const nl_double G)
{
set_ptr(m_Idr1, 0);
@ -551,8 +581,6 @@ namespace netlist
ATTR_HOT void schedule_solve();
ATTR_HOT void schedule_after(const netlist_time &after);
terminal_t *m_otherterm;
protected:
virtual void save_register() override;
@ -569,7 +597,7 @@ namespace netlist
// -----------------------------------------------------------------------------
// netlist_input_t
// logic_t
// -----------------------------------------------------------------------------
class logic_t : public core_terminal_t, public logic_family_t
@ -583,6 +611,10 @@ namespace netlist
{
}
virtual void reset() override
{
}
ATTR_COLD bool has_proxy() const { return (m_proxy != NULL); }
ATTR_COLD devices::nld_base_proxy *get_proxy() const { return m_proxy; }
ATTR_COLD void set_proxy(devices::nld_base_proxy *proxy) { m_proxy = proxy; }
@ -593,23 +625,8 @@ namespace netlist
devices::nld_base_proxy *m_proxy;
};
class netlist_analog_t : public core_terminal_t
{
public:
ATTR_COLD netlist_analog_t(const type_t atype)
: core_terminal_t(atype, ANALOG)
{
}
protected:
private:
};
// -----------------------------------------------------------------------------
// netlist_logic_input_t
// logic_input_t
// -----------------------------------------------------------------------------
class logic_input_t : public logic_t
@ -632,21 +649,21 @@ namespace netlist
protected:
virtual void reset() override
{
//netlist_core_terminal_t::reset();
logic_t::reset();
set_state(STATE_INP_ACTIVE);
}
};
// -----------------------------------------------------------------------------
// netlist_analog_input_t
// analog_input_t
// -----------------------------------------------------------------------------
class analog_input_t : public netlist_analog_t
class analog_input_t : public analog_t
{
public:
ATTR_COLD analog_input_t()
: netlist_analog_t(INPUT)
: analog_t(INPUT)
{
set_state(STATE_INP_ACTIVE);
}
@ -656,7 +673,7 @@ namespace netlist
protected:
virtual void reset() override
{
//netlist_core_terminal_t::reset();
analog_t::reset();
set_state(STATE_INP_ACTIVE);
}
};
@ -815,7 +832,7 @@ namespace netlist
ATTR_COLD analog_net_t();
virtual ~analog_net_t() { };
ATTR_HOT nl_double Q_Analog() const
ATTR_HOT const nl_double &Q_Analog() const
{
return m_cur_Analog;
}
@ -827,8 +844,8 @@ namespace netlist
ATTR_HOT devices::matrix_solver_t *solver() { return m_solver; }
ATTR_COLD bool already_processed(list_t *groups, int cur_group);
ATTR_COLD void process_net(list_t *groups, int &cur_group);
ATTR_COLD bool already_processed(pvector_t<list_t> &groups);
ATTR_COLD void process_net(pvector_t<list_t> &groups);
protected:
@ -874,7 +891,7 @@ namespace netlist
logic_net_t m_my_net;
};
class analog_output_t : public netlist_analog_t
class analog_output_t : public analog_t
{
P_PREVENT_COPYING(analog_output_t)
public:
@ -1065,7 +1082,7 @@ namespace netlist
virtual void stop() { } \
virtual logic_family_desc_t *default_logic_family()
{
return netlist_family_TTL;
return family_TTL;
}
private:
@ -1128,7 +1145,7 @@ namespace netlist
// -----------------------------------------------------------------------------
// netlist_queue_t
// queue_t
// -----------------------------------------------------------------------------
class queue_t : public timed_queue<net_t *, netlist_time>,
@ -1154,7 +1171,7 @@ namespace netlist
};
// -----------------------------------------------------------------------------
// netlist_base_t
// netlist_t
// -----------------------------------------------------------------------------
@ -1245,10 +1262,7 @@ namespace netlist
protected:
// any derived netlist must override vlog inherited from plog_base
// virtual void vlog(const plog_level &l, const pstring &ls) = 0;
/* from netlist_object */
/* from object */
virtual void reset() override;
virtual void save_register() override;
@ -1382,6 +1396,16 @@ namespace netlist
}
}
ATTR_HOT inline const analog_net_t & analog_t::net() const
{
return core_terminal_t::net().as_analog();
}
ATTR_HOT inline analog_net_t & analog_t::net()
{
return core_terminal_t::net().as_analog();
}
ATTR_HOT inline netlist_sig_t logic_input_t::Q() const
{
@ -1395,9 +1419,9 @@ namespace netlist
ATTR_HOT inline void analog_output_t::set_Q(const nl_double newQ)
{
if (newQ != net().as_analog().m_cur_Analog)
if (newQ != net().Q_Analog())
{
net().as_analog().m_cur_Analog = newQ;
net().m_cur_Analog = newQ;
net().push_to_queue(NLTIME_FROM_NS(1));
}
}

21
src/lib/netlist/nl_setup.cpp
View File

@ -598,9 +598,6 @@ void setup_t::connect_terminal_output(terminal_t &in, core_terminal_t &out)
void setup_t::connect_terminals(core_terminal_t &t1, core_terminal_t &t2)
{
//nl_assert(in.isType(netlist_terminal_t::TERMINAL));
//nl_assert(out.isType(netlist_terminal_t::TERMINAL));
if (t1.has_net() && t2.has_net())
{
log().debug("T2 and T1 have net\n");
@ -621,7 +618,6 @@ void setup_t::connect_terminals(core_terminal_t &t1, core_terminal_t &t2)
log().debug("adding net ...\n");
analog_net_t *anet = palloc(analog_net_t);
t1.set_net(*anet);
//m_netlist.solver()->m_nets.add(anet);
// FIXME: Nets should have a unique name
t1.net().init_object(netlist(),"net." + t1.name() );
t1.net().register_con(t2);
@ -651,8 +647,7 @@ bool setup_t::connect_input_input(core_terminal_t &t1, core_terminal_t &t2)
{
for (core_terminal_t *t : t1.net().m_core_terms)
{
if (t->isType(core_terminal_t::TERMINAL)
/*|| t1.net().m_core_terms[i]->isType(netlist_core_terminal_t::OUTPUT)*/)
if (t->isType(core_terminal_t::TERMINAL))
ret = connect(t2, *t);
if (ret)
break;
@ -667,8 +662,7 @@ bool setup_t::connect_input_input(core_terminal_t &t1, core_terminal_t &t2)
{
for (core_terminal_t *t : t2.net().m_core_terms)
{
if (t->isType(core_terminal_t::TERMINAL)
/*|| t2.net().m_core_terms[i]->isType(netlist_core_terminal_t::OUTPUT)*/)
if (t->isType(core_terminal_t::TERMINAL))
ret = connect(t1, *t);
if (ret)
break;
@ -793,11 +787,12 @@ void setup_t::resolve_inputs()
for (std::size_t i = 0; i < m_terminals.size(); i++)
{
core_terminal_t *term = m_terminals.value_at(i);
if (!term->has_net())
if (!term->has_net() && dynamic_cast< devices::NETLIB_NAME(dummy_input) *>(&term->device()) != NULL)
log().warning("Found dummy terminal {1} without connections", term->name());
else if (!term->has_net())
errstr += pfmt("Found terminal {1} without a net\n")(term->name());
else if (term->net().num_cons() == 0)
log().warning("Found terminal {1} without connections",
term->name());
log().warning("Found terminal {1} without connections", term->name());
}
if (errstr != "")
log().fatal("{1}", errstr);
@ -885,9 +880,9 @@ logic_family_desc_t *setup_t::family_from_model(const pstring &model)
model_parse(model, map);
if (setup_t::model_value_str(map, "TYPE") == "TTL")
return netlist_family_TTL;
return family_TTL;
if (setup_t::model_value_str(map, "TYPE") == "CD4XXX")
return netlist_family_CD4XXX;
return family_CD4XXX;
logic_family_std_proxy_t *ret = palloc(logic_family_std_proxy_t);

1
src/lib/netlist/plib/plists.h
View File

@ -467,7 +467,6 @@ public:
struct element_t
{
element_t() { }
element_t(const K &key, const H &hash, const V &value)
: m_key(key), m_hash(hash), m_value(value), m_next(-1)
{}

22
src/lib/netlist/solver/nld_ms_direct.h
View File

@ -11,6 +11,7 @@
#include <algorithm>
#include "solver/nld_solver.h"
#include "solver/vector_base.h"
NETLIB_NAMESPACE_DEVICES_START()
@ -105,7 +106,7 @@ ATTR_HOT nl_double matrix_solver_direct_t<m_N, _storage_N>::compute_next_timeste
{
analog_net_t *n = m_nets[k];
const nl_double DD_n = (n->m_cur_Analog - m_last_V[k]);
const nl_double DD_n = (n->Q_Analog() - m_last_V[k]);
const nl_double hn = current_timestep();
nl_double DD2 = (DD_n / hn - n->m_DD_n_m_1 / n->m_h_n_m_1) / (hn + n->m_h_n_m_1);
@ -409,8 +410,13 @@ ATTR_HOT void matrix_solver_direct_t<m_N, _storage_N>::LE_solve()
const nl_double f1 = - A(j,i) * f;
if (f1 != NL_FCONST(0.0))
{
for (unsigned k = i+1; k < kN; k++)
A(j,k) += A(i,k) * f1;
nl_double * RESTRICT pi = &m_A[i][i+1];
nl_double * RESTRICT pj = &m_A[j][i+1];
vec_add_mult_scalar(kN-i-1,pj,f1,pi);
//for (unsigned k = i+1; k < kN; k++)
// pj[k] = pj[k] + pi[k] * f1;
//for (unsigned k = i+1; k < kN; k++)
//A(j,k) += A(i,k) * f1;
m_RHS[j] += m_RHS[i] * f1;
}
}
@ -430,10 +436,14 @@ ATTR_HOT void matrix_solver_direct_t<m_N, _storage_N>::LE_solve()
{
const unsigned j = pb[jb];
const nl_double f1 = - A(j,i) * f;
#if 0
nl_double * RESTRICT pi = &m_A[i][i+1];
nl_double * RESTRICT pj = &m_A[j][i+1];
vec_add_mult_scalar(kN-i-1,pi,f1,pj);
#else
for (unsigned k = 0; k < e; k++)
{
A(j,p[k]) += A(i,p[k]) * f1;
}
#endif
m_RHS[j] += m_RHS[i] * f1;
}
}
@ -577,6 +587,8 @@ ATTR_HOT inline int matrix_solver_direct_t<m_N, _storage_N>::vsolve_non_dynamic(
this->LE_solve();
this->m_stat_calculations++;
return this->solve_non_dynamic(newton_raphson);
}

2
src/lib/netlist/solver/nld_ms_direct1.h
View File

@ -45,7 +45,7 @@ ATTR_HOT inline int matrix_solver_direct1_t::vsolve_non_dynamic(ATTR_UNUSED cons
nl_double new_val = m_RHS[0] / A(0,0);
nl_double e = (new_val - net->m_cur_Analog);
nl_double e = (new_val - net->Q_Analog());
nl_double cerr = nl_math::abs(e);
net->m_cur_Analog = new_val;

2
src/lib/netlist/solver/nld_ms_direct_lu.h
View File

@ -185,7 +185,7 @@ ATTR_HOT nl_double matrix_solver_direct_t<m_N, _storage_N>::compute_next_timeste
{
analog_net_t *n = m_nets[k];
const nl_double DD_n = (n->m_cur_Analog - m_last_V[k]);
const nl_double DD_n = (n->Q_Analog() - m_last_V[k]);
const nl_double hn = current_timestep();
nl_double DD2 = (DD_n / hn - n->m_DD_n_m_1 / n->m_h_n_m_1) / (hn + n->m_h_n_m_1);

4
src/lib/netlist/solver/nld_ms_sor.h
View File

@ -135,7 +135,6 @@ ATTR_HOT inline int matrix_solver_SOR_t<m_N, _storage_N>::vsolve_non_dynamic(con
/* uncommenting the line below will force dynamic updates every X iterations
* althought the system has not converged yet. This is a proof of concept,
* 91glub
*
*/
const bool interleaved_dynamic_updates = false;
@ -168,7 +167,6 @@ ATTR_HOT inline int matrix_solver_SOR_t<m_N, _storage_N>::vsolve_non_dynamic(con
} while (resched && ((!interleaved_dynamic_updates && resched_cnt < this->m_params.m_gs_loops) || (interleaved_dynamic_updates && resched_cnt < 5 )));
this->m_iterative_total += resched_cnt;
this->m_stat_calculations++;
if (resched && !interleaved_dynamic_updates)
{
@ -177,6 +175,8 @@ ATTR_HOT inline int matrix_solver_SOR_t<m_N, _storage_N>::vsolve_non_dynamic(con
return matrix_solver_direct_t<m_N, _storage_N>::vsolve_non_dynamic(newton_raphson);
}
this->m_stat_calculations++;
if (interleaved_dynamic_updates)
{
for (unsigned k = 0; k < iN; k++)

2
src/lib/netlist/solver/nld_ms_sor_mat.h
View File

@ -95,7 +95,7 @@ ATTR_HOT nl_double matrix_solver_SOR_mat_t<m_N, _storage_N>::vsolve()
for (unsigned k = 0; k < this->N(); k++)
{
const analog_net_t *n = this->m_nets[k];
const nl_double nv = (n->m_cur_Analog - this->m_last_V[k]) * rez_cts ;
const nl_double nv = (n->Q_Analog() - this->m_last_V[k]) * rez_cts ;
sq += nv * nv;
sqo += this->m_Vdelta[k] * this->m_Vdelta[k];
this->m_Vdelta[k] = nv;

43
src/lib/netlist/solver/nld_solver.cpp
View File

@ -12,6 +12,9 @@
#if 0
#pragma GCC optimize "-ffast-math"
#pragma GCC optimize "-fstrict-aliasing"
#pragma GCC optimize "-ftree-vectorizer-verbose=2"
#pragma GCC optimize "-fopt-info-vec"
#pragma GCC optimize "-fopt-info-vec-missed"
//#pragma GCC optimize "-ftree-parallelize-loops=4"
#pragma GCC optimize "-funroll-loops"
#pragma GCC optimize "-funswitch-loops"
@ -79,7 +82,7 @@ ATTR_COLD void terms_t::set_pointers()
m_term[i]->m_gt1 = &m_gt[i];
m_term[i]->m_go1 = &m_go[i];
m_term[i]->m_Idr1 = &m_Idr[i];
m_other_curanalog[i] = &m_term[i]->m_otherterm->net().as_analog().m_cur_Analog;
m_other_curanalog[i] = &m_term[i]->m_otherterm->net().m_cur_Analog;
}
}
@ -188,7 +191,7 @@ ATTR_HOT void matrix_solver_t::update_inputs()
{
// avoid recursive calls. Inputs are updated outside this call
for (std::size_t i=0; i<m_inps.size(); i++)
m_inps[i]->set_Q(m_inps[i]->m_proxied_net->m_cur_Analog);
m_inps[i]->set_Q(m_inps[i]->m_proxied_net->Q_Analog());
}
ATTR_HOT void matrix_solver_t::update_dynamic()
@ -304,7 +307,7 @@ ATTR_COLD int matrix_solver_t::get_net_idx(net_t *net)
void matrix_solver_t::log_stats()
{
if (this->m_stat_calculations != 0 && this->m_params.m_log_stats)
//if (this->m_stat_calculations != 0 && this->m_params.m_log_stats)
{
log().verbose("==============================================");
log().verbose("Solver {1}", this->name());
@ -449,7 +452,12 @@ matrix_solver_t * NETLIB_NAME(solver)::create_solver(int size, const bool use_sp
{
if (pstring("SOR_MAT").equals(m_iterative_solver))
{
typedef matrix_solver_SOR_mat_t<m_N,_storage_N> solver_mat;
typedef matrix_solver_SOR_mat_t<m_N,_storage_N> solver_sor_mat;
return palloc(solver_sor_mat(&m_params, size));
}
else if (pstring("MAT").equals(m_iterative_solver))
{
typedef matrix_solver_direct_t<m_N,_storage_N> solver_mat;
return palloc(solver_mat(&m_params, size));
}
else if (pstring("SOR").equals(m_iterative_solver))
@ -478,8 +486,7 @@ matrix_solver_t * NETLIB_NAME(solver)::create_solver(int size, const bool use_sp
ATTR_COLD void NETLIB_NAME(solver)::post_start()
{
analog_net_t::list_t groups[256];
int cur_group = -1;
pvector_t<analog_net_t::list_t> groups;
const bool use_specific = true;
m_params.m_pivot = m_pivot.Value();
@ -519,20 +526,20 @@ ATTR_COLD void NETLIB_NAME(solver)::post_start()
{
netlist().log().debug(" ==> not a rail net\n");
analog_net_t *n = &net->as_analog();
if (!n->already_processed(groups, cur_group))
if (!n->already_processed(groups))
{
cur_group++;
n->process_net(groups, cur_group);
groups.push_back(analog_net_t::list_t());
n->process_net(groups);
}
}
}
// setup the solvers
netlist().log().verbose("Found {1} net groups in {2} nets\n", cur_group + 1, netlist().m_nets.size());
for (int i = 0; i <= cur_group; i++)
netlist().log().verbose("Found {1} net groups in {2} nets\n", groups.size(), netlist().m_nets.size());
for (auto & grp : groups)
{
matrix_solver_t *ms;
std::size_t net_count = groups[i].size();
std::size_t net_count = grp.size();
switch (net_count)
{
@ -613,21 +620,19 @@ ATTR_COLD void NETLIB_NAME(solver)::post_start()
register_sub(pfmt("Solver_{1}")(m_mat_solvers.size()), *ms);
ms->vsetup(groups[i]);
ms->vsetup(grp);
m_mat_solvers.push_back(ms);
netlist().log().verbose("Solver {1}", ms->name());
netlist().log().verbose(" # {1} ==> {2} nets", i, groups[i].size());
netlist().log().verbose(" ==> {2} nets", grp.size());
netlist().log().verbose(" has {1} elements", ms->is_dynamic() ? "dynamic" : "no dynamic");
netlist().log().verbose(" has {1} elements", ms->is_timestep() ? "timestep" : "no timestep");
for (std::size_t j=0; j<groups[i].size(); j++)
for (net_t *n : grp)
{
netlist().log().verbose("Net {1}: {2}", j, groups[i][j]->name());
net_t *n = groups[i][j];
for (std::size_t k = 0; k < n->m_core_terms.size(); k++)
netlist().log().verbose("Net {1}", n->name());
for (const core_terminal_t *pcore : n->m_core_terms)
{
const core_terminal_t *pcore = n->m_core_terms[k];
netlist().log().verbose(" {1}", pcore->name());
}
}

4
src/mame/audio/irem.cpp
View File

@ -419,7 +419,9 @@ NETLIST_START(kidniki_interface)
PARAM(Solver.NR_LOOPS, 300)
PARAM(Solver.GS_LOOPS, 1)
PARAM(Solver.GS_THRESHOLD, 6)
PARAM(Solver.ITERATIVE, "SOR")
//PARAM(Solver.ITERATIVE, "SOR")
//PARAM(Solver.ITERATIVE, "MAT")
PARAM(Solver.ITERATIVE, "GMRES")
PARAM(Solver.PARALLEL, 1)
PARAM(Solver.SOR_FACTOR, 1.00)
#else