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(MESS) ti99: Avoid debugger messing up the setaddress/memory access pairs. (nw)

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This commit is contained in:
Michael Zapf 2014-09-14 22:28:33 +00:00
parent 5a3c3144fc
commit 48a30d346c
4 changed files with 101 additions and 10 deletions
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50
src/emu/bus/ti99_peb/bwg.c
View File

@ -136,6 +136,9 @@ WRITE_LINE_MEMBER( snug_bwg_device::fdc_drq_w )
SETADDRESS_DBIN_MEMBER( snug_bwg_device::setaddress_dbin )
{
// Do not allow setaddress for debugger
if (space.debugger_access()) return;
// Selection login in the PAL and some circuits on the board
// Is the card being selected?
@ -180,12 +183,45 @@ SETADDRESS_DBIN_MEMBER( snug_bwg_device::setaddress_dbin )
operate_ready_line();
}
/*
Access for debugger. This is a stripped-down version of the
main methods below. We only allow ROM and RAM access.
*/
void snug_bwg_device::debug_read(offs_t offset, UINT8* value)
{
if (((offset & m_select_mask)==m_select_value) && m_selected)
{
if ((offset & 0x1c00)==0x1c00)
{
if ((offset & 0x1fe0)!=0x1fe0)
*value = m_buffer_ram[(m_ram_page<<10) | (offset & 0x03ff)];
}
else
*value = m_dsrrom[(m_rom_page<<13) | (offset & 0x1fff)];
}
}
void snug_bwg_device::debug_write(offs_t offset, UINT8 data)
{
if (((offset & m_select_mask)==m_select_value) && m_selected)
{
if (((offset & 0x1c00)==0x1c00) && ((offset & 0x1fe0)!=0x1fe0))
m_buffer_ram[(m_ram_page<<10) | (m_address & 0x03ff)] = data;
}
}
/*
Read a byte from ROM, RAM, FDC, or RTC. See setaddress_dbin for selection
logic.
*/
READ8Z_MEMBER(snug_bwg_device::readz)
{
if (space.debugger_access())
{
debug_read(offset, value);
return;
}
if (m_inDsrArea && m_selected)
{
// 010x xxxx xxxx xxxx
@ -197,7 +233,7 @@ READ8Z_MEMBER(snug_bwg_device::readz)
if (m_RTCsel)
{
// .... ..11 111x xxx0
if (!space.debugger_access()) *value = m_clock->read(space, (m_address & 0x001e) >> 1);
*value = m_clock->read(space, (m_address & 0x001e) >> 1);
if (TRACE_RW) logerror("bwg: read RTC: %04x -> %02x\n", m_address & 0xffff, *value);
}
else
@ -213,7 +249,7 @@ READ8Z_MEMBER(snug_bwg_device::readz)
// .... ..11 1111 0xx0
// Note that the value is inverted again on the board,
// so we can drop the inversion
if (!space.debugger_access()) *value = m_wd1773->gen_r((m_address >> 1)&0x03);
*value = m_wd1773->gen_r((m_address >> 1)&0x03);
if (TRACE_RW) logerror("bwg: read FDC: %04x -> %02x\n", m_address & 0xffff, *value);
if (TRACE_DATA)
{
@ -250,6 +286,12 @@ READ8Z_MEMBER(snug_bwg_device::readz)
*/
WRITE8_MEMBER(snug_bwg_device::write)
{
if (space.debugger_access())
{
debug_write(offset, data);
return;
}
if (m_inDsrArea && m_selected)
{
if (m_lastK)
@ -260,7 +302,7 @@ WRITE8_MEMBER(snug_bwg_device::write)
{
// .... ..11 111x xxx0
if (TRACE_RW) logerror("bwg: write RTC: %04x <- %02x\n", m_address & 0xffff, data);
if (!space.debugger_access()) m_clock->write(space, (m_address & 0x001e) >> 1, data);
m_clock->write(space, (m_address & 0x001e) >> 1, data);
}
else
{
@ -276,7 +318,7 @@ WRITE8_MEMBER(snug_bwg_device::write)
// Note that the value is inverted again on the board,
// so we can drop the inversion
if (TRACE_RW) logerror("bwg: write FDC: %04x <- %02x\n", m_address & 0xffff, data);
if (!space.debugger_access()) m_wd1773->gen_w((m_address >> 1)&0x03, data);
m_wd1773->gen_w((m_address >> 1)&0x03, data);
}
else
{

4
src/emu/bus/ti99_peb/bwg.h
View File

@ -54,6 +54,10 @@ protected:
private:
void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
// Debugger accessors
void debug_read(offs_t offset, UINT8* value);
void debug_write(offs_t offset, UINT8 data);
// Wait state logic
void operate_ready_line();

53
src/emu/bus/ti99_peb/hfdc.c
View File

@ -96,8 +96,8 @@ myarc_hfdc_device::myarc_hfdc_device(const machine_config &mconfig, const char *
SETADDRESS_DBIN_MEMBER( myarc_hfdc_device::setaddress_dbin )
{
// Debugger does not run safely with HFDC
// TODO: Check why debugger messes up the access (likely to happen at other locations, too)
// Do not allow setaddress for the debugger. It will mess up the
// setaddress/memory access pairs when the CPU enters wait states.
if (space.debugger_access()) return;
// Selection login in the PAL and some circuits on the board
@ -138,6 +138,41 @@ SETADDRESS_DBIN_MEMBER( myarc_hfdc_device::setaddress_dbin )
m_ROMsel = m_inDsrArea && !m_RAMsel && !((m_address & 0x0fc0)==0x0fc0);
}
/*
Access for debugger. This is a stripped-down version of the
main methods below. We only allow ROM and RAM access.
*/
void myarc_hfdc_device::debug_read(offs_t offset, UINT8* value)
{
if (((offset & m_select_mask)==m_select_value) && m_selected)
{
if ((offset & 0x1000)==RAM_ADDR)
{
int bank = (offset & 0x0c00) >> 10;
*value = m_buffer_ram[(m_ram_page[bank]<<10) | (offset & 0x03ff)];
}
else
{
if ((offset & 0x0fc0)!=0x0fc0)
{
*value = m_dsrrom[(m_rom_page << 12) | (offset & 0x0fff)];
}
}
}
}
void myarc_hfdc_device::debug_write(offs_t offset, UINT8 data)
{
if (((offset & m_select_mask)==m_select_value) && m_selected)
{
if ((offset & 0x1000)==RAM_ADDR)
{
int bank = (offset & 0x0c00) >> 10;
m_buffer_ram[(m_ram_page[bank]<<10) | (m_address & 0x03ff)] = data;
}
}
}
/*
Read a byte from the memory address space of the HFDC
@ -155,8 +190,11 @@ SETADDRESS_DBIN_MEMBER( myarc_hfdc_device::setaddress_dbin )
*/
READ8Z_MEMBER(myarc_hfdc_device::readz)
{
// Debugger does not run safely with HFDC
if (space.debugger_access()) return;
if (space.debugger_access())
{
debug_read(offset, value);
return;
}
if (m_inDsrArea && m_selected)
{
@ -229,8 +267,11 @@ READ8Z_MEMBER(myarc_hfdc_device::readz)
*/
WRITE8_MEMBER( myarc_hfdc_device::write )
{
// Debugger does not run safely with HFDC
if (space.debugger_access()) return;
if (space.debugger_access())
{
debug_write(offset, data);
return;
}
if (m_inDsrArea && m_selected)
{

4
src/emu/bus/ti99_peb/hfdc.h
View File

@ -59,6 +59,10 @@ private:
machine_config_constructor device_mconfig_additions() const;
ioport_constructor device_input_ports() const;
// Debug accessors
void debug_read(offs_t offset, UINT8* value);
void debug_write(offs_t offset, UINT8 data);
// Callback for the index hole
void floppy_index_callback(floppy_image_device *floppy, int state);