Add disassembler and skeleton device for DP8344 Biphase Communications Processor

scripts/src/cpu.lua

@@ -2897,3 +2897,20 @@ if (CPUS["RII"]~=null or _OPTIONS["with-tools"]) then
 	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/rii/riidasm.cpp")
 	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/rii/riidasm.h")
 end
+
+--------------------------------------------------
+-- National Semiconductor BCP
+--@src/devices/cpu/bcp/dp8344.h,CPUS["BCP"] = true
+--------------------------------------------------
+
+if (CPUS["BCP"]~=null) then
+	files {
+		MAME_DIR .. "src/devices/cpu/bcp/dp8344.cpp",
+		MAME_DIR .. "src/devices/cpu/bcp/dp8344.h",
+	}
+end
+
+if (CPUS["BCP"]~=null or _OPTIONS["with-tools"]) then
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/bcp/bcpdasm.cpp")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/bcp/bcpdasm.h")
+end

scripts/target/mame/arcade.lua

@@ -135,6 +135,7 @@ CPUS["ST62XX"] = true
 CPUS["DSPP"] = true
 CPUS["HPC"] = true
 --CPUS["RII"] = true
+--CPUS["BCP"] = true
 
 --------------------------------------------------
 -- specify available sound cores

scripts/target/mame/mess.lua

@@ -143,6 +143,7 @@ CPUS["HPC"] = true
 CPUS["MEG"] = true
 CPUS["DSPV"] = true
 CPUS["RII"] = true
+CPUS["BCP"] = true
 
 --------------------------------------------------
 -- specify available sound cores; some of these are

src/devices/cpu/bcp/bcpdasm.cpp

@@ -0,0 +1,475 @@
+// license:BSD-3-Clause
+// copyright-holders:AJR
+/***************************************************************************
+
+    National Semiconductor DP8344 BCP disassembler
+
+***************************************************************************/
+
+#include "util/disasmintf.h"
+#include "bcpdasm.h"
+
+#include "util/strformat.h"
+
+using osd::u32;
+using util::BIT;
+using offs_t = u32;
+
+
+//**************************************************************************
+//  BCP DISASSEMBLER
+//**************************************************************************
+
+dp8344_disassembler::dp8344_disassembler()
+	: util::disasm_interface()
+{
+}
+
+u32 dp8344_disassembler::opcode_alignment() const
+{
+	return 1;
+}
+
+const char *dp8344_disassembler::cc_to_string(u8 f, bool s) const
+{
+	// f = 0, s = 1: Zero or EQual
+	// f = 0, s = 0: Not Zero or Not EQual
+	// f = 1, s = 1: Carry
+	// f = 1, s = 0: No Carry
+	// f = 2, s = 1: Overflow
+	// f = 2, s = 0: No Overflow
+	// f = 3, s = 1: Negative
+	// f = 3, s = 0: Positive
+	// f = 4, s = 1: Receiver Active
+	// f = 4, s = 0: Not Receiver Active
+	// f = 5, s = 1: Receiver Error
+	// f = 5, s = 0: No Receiver Error
+	// f = 6, s = 1: Data Available
+	// f = 6, s = 0: No Data Available
+	// f = 7, s = 1: Transmitter FIFO Full
+	// f = 7, s = 0: Transmitter FIFO Not Full
+
+	return std::array<const char *, 16> {
+		"nz", "nc", "nv", "p", "nra", "nre", "ndav", "ntss",
+		"z", "c", "v", "n", "ra", "re", "dav", "tss"
+	}[f | (s ? 8 : 0)];
+}
+
+const char *dp8344_disassembler::aop_to_string(u8 o) const
+{
+	return std::array<const char *, 8> {
+		"adda", "adca", "suba", "sbca", "anda", "ora", "xora", "move"
+	}[o];
+}
+
+void dp8344_disassembler::format_number(std::ostream &stream, u8 n) const
+{
+	if (n >= 0xa0)
+		stream << "0";
+	util::stream_format(stream, "%02Xh", n);
+}
+
+void dp8344_disassembler::format_address(std::ostream &stream, u16 nn) const
+{
+	if (nn >= 0xa000)
+		stream << "0";
+	util::stream_format(stream, "%04Xh", nn);
+}
+
+void dp8344_disassembler::format_register(std::ostream &stream, u8 r) const
+{
+	stream << std::array<const char *, 32> {
+		"CCR/DCR", "NCF/IBR", "ICR/ATR", "ACR/FBR",
+		"GP0/RTR", "GP1/TSR", "GP2/TCR", "GP3/TMR",
+		"GP4/GP4'", "GP5/GP5'", "GP6/GP6'", "GP7/GP7'",
+		"IWLO", "IWHI", "IXLO", "IXHI",
+		"IYLO", "IYHI", "IZLO", "IZHI",
+		"GP8", "GP9", "GP10", "GP11",
+		"GP12", "GP13", "GP14", "GP15",
+		"TRL", "TRH", "ISP", "DS"
+	}[r];
+}
+
+void dp8344_disassembler::format_modified_index_register(std::ostream &stream, u8 ir, u8 m) const
+{
+	if (m == 3)
+		stream << "+";
+	util::stream_format(stream, "I%c", 'W' + ir);
+	if (m == 0)
+		stream << "-";
+	else if (m == 2)
+		stream << "+";
+}
+
+void dp8344_disassembler::format_interrupt_vector(std::ostream &stream, u8 v) const
+{
+	switch (v)
+	{
+	case 0x1c:
+		stream << "NMI";
+		break;
+
+	case 0x04:
+		stream << "RFF/DA/RA";
+		break;
+
+	case 0x08:
+		stream << "TFE";
+		break;
+
+	case 0x0c:
+		stream << "LTE";
+		break;
+
+	case 0x10:
+		stream << "BIRQ";
+		break;
+
+	case 0x14:
+		stream << "TO";
+		break;
+
+	default:
+		format_number(stream, v);
+		break;
+	}
+}
+
+offs_t dp8344_disassembler::disassemble(std::ostream &stream, offs_t pc, const dp8344_disassembler::data_buffer &opcodes, const dp8344_disassembler::data_buffer &params)
+{
+	u16 inst = opcodes.r16(pc);
+	offs_t words = 1;
+
+	switch (inst & 0xf000)
+	{
+	case 0x0000:
+		// 0000-0FFF: ADD n,rsd (2 T-states)
+		util::stream_format(stream, "%-8s", "add");
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		stream << ",";
+		format_register(stream, inst & 0x000f);
+		break;
+
+	case 0x1000:
+		// 1000-1FFF: MOVE rs,[IZ+n] (3 T-states)
+		util::stream_format(stream, "%-8s", "move");
+		format_register(stream, inst & 0x000f);
+		stream << ",[IZ+";
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		stream << "]";
+		break;
+
+	case 0x2000:
+		// 2000-2FFF: SUB n,rsd (2 T-states)
+		util::stream_format(stream, "%-8s", "sub");
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		stream << ",";
+		format_register(stream, inst & 0x000f);
+		break;
+
+	case 0x3000:
+		// 3000-3FFF: CMP rs,n (2 T-states)
+		util::stream_format(stream, "%-8s", "cmp");
+		format_register(stream, inst & 0x000f);
+		stream << ",";
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		break;
+
+	case 0x4000:
+		// 4000-4FFF: AND n,rsd (2 T-states)
+		util::stream_format(stream, "%-8s", "and");
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		stream << ",";
+		format_register(stream, inst & 0x000f);
+		break;
+
+	case 0x5000:
+		// 5000-5FFF: OR n,rsd (2 T-states)
+		util::stream_format(stream, "%-8s", "or");
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		stream << ",";
+		format_register(stream, inst & 0x000f);
+		break;
+
+	case 0x6000:
+		// 6000-6FFF: XOR n,rsd (2 T-states)
+		util::stream_format(stream, "%-8s", "xor");
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		stream << ",";
+		format_register(stream, inst & 0x000f);
+		break;
+
+	case 0x7000:
+		// 7000-7FFF: BIT rs,n (2 T-states)
+		util::stream_format(stream, "%-8s", "bit");
+		format_register(stream, inst & 0x000f);
+		stream << ",";
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		break;
+
+	case 0x8000:
+		if (!BIT(inst, 11))
+		{
+			// 8000-87FF: JRMK Rs,b,m (4 T-states)
+			util::stream_format(stream, "%-8s", "jrmk");
+			format_register(stream, inst & 0x001f);
+			util::stream_format(stream, ",%d,%d", (inst & 0x00e0) >> 5, (inst & 0x0700) >> 8);
+		}
+		else if (!BIT(inst, 10))
+		{
+			// 8800-8BFF: MOVE n,[Ir] (3 T-states)
+			util::stream_format(stream, "%-8s", "move");
+			format_number(stream, (inst & 0x0380) >> 2 | (inst & 0x001f));
+			util::stream_format(stream, ",[I%c]", 'W' + ((inst & 0x0060) >> 5));
+		}
+		else
+		{
+			words = 2;
+			if (!BIT(inst, 9))
+			{
+				// 8C00-8DFF, 0000-FFFF: LJMP Rs,p,s,nn (2 + 2 T-states)
+				util::stream_format(stream, "%-8s", "ljmp");
+			}
+			else
+			{
+				// 8E00-8FFF, 0000-FFFF: LCALL Rs,p,s,nn (2 + 2 T-states)
+				util::stream_format(stream, "%-8s", "lcall");
+				words |= STEP_OVER;
+			}
+			format_register(stream, inst & 0x001f);
+			util::stream_format(stream, ",%d,%d,", (inst & 0x00e0) >> 5, BIT(inst, 8));
+			format_address(stream, opcodes.r16(pc + 1));
+		}
+		break;
+
+	case 0x9000:
+		// 9000-9FFF: MOVE [IZ+n],rd (3 T-states)
+		util::stream_format(stream, "%-8s[IZ+", "move");
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		stream << "],";
+		format_register(stream, inst & 0x000f);
+		break;
+
+	case 0xa000:
+	{
+		if (inst < 0xae00)
+		{
+			// A000-A1FF: ADDA Rs,[mIr] (3 T-states)
+			// A200-A3FF: ADCA Rs,[mIr] (3 T-states)
+			// A400-A5FF: SUBA Rs,[mIr] (3 T-states)
+			// A600-A7FF: SBCA Rs,[mIr] (3 T-states)
+			// A800-A9FF: ANDA Rs,[mIr] (3 T-states)
+			// AA00-ABFF: ORA  Rs,[mIr] (3 T-states)
+			// AC00-ADFF: XORA Rs,[mIr] (3 T-states)
+			util::stream_format(stream, "%-8s", aop_to_string((inst & 0x0e00) >> 9));
+			format_register(stream, inst & 0x001f);
+			stream << ",";
+			format_modified_index_register(stream, (inst & 0x0060) >> 5, (inst & 0x0180) >> 7);
+		}
+		else if (!BIT(inst, 8))
+		{
+			if (!BIT(inst, 7))
+			{
+				// AE00-AE1F: CPL Rsd (2 T-states)
+				util::stream_format(stream, "%-8s", "cpl");
+				format_register(stream, inst & 0x001f);
+			}
+			else
+			{
+				// AE80-AEF8: EXX ba,bb{,g} (2 T-states)
+				util::stream_format(stream, "%-8s%cA,%cB", "exx", BIT(inst, 4) ? 'A' : 'M', BIT(inst, 3) ? 'A' : 'M');
+				switch (inst & 0x0060)
+				{
+				case 0x0000: // NCHG
+					break;
+
+				case 0x0020:
+					stream << ",RI";
+					break;
+
+				case 0x0040:
+					stream << ",EI";
+					break;
+
+				case 0x0060:
+					stream << ",DI";
+					break;
+				}
+			}
+		}
+		else
+		{
+			// AF00-A7FF: RETF f,s{,{g}{,rf}} (2 or 3 T-states)
+			// AF80-AFF0: RET  {g{,rf}} (2 T-states)
+			if (!BIT(inst, 7))
+				util::stream_format(stream, (inst & 0x0070) == 0 ? "r%s" : "r%-7s", cc_to_string(inst & 0x0007, BIT(inst, 3)));
+			else
+				util::stream_format(stream, (inst & 0x0070) == 0 ? "%s" : "%-8s", "ret");
+
+			switch (inst & 0x0060)
+			{
+			case 0x0000:
+				if (BIT(inst, 4))
+					stream << "NCHG";
+				break;
+
+			case 0x0020:
+				stream << "RI";
+				break;
+
+			case 0x0040:
+				stream << "EI";
+				break;
+
+			case 0x0060:
+				stream << "DI";
+				break;
+			}
+			if (BIT(inst, 4))
+				stream << ",RF";
+
+			words |= STEP_OUT;
+		}
+		break;
+	}
+
+	case 0xb000:
+		// B000-BFFF: MOVE n,rd (2 T-states)
+		util::stream_format(stream, "%-8s", "move");
+		format_number(stream, (inst & 0x0ff0) >> 4);
+		stream << ",";
+		format_register(stream, inst & 0x000f);
+		break;
+
+	case 0xc000:
+		switch (inst & 0xf80)
+		{
+		case 0x000: case 0x080: case 0x100: case 0x180:
+			// C000-C1FF: MOVE [mIr],Rd (3 T-states)
+			util::stream_format(stream, "%-8s[", "move");
+			format_modified_index_register(stream, (inst & 0x0060) >> 5, (inst & 0x0180) >> 7);
+			stream << "],";
+			format_register(stream, inst & 0x001f);
+			break;
+
+		case 0x200: case 0x280: case 0x300: case 0x380:
+			// C200-C3FF: MOVE Rs,[mIr] (3 T-states)
+			util::stream_format(stream, "%-8s", "move");
+			format_register(stream, inst & 0x001f);
+			stream << ",[";
+			format_modified_index_register(stream, (inst & 0x0060) >> 5, (inst & 0x0180) >> 7);
+			stream << "]";
+			break;
+
+		case 0x400:
+			// C400-C47F: MOVE [Ir+A],Rd (3 T-states)
+			util::stream_format(stream, "%-8s[I%c+A],", "move", 'W' + ((inst & 0x0060) >> 5));
+			format_register(stream, inst & 0x001f);
+			break;
+
+		case 0x480:
+			// C480-C4FF: MOVE Rs,[Ir+A] (3 T-states)
+			util::stream_format(stream, "%-8s", "move");
+			format_register(stream, inst & 0x001f);
+			util::stream_format(stream, ",[I%c+A]", 'W' + ((inst & 0x0060) >> 5));
+			break;
+
+		case 0x800: case 0x880:
+			// C800-C8FF: SHR Rsd,b (2 T-states)
+			util::stream_format(stream, "%-8s", "shr");
+			format_register(stream, inst & 0x001f);
+			util::stream_format(stream, ",%d", (inst & 0x00e0) >> 5);
+			break;
+
+		case 0x900: case 0x980:
+			// C900-C9FF: SHL Rsd,b (2 T-states)
+			util::stream_format(stream, "%-8s", "shl");
+			format_register(stream, inst & 0x001f);
+			util::stream_format(stream, ",%d", (inst & 0x00e0) >> 5);
+			break;
+
+		case 0xa00: case 0xa80:
+			// CA00-CAFF: ROT Rsd,b (2 T-states)
+			util::stream_format(stream, "%-8s", "rot");
+			format_register(stream, inst & 0x001f);
+			util::stream_format(stream, ",%d", (inst & 0x00e0) >> 5);
+			break;
+
+		case 0xb00: case 0xb80:
+			// CB00-CBFF: JMP n (3 T-states)
+			util::stream_format(stream, "%-8s", "jmp");
+			format_address(stream, pc + 1 + s8(inst & 0x00ff));
+			break;
+
+		case 0xc00: case 0xc80:
+			// CC00-CCFF: CALL n (3 T-states)
+			util::stream_format(stream, "%-8s", "call");
+			format_address(stream, pc + 1 + s8(inst & 0x00ff));
+			words |= STEP_OVER;
+			break;
+
+		case 0xd00:
+			// CD00-DC60: LJMP [Ir] (2 T-states)
+			util::stream_format(stream, "%-8s[I%c]", "ljmp", 'W' + ((inst & 0x0060) >> 5));
+			break;
+
+		case 0xd80:
+			// CD80-CD9F: JMP Rs (4 T-states)
+			util::stream_format(stream, "%-8s", "jmp");
+			format_register(stream, inst & 0x001f);
+			break;
+
+		case 0xe00:
+			// CE00: LJMP nn (2 + 2 T-states)
+			util::stream_format(stream, "%-8s", "ljmp");
+			format_address(stream, opcodes.r16(pc + 1));
+			words = 2;
+			break;
+
+		case 0xe80:
+			// CE80: LCALL nn (2 + 2 T-states)
+			util::stream_format(stream, "%-8s", "lcall");
+			format_address(stream, opcodes.r16(pc + 1));
+			words = 2 | STEP_OVER;
+			break;
+
+		case 0xf80:
+			// CF80-CFFF: TRAP v{,g'} (2 T-states)
+			util::stream_format(stream, "%-8s", "trap");
+			format_interrupt_vector(stream, inst & 0x003f);
+			if (BIT(inst, 6))
+				stream << ",DI";
+			words |= STEP_OVER;
+			break;
+
+		default:
+			// invalid
+			stream << "???";
+			break;
+		}
+		break;
+
+	case 0xd000:
+		// D000-DFFF: JMP f,s,n (2 or 3 T-states)
+		util::stream_format(stream, "j%-7s", cc_to_string((inst & 0x0700) >> 8, BIT(inst, 11)));
+		format_address(stream, pc + 1 + s8(inst & 0x00ff));
+		break;
+
+	case 0xe000: case 0xf000:
+		// E000-E3FF: ADDA Rs,Rd (2 T-states)
+		// E400-E7FF: ADCA Rs,Rd (2 T-states)
+		// E800-EBFF: SUBA Rs,Rd (2 T-states)
+		// EC00-EFFF: SBCA Rs,Rd (2 T-states)
+		// F000-F3FF: ANDA Rs,Rd (2 T-states)
+		// F400-F7FF: ORA  Rs,Rd (2 T-states)
+		// F800-FBFF: XORA Rs,Rd (2 T-states)
+		// FC00-FFFF: MOVE Rs,Rd (2 T-states)
+		util::stream_format(stream, "%-8s", aop_to_string((inst & 0x0e00) >> 9));
+		format_register(stream, inst & 0x001f);
+		stream << ",";
+		format_register(stream, (inst & 0x03e0) >> 5);
+		break;
+	}
+
+	return words | SUPPORTED;
+}

src/devices/cpu/bcp/bcpdasm.h

@@ -0,0 +1,36 @@
+// license:BSD-3-Clause
+// copyright-holders:AJR
+/***************************************************************************
+
+    National Semiconductor DP8344 BCP disassembler
+
+***************************************************************************/
+
+#ifndef MAME_CPU_BCP_BCPDASM_H
+#define MAME_CPU_BCP_BCPDASM_H 1
+
+#pragma once
+
+class dp8344_disassembler : public util::disasm_interface
+{
+public:
+	// construction/destruction
+	dp8344_disassembler();
+
+protected:
+	// disassembler overrides
+	virtual u32 opcode_alignment() const override;
+	virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params) override;
+
+private:
+	// internal helpers
+	const char *cc_to_string(u8 f, bool s) const;
+	const char *aop_to_string(u8 o) const;
+	void format_number(std::ostream &stream, u8 n) const;
+	void format_address(std::ostream &stream, u16 nn) const;
+	void format_register(std::ostream &stream, u8 r) const;
+	void format_modified_index_register(std::ostream &stream, u8 ir, u8 m) const;
+	void format_interrupt_vector(std::ostream &stream, u8 v) const;
+};
+
+#endif // MAME_CPU_BCP_BCPDASM_H

src/devices/cpu/bcp/dp8344.h

@@ -0,0 +1,187 @@
+// license:BSD-3-Clause
+// copyright-holders:AJR
+/**********************************************************************
+
+    National Semiconductor DP8344 Biphase Communications Processor
+
+**********************************************************************/
+
+#ifndef MAME_CPU_BCP_DP8344_H
+#define MAME_CPU_BCP_DP8344_H 1
+
+#pragma once
+
+//**************************************************************************
+//  TYPE DEFINITIONS
+//**************************************************************************
+
+// ======================> dp8344_device
+
+class dp8344_device : public cpu_device
+{
+public:
+	// input line enumeration
+	enum {
+		BIRQ_LINE = INPUT_LINE_IRQ0,
+		NMI_LINE = INPUT_LINE_NMI,
+		DATA_IN_LINE = BIRQ_LINE + 1,
+		X_TCLK_LINE
+	};
+
+	// register enumeration
+	enum {
+		BCP_PC,
+		BCP_CCR, BCP_NCF, BCP_ICR, BCP_ACR,
+		BCP_DCR, BCP_IBR, BCP_ATR, BCP_FBR,
+		BCP_GP0, BCP_GP1, BCP_GP2, BCP_GP3, BCP_GP4, BCP_GP5, BCP_GP6, BCP_GP7,
+		BCP_GP8, BCP_GP9, BCP_GP10, BCP_GP11, BCP_GP12, BCP_GP13, BCP_GP14, BCP_GP15,
+		BCP_ECR, BCP_TSR, BCP_TCR, BCP_TMR,
+		BCP_GP4_ALT, BCP_GP5_ALT, BCP_GP6_ALT, BCP_GP7_ALT,
+		BCP_IW, BCP_IX, BCP_IY, BCP_IZ,
+		BCP_IWLO, BCP_IXLO, BCP_IYLO, BCP_IZLO,
+		BCP_IWHI, BCP_IXHI, BCP_IYHI, BCP_IZHI,
+		BCP_TR,
+		BCP_ASP, BCP_DSP,
+		BCP_BA, BCP_BB
+	};
+
+	// construction/destruction
+	dp8344_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+	// callback configuration
+	auto birq_out_cb() { return m_birq_out_cb.bind(); }
+	auto data_out_cb() { return m_data_out_cb.bind(); }
+	auto data_dly_cb() { return m_data_dly_cb.bind(); }
+	auto tx_act_cb() { return m_tx_act_cb.bind(); }
+
+	// misc. configuration
+	void set_auto_start(bool auto_start) { m_auto_start = auto_start; }
+
+	// remote interface
+	void ric_w(u8 data);
+
+protected:
+	// device-specific overrides
+	virtual void device_resolve_objects() override;
+	virtual void device_start() override;
+	virtual void device_reset() override;
+
+	// device_execute_interface overrides
+	virtual u32 execute_min_cycles() const override { return 2; }
+	virtual u32 execute_max_cycles() const override { return 4; }
+	virtual u32 execute_input_lines() const override { return 3; }
+	virtual void execute_run() override;
+	virtual void execute_set_input(int irqline, int state) override;
+
+	// device_disasm_interface overrides
+	virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
+
+	// device_memory_interface overrides
+	virtual space_config_vector memory_space_config() const override;
+
+private:
+	// internal functions
+	bool get_flag(unsigned f) const;
+	void set_receiver_interrupt(bool state);
+	void set_transmitter_interrupt(bool state);
+	void set_line_turn_around_interrupt(bool state);
+	void set_birq_interrupt(bool state);
+	void set_timer_interrupt(bool state);
+	void set_gie(bool state);
+	void set_condition_code(u8 data);
+	void set_interrupt_control(u8 data);
+	void set_auxiliary_control(u8 data);
+	u16 get_timer_count();
+	void address_stack_push();
+	void address_stack_pop(u8 grf);
+	void set_stack_pointer(u8 data);
+	void data_stack_push(u8 data);
+	u8 data_stack_pop();
+	void transceiver_reset();
+	void transmit_fifo_push(u8 data);
+	u16 transmit_fifo_pop();
+	void transmitter_idle();
+	void receiver_active();
+	void receive_fifo_push(u8 data);
+	u8 receive_fifo_pop();
+	void set_receiver_error(u8 code);
+	u8 get_error_code();
+	void set_transceiver_mode(u8 data);
+	void clear_network_command_flag(u8 data);
+	u8 read_register(unsigned reg);
+	u8 read_accumulator() const;
+	void write_register(unsigned reg, u8 data);
+	void remote_read();
+	void remote_write();
+
+	// address spaces
+	const address_space_config m_inst_config;
+	const address_space_config m_data_config;
+	address_space *m_inst_space;
+	address_space *m_data_space;
+	memory_access_cache<1, -1, ENDIANNESS_LITTLE> *m_inst_cache;
+
+	// output callbacks
+	devcb_write_line m_birq_out_cb;
+	devcb_write_line m_data_out_cb;
+	devcb_write_line m_data_dly_cb;
+	devcb_write_line m_tx_act_cb;
+
+	// execution state
+	u16 m_pc;
+	s32 m_icount;
+	bool m_nmi_pending;
+
+	// control registers
+	u8 m_ccr;
+	u8 m_ncf;
+	u8 m_icr;
+	u8 m_acr;
+	u8 m_dcr;
+	u8 m_ibr;
+	u8 m_atr;
+	u8 m_fbr;
+	u8 m_ecr;
+	u8 m_tsr;
+	u8 m_tcr;
+	u8 m_tmr;
+
+	// general purpose registers
+	u8 m_gp_main[16];
+	u8 m_gp_alt[4];
+
+	// index registers
+	PAIR16 m_ir[4];
+
+	// timer registers
+	u16 m_tr;
+
+	// internal stacks
+	u32 m_as[12];
+	u8 m_ds[16];
+	u8 m_asp;
+	u8 m_dsp;
+
+	// bank selects
+	bool m_ba;
+	bool m_bb;
+
+	// remote interface registers
+	u8 m_ric;
+	bool m_hib;
+	bool m_auto_start;
+
+	// input lines
+	bool m_nmi_state;
+
+	// transceiver FIFOs
+	u16 m_rfifo[3];
+	u16 m_tfifo[3];
+	u8 m_rfifo_head;
+	u8 m_tfifo_head;
+};
+
+// device type declaration
+DECLARE_DEVICE_TYPE(DP8344, dp8344_device)
+
+#endif // MAME_CPU_BCP_DP8344_H

src/emu/xtal.cpp

@@ -255,6 +255,7 @@ const double XTAL::known_xtals[] = {
 	 18'480'000, /* 18.48_MHz_XTAL         Wyse WY-100 video */
 	 18'575'000, /* 18.575_MHz_XTAL        Visual 102, Visual 220 */
 	 18'720'000, /* 18.72_MHz_XTAL         Nokia MikroMikko 1 */
+	 18'867'000, /* 18.867_MHz_XTAL        Decision Data IS-482 */
 	 18'869'600, /* 18.8696_MHz_XTAL       Memorex 2178 */
 	 19'339'600, /* 19.3396_MHz_XTAL       TeleVideo TVI-955 80-column display clock */
 	 19'584'000, /* 19.584_MHz_XTAL        ADM-42 */

src/mame/drivers/is48x.cpp

@@ -8,7 +8,7 @@
 
 #include "emu.h"
 #include "cpu/i86/i186.h"
-//#include "cpu/bcp/bcp.h"
+#include "cpu/bcp/dp8344.h"
 //#include "machine/eeprompar.h"
 //#include "video/mc6845.h"
 //#include "screen.h"
@@ -19,21 +19,46 @@ public:
 	is48x_state(const machine_config &mconfig, device_type type, const char *tag)
 		: driver_device(mconfig, type, tag)
 		, m_maincpu(*this, "maincpu")
+		, m_bcp(*this, "bcp")
+		, m_bcpram(*this, "bcpram")
 	{ }
 
 	void is482(machine_config &config);
 
 private:
+	u8 bcpram_r(offs_t offset);
+	void bcpram_w(offs_t offset, u8 data);
+
 	void mem_map(address_map &map);
 	void io_map(address_map &map);
+	void bcp_inst_map(address_map &map);
+	void bcp_data_map(address_map &map);
 
 	required_device<cpu_device> m_maincpu;
+	required_device<dp8344_device> m_bcp;
+	required_shared_ptr<u16> m_bcpram;
 };
 
+u8 is48x_state::bcpram_r(offs_t offset)
+{
+	if (BIT(offset, 0))
+		return m_bcpram[offset >> 1] >> 8;
+	else
+		return m_bcpram[offset >> 1] & 0x00ff;
+}
+
+void is48x_state::bcpram_w(offs_t offset, u8 data)
+{
+	if (BIT(offset, 0))
+		m_bcpram[offset >> 1] = (m_bcpram[offset >> 1] & 0x00ff) | data << 8;
+	else
+		m_bcpram[offset >> 1] = (m_bcpram[offset >> 1] & 0xff00) | data;
+}
+
 void is48x_state::mem_map(address_map &map)
 {
 	map(0x00000, 0x07fff).ram();
-	map(0x40000, 0x47fff).ram();
+	map(0x40000, 0x47fff).rw(FUNC(is48x_state::bcpram_r), FUNC(is48x_state::bcpram_w));
 	map(0x50000, 0x51fff).ram();
 	map(0x54000, 0x55fff).ram();
 	map(0x60022, 0x60022).nopr();
@@ -50,6 +75,15 @@ void is48x_state::io_map(address_map &map)
 	map(0x8180, 0x8180).ram();
 }
 
+void is48x_state::bcp_inst_map(address_map &map)
+{
+	map(0x0000, 0x3fff).ram().share("bcpram");
+}
+
+void is48x_state::bcp_data_map(address_map &map)
+{
+}
+
 static INPUT_PORTS_START(is482)
 INPUT_PORTS_END
 
@@ -59,7 +93,9 @@ void is48x_state::is482(machine_config &config)
 	m_maincpu->set_addrmap(AS_PROGRAM, &is48x_state::mem_map);
 	m_maincpu->set_addrmap(AS_IO, &is48x_state::io_map);
 
-	//DP8344(config, "bcp", 18.867_MHz_XTAL);
+	DP8344(config, m_bcp, 18.867_MHz_XTAL);
+	m_bcp->set_addrmap(AS_PROGRAM, &is48x_state::bcp_inst_map);
+	m_bcp->set_addrmap(AS_DATA, &is48x_state::bcp_data_map);
 }
 
 ROM_START(is482) // "IS-488-A" on case

src/tools/unidasm.cpp

@@ -28,6 +28,7 @@ using util::BIT;
 #include "cpu/arm7/arm7dasm.h"
 #include "cpu/asap/asapdasm.h"
 #include "cpu/avr8/avr8dasm.h"
+#include "cpu/bcp/bcpdasm.h"
 #include "cpu/capricorn/capricorn_dasm.h"
 #include "cpu/ccpu/ccpudasm.h"
 #include "cpu/clipper/clipperd.h"
@@ -339,6 +340,7 @@ static const dasm_table_entry dasm_table[] =
 	{ "cquestlin",       be, -3, []() -> util::disasm_interface * { return new cquestlin_disassembler; } },
 	{ "cquestrot",       be, -3, []() -> util::disasm_interface * { return new cquestrot_disassembler; } },
 	{ "cquestsnd",       be, -3, []() -> util::disasm_interface * { return new cquestsnd_disassembler; } },
+	{ "dp8344",          le, -1, []() -> util::disasm_interface * { return new dp8344_disassembler; } },
 	{ "ds5002fp",        le,  0, []() -> util::disasm_interface * { return new ds5002fp_disassembler; } },
 	{ "dsp16",           le, -1, []() -> util::disasm_interface * { return new dsp16_disassembler; } },
 	{ "dsp32c",          le,  0, []() -> util::disasm_interface * { return new dsp32c_disassembler; } },