From 49121f9998690f9719cfd91daac939068a209c20 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C3=ABl=20Banaan=20Ananas?=
 <happppp@users.noreply.github.com>
Date: Wed, 5 Feb 2014 22:26:32 +0000
Subject: [PATCH] readability cleanup in opcode table

---
 src/emu/cpu/mn10200/mn10200.c | 1586 +++++++++++++++++----------------
 src/emu/cpu/mn10200/mn10200.h |    6 +-
 2 files changed, 809 insertions(+), 783 deletions(-)

diff --git a/src/emu/cpu/mn10200/mn10200.c b/src/emu/cpu/mn10200/mn10200.c
index d3f186ae318..7e94cc78294 100644
--- a/src/emu/cpu/mn10200/mn10200.c
+++ b/src/emu/cpu/mn10200/mn10200.c
@@ -49,6 +49,7 @@ mn10200_device::mn10200_device(const machine_config &mconfig, const char *tag, d
 
 UINT8 mn10200_device::read_arg8(UINT32 address)
 {
+	address &= 0xffffff;
 	if (address >= 0xfc00 && address < 0x10000)
 	{
 		return mn10200_r(address-0xfc00, MEM_BYTE);
@@ -59,6 +60,7 @@ UINT8 mn10200_device::read_arg8(UINT32 address)
 
 UINT16 mn10200_device::read_arg16(UINT32 address)
 {
+	address &= 0xffffff;
 	if (address >= 0xfc00 && address < 0x10000)
 	{
 		return mn10200_r(address-0xfc00, MEM_WORD);
@@ -74,6 +76,7 @@ UINT16 mn10200_device::read_arg16(UINT32 address)
 
 void mn10200_device::write_mem8(UINT32 address, UINT8 data)
 {
+	address &= 0xffffff;
 	if (address >= 0xfc00 && address < 0x10000)
 	{
 		mn10200_w(address-0xfc00, data, MEM_BYTE);
@@ -85,6 +88,7 @@ void mn10200_device::write_mem8(UINT32 address, UINT8 data)
 
 void mn10200_device::write_mem16(UINT32 address, UINT16 data)
 {
+	address &= 0xffffff;
 	if (address >= 0xfc00 && address < 0x10000)
 	{
 		mn10200_w(address-0xfc00, data, MEM_WORD);
@@ -101,23 +105,26 @@ void mn10200_device::write_mem16(UINT32 address, UINT16 data)
 	m_program->write_word(address, data);
 }
 
-INT32 mn10200_device::read_arg24(offs_t adr)
+UINT32 mn10200_device::read_arg24(UINT32 address)
 {
-	return read_arg16(adr)|(read_arg8(adr+2)<<16);
+	address &= 0xffffff;
+	return read_arg16(address)|(read_arg8(address+2)<<16);
 }
 
-void mn10200_device::write_mem24(offs_t adr, UINT32 val)
+void mn10200_device::write_mem24(UINT32 address, UINT32 data)
 {
+	address &= 0xffffff;
 /*  if(adr == 0x4075aa || adr == 0x40689a || adr == 0x4075a2) {
         log_write("TRACE", adr, val, MEM_LONG);
     }*/
-	write_mem8(adr, val);
-	write_mem8(adr+1, val>>8);
-	write_mem8(adr+2, val>>16);
+	write_mem8(address, data);
+	write_mem8(address+1, data>>8);
+	write_mem8(address+2, data>>16);
 }
 
 UINT8 mn10200_device::read_mem8(UINT32 address)
 {
+	address &= 0xffffff;
 	if (address >= 0xfc00 && address < 0x10000)
 	{
 		return mn10200_r(address-0xfc00, MEM_BYTE);
@@ -128,6 +135,7 @@ UINT8 mn10200_device::read_mem8(UINT32 address)
 
 UINT16 mn10200_device::read_mem16(UINT32 address)
 {
+	address &= 0xffffff;
 	if (address >= 0xfc00 && address < 0x10000)
 	{
 		return mn10200_r(address-0xfc00, MEM_WORD);
@@ -141,9 +149,10 @@ UINT16 mn10200_device::read_mem16(UINT32 address)
 	return m_program->read_word(address);
 }
 
-INT32 mn10200_device::read_mem24(offs_t adr)
+UINT32 mn10200_device::read_mem24(UINT32 address)
 {
-	return read_mem16(adr)|(read_mem8(adr+2)<<16);
+	address &= 0xffffff;
+	return read_mem16(address)|(read_mem8(address+2)<<16);
 }
 
 void mn10200_device::mn102_change_pc(UINT32 pc)
@@ -466,7 +475,7 @@ void mn10200_device::device_reset()
 
 	memset(m_d, 0, sizeof(m_d));
 	memset(m_a, 0, sizeof(m_a));
-	m_pc = 0x80000;
+	mn102_change_pc(0x80000);
 	m_psw = 0;
 	m_nmicr = 0;
 	memset(m_icrl, 0, sizeof(m_icrl));
@@ -499,23 +508,24 @@ UINT32 mn10200_device::do_add(UINT32 a, UINT32 b, UINT32 c)
 	UINT32 r = (a & 0xffffff) + (b & 0xffffff) + c;
 
 	m_psw &= 0xff00;
-	if((a^r) & (b^r) & 0x00800000)
+	if ((a^r) & (b^r) & 0x00800000)
 		m_psw |= FLAG_VX;
-	if(r & 0x01000000)
+	if (r & 0x01000000)
 		m_psw |= FLAG_CX;
-	if(r & 0x00800000)
+	if (r & 0x00800000)
 		m_psw |= FLAG_NX;
-	if((r & 0x00ffffff) == 0)
+	if ((r & 0x00ffffff) == 0)
 		m_psw |= FLAG_ZX;
-	if((a^r) & (b^r) & 0x00008000)
+	if ((a^r) & (b^r) & 0x00008000)
 		m_psw |= FLAG_VF;
 	if (((a & 0xffff) + (b & 0xffff) + c) & 0x00010000)
 		m_psw |= FLAG_CF;
-	if(r & 0x00008000)
+	if (r & 0x00008000)
 		m_psw |= FLAG_NF;
-	if((r & 0x0000ffff) == 0)
+	if ((r & 0x0000ffff) == 0)
 		m_psw |= FLAG_ZF;
-	return r & 0xffffff;
+
+	return r;
 }
 
 UINT32 mn10200_device::do_sub(UINT32 a, UINT32 b, UINT32 c)
@@ -523,23 +533,24 @@ UINT32 mn10200_device::do_sub(UINT32 a, UINT32 b, UINT32 c)
 	UINT32 r = (a & 0xffffff) - (b & 0xffffff) - c;
 
 	m_psw &= 0xff00;
-	if((a^b) & (a^r) & 0x00800000)
+	if ((a^b) & (a^r) & 0x00800000)
 		m_psw |= FLAG_VX;
-	if(r & 0x01000000)
+	if (r & 0x01000000)
 		m_psw |= FLAG_CX;
-	if(r & 0x00800000)
+	if (r & 0x00800000)
 		m_psw |= FLAG_NX;
-	if((r & 0x00ffffff) == 0)
+	if ((r & 0x00ffffff) == 0)
 		m_psw |= FLAG_ZX;
-	if((a^b) & (a^r) & 0x00008000)
+	if ((a^b) & (a^r) & 0x00008000)
 		m_psw |= FLAG_VF;
 	if (((a & 0xffff) - (b & 0xffff) - c) & 0x00010000)
 		m_psw |= FLAG_CF;
-	if(r & 0x00008000)
+	if (r & 0x00008000)
 		m_psw |= FLAG_NF;
-	if((r & 0x0000ffff) == 0)
+	if ((r & 0x0000ffff) == 0)
 		m_psw |= FLAG_ZF;
-	return r & 0xffffff;
+
+	return r;
 }
 
 void mn10200_device::test_nz16(UINT16 v)
@@ -553,7 +564,7 @@ void mn10200_device::test_nz16(UINT16 v)
 
 void mn10200_device::do_jsr(UINT32 to, UINT32 ret)
 {
-	mn102_change_pc(to & 0xffffff);
+	mn102_change_pc(to);
 	m_a[3] -= 4;
 	write_mem24(m_a[3], ret);
 }
@@ -585,199 +596,200 @@ void mn10200_device::execute_set_input(int irqnum, int state)
 
 void mn10200_device::execute_run()
 {
-	while(m_cycles > 0)
+	while (m_cycles > 0)
 	{
 		UINT8 opcode;
 
 		debugger_instruction_hook(this, m_pc);
 
 		opcode = read_arg8(m_pc);
-		switch(opcode) {
-		// mov dm, (an)
-		case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
-		case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-			m_cycles -= 1;
-			write_mem16(m_a[(opcode>>2)&3], (UINT16)m_d[opcode & 3]);
-			m_pc += 1;
-			break;
+		switch (opcode)
+		{
+			// mov dm, (an)
+			case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
+			case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+				m_cycles -= 1;
+				write_mem16(m_a[opcode >> 2 & 3], (UINT16)m_d[opcode & 3]);
+				m_pc += 1;
+				break;
 
-		// movb dm, (an)
-		case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
-		case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-			m_cycles -= 1;
-			write_mem8(m_a[(opcode>>2)&3], (UINT8)m_d[opcode & 3]); // note: typo in manual
-			m_pc += 1;
-			break;
+			// movb dm, (an)
+			case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
+			case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+				m_cycles -= 1;
+				write_mem8(m_a[opcode >> 2 & 3], (UINT8)m_d[opcode & 3]); // note: typo in manual
+				m_pc += 1;
+				break;
 
-		// mov (an), dm
-		case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
-		case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (INT16)read_mem16(m_a[(opcode>>2)&3]);
-			m_pc += 1;
-			break;
+			// mov (an), dm
+			case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+			case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+				m_cycles -= 1;
+				m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3]);
+				m_pc += 1;
+				break;
 
-		// movbu (an), dm
-		case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
-		case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
-			m_cycles -= 1;
-			m_d[opcode & 3] = read_mem8(m_a[(opcode>>2)&3]);
-			m_pc += 1;
-			break;
+			// movbu (an), dm
+			case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+			case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+				m_cycles -= 1;
+				m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3]);
+				m_pc += 1;
+				break;
 
-		// mov dm, (d8, an)
-		case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
-		case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
-			m_cycles -= 1;
-			write_mem16((m_a[(opcode>>2)&3]+(INT8)read_arg8(m_pc+1)) & 0xffffff, (UINT16)m_d[opcode & 3]);
-			m_pc += 2;
-			break;
+			// mov dm, (d8, an)
+			case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+			case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+				m_cycles -= 1;
+				write_mem16((m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 1)), m_d[opcode & 3]);
+				m_pc += 2;
+				break;
 
-		// mov am, (d8, an)
-		case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
-		case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
-			m_cycles -= 2;
-			write_mem24((m_a[(opcode>>2)&3]+(INT8)read_arg8(m_pc+1)) & 0xffffff, m_a[opcode & 3]);
-			m_pc += 2;
-			break;
+			// mov am, (d8, an)
+			case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+			case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+				m_cycles -= 2;
+				write_mem24((m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 1)), m_a[opcode & 3]);
+				m_pc += 2;
+				break;
 
-		// mov (d8, an), dm
-		case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
-		case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (INT16)read_mem16((m_a[(opcode>>2) & 3] + (INT8)read_arg8(m_pc+1)) & 0xffffff);
-			m_pc += 2;
-			break;
+			// mov (d8, an), dm
+			case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+			case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+				m_cycles -= 1;
+				m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 1));
+				m_pc += 2;
+				break;
 
-		// mov (d8, an), am
-		case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
-		case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-			m_cycles -= 2;
-			m_a[opcode & 3] = read_mem24((m_a[(opcode>>2) & 3] + (INT8)read_arg8(m_pc+1)) & 0xffffff);
-			m_pc += 2;
-			break;
+			// mov (d8, an), am
+			case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
+			case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+				m_cycles -= 2;
+				m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 1));
+				m_pc += 2;
+				break;
 
-		// mov dm, dn
-		case 0x81: case 0x82: case 0x83: case 0x84: case 0x86: case 0x87:
-		case 0x88: case 0x89: case 0x8b: case 0x8c: case 0x8d: case 0x8e:
-			m_cycles -= 1;
-			m_d[opcode & 3] = m_d[(opcode>>2) & 3];
-			m_pc += 1;
-			break;
+			// mov dm, dn
+			case 0x81: case 0x82: case 0x83: case 0x84: case 0x86: case 0x87:
+			case 0x88: case 0x89: case 0x8b: case 0x8c: case 0x8d: case 0x8e:
+				m_cycles -= 1;
+				m_d[opcode & 3] = m_d[opcode >> 2 & 3];
+				m_pc += 1;
+				break;
 
-		// mov imm8, dn
-		case 0x80: case 0x85: case 0x8a: case 0x8f:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (INT8)read_arg8(m_pc+1);
-			m_pc += 2;
-			break;
+			// mov imm8, dn
+			case 0x80: case 0x85: case 0x8a: case 0x8f:
+				m_cycles -= 1;
+				m_d[opcode & 3] = (INT8)read_arg8(m_pc + 1);
+				m_pc += 2;
+				break;
 
-		// add dn, dm
-		case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
-		case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
-			m_cycles -= 1;
-			m_d[opcode & 3] = do_add(m_d[opcode & 3], m_d[(opcode >> 2) & 3], 0);
-			m_pc += 1;
-			break;
+			// add dn, dm
+			case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+			case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+				m_cycles -= 1;
+				m_d[opcode & 3] = do_add(m_d[opcode & 3], m_d[opcode >> 2 & 3], 0);
+				m_pc += 1;
+				break;
 
-		// sub dn, dm
-		case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
-		case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
-			m_cycles -= 1;
-			m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_d[(opcode >> 2) & 3], 0);
-			m_pc += 1;
-			break;
+			// sub dn, dm
+			case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
+			case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+				m_cycles -= 1;
+				m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_d[opcode >> 2 & 3], 0);
+				m_pc += 1;
+				break;
 
-		// extx dn
-		case 0xb0: case 0xb1: case 0xb2: case 0xb3:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (INT16)m_d[opcode & 3] & 0xffffff;
-			m_pc += 1;
-			break;
+			// extx dn
+			case 0xb0: case 0xb1: case 0xb2: case 0xb3:
+				m_cycles -= 1;
+				m_d[opcode & 3] = (INT16)m_d[opcode & 3];
+				m_pc += 1;
+				break;
 
-		// extxu dn
-		case 0xb4: case 0xb5: case 0xb6: case 0xb7:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (UINT16)m_d[opcode & 3];
-			m_pc += 1;
-			break;
+			// extxu dn
+			case 0xb4: case 0xb5: case 0xb6: case 0xb7:
+				m_cycles -= 1;
+				m_d[opcode & 3] = (UINT16)m_d[opcode & 3];
+				m_pc += 1;
+				break;
 
-		// extxb dn
-		case 0xb8: case 0xb9: case 0xba: case 0xbb:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (INT8)m_d[opcode & 3] & 0xffffff;
-			m_pc += 1;
-			break;
+			// extxb dn
+			case 0xb8: case 0xb9: case 0xba: case 0xbb:
+				m_cycles -= 1;
+				m_d[opcode & 3] = (INT8)m_d[opcode & 3];
+				m_pc += 1;
+				break;
 
-		// extxbu dn
-		case 0xbc: case 0xbd: case 0xbe: case 0xbf:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (UINT8)m_d[opcode & 3];
-			m_pc += 1;
-			break;
+			// extxbu dn
+			case 0xbc: case 0xbd: case 0xbe: case 0xbf:
+				m_cycles -= 1;
+				m_d[opcode & 3] = (UINT8)m_d[opcode & 3];
+				m_pc += 1;
+				break;
 
-		// mov dn, (imm16)
-		case 0xc0: case 0xc1: case 0xc2: case 0xc3:
-			m_cycles -= 1;
-			write_mem16(read_arg16(m_pc+1), (UINT16)m_d[opcode & 3]);
-			m_pc += 3;
-			break;
+			// mov dn, (imm16)
+			case 0xc0: case 0xc1: case 0xc2: case 0xc3:
+				m_cycles -= 1;
+				write_mem16(read_arg16(m_pc + 1), m_d[opcode & 3]);
+				m_pc += 3;
+				break;
 
-		// movb dn, (imm16)
-		case 0xc4: case 0xc5: case 0xc6: case 0xc7:
-			m_cycles -= 1;
-			write_mem8(read_arg16(m_pc+1), (UINT8)m_d[opcode & 3]);
-			m_pc += 3;
-			break;
+			// movb dn, (imm16)
+			case 0xc4: case 0xc5: case 0xc6: case 0xc7:
+				m_cycles -= 1;
+				write_mem8(read_arg16(m_pc + 1), m_d[opcode & 3]);
+				m_pc += 3;
+				break;
 
-		// mov (abs16), dn
-		case 0xc8: case 0xc9: case 0xca: case 0xcb:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (INT16)read_mem16(read_arg16(m_pc+1));
-			m_pc += 3;
-			break;
+			// mov (abs16), dn
+			case 0xc8: case 0xc9: case 0xca: case 0xcb:
+				m_cycles -= 1;
+				m_d[opcode & 3] = (INT16)read_mem16(read_arg16(m_pc + 1));
+				m_pc += 3;
+				break;
 
-		// movbu (abs16), dn
-		case 0xcc: case 0xcd: case 0xce: case 0xcf:
-			m_cycles -= 1;
-			m_d[opcode & 3] = read_mem8(read_arg16(m_pc+1));
-			m_pc += 3;
-			break;
+			// movbu (abs16), dn
+			case 0xcc: case 0xcd: case 0xce: case 0xcf:
+				m_cycles -= 1;
+				m_d[opcode & 3] = read_mem8(read_arg16(m_pc + 1));
+				m_pc += 3;
+				break;
 
-		// add imm8, an
-		case 0xd0: case 0xd1: case 0xd2: case 0xd3:
-			m_cycles -= 1;
-			m_a[opcode & 3] = do_add(m_a[opcode & 3], (INT8)read_arg8(m_pc+1), 0);
-			m_pc += 2;
-			break;
+			// add imm8, an
+			case 0xd0: case 0xd1: case 0xd2: case 0xd3:
+				m_cycles -= 1;
+				m_a[opcode & 3] = do_add(m_a[opcode & 3], (INT8)read_arg8(m_pc + 1), 0);
+				m_pc += 2;
+				break;
 
-		// add imm8, dn
-		case 0xd4: case 0xd5: case 0xd6: case 0xd7:
-			m_cycles -= 1;
-			m_d[opcode & 3] = do_add(m_d[opcode & 3], (INT8)read_arg8(m_pc+1), 0);
-			m_pc += 2;
-			break;
+			// add imm8, dn
+			case 0xd4: case 0xd5: case 0xd6: case 0xd7:
+				m_cycles -= 1;
+				m_d[opcode & 3] = do_add(m_d[opcode & 3], (INT8)read_arg8(m_pc + 1), 0);
+				m_pc += 2;
+				break;
 
-		// cmp imm8, dn
-		case 0xd8: case 0xd9: case 0xda: case 0xdb:
-			m_cycles -= 1;
-			do_sub(m_d[opcode & 3], (INT8)read_arg8(m_pc+1), 0);
-			m_pc += 2;
-			break;
+			// cmp imm8, dn
+			case 0xd8: case 0xd9: case 0xda: case 0xdb:
+				m_cycles -= 1;
+				do_sub(m_d[opcode & 3], (INT8)read_arg8(m_pc + 1), 0);
+				m_pc += 2;
+				break;
 
-		// mov imm16, an
-		case 0xdc: case 0xdd: case 0xde: case 0xdf:
-			m_cycles -= 1;
-			m_a[opcode & 3] = read_arg16(m_pc+1);
-			m_pc += 3;
-			break;
+			// mov imm16, an
+			case 0xdc: case 0xdd: case 0xde: case 0xdf:
+				m_cycles -= 1;
+				m_a[opcode & 3] = read_arg16(m_pc + 1);
+				m_pc += 3;
+				break;
 
 		// blt label8
 		case 0xe0:
-			if(((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_NF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_VF)) // (VF^NF)=1
+			if (((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_NF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_VF)) // (VF^NF)=1
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -788,10 +800,10 @@ void mn10200_device::execute_run()
 
 		// bgt label8
 		case 0xe1:
-			if(((m_psw & (FLAG_ZF|FLAG_NF|FLAG_VF)) == 0) || ((m_psw & (FLAG_ZF|FLAG_NF|FLAG_VF)) == (FLAG_NF|FLAG_VF))) // ((VF^NF)|ZF)=0
+			if (((m_psw & (FLAG_ZF|FLAG_NF|FLAG_VF)) == 0) || ((m_psw & (FLAG_ZF|FLAG_NF|FLAG_VF)) == (FLAG_NF|FLAG_VF))) // ((VF^NF)|ZF)=0
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -802,10 +814,10 @@ void mn10200_device::execute_run()
 
 		// bge label8
 		case 0xe2:
-			if(((m_psw & (FLAG_NF|FLAG_VF)) == 0) || ((m_psw & (FLAG_NF|FLAG_VF)) == (FLAG_NF|FLAG_VF))) // (VF^NF)=0
+			if (((m_psw & (FLAG_NF|FLAG_VF)) == 0) || ((m_psw & (FLAG_NF|FLAG_VF)) == (FLAG_NF|FLAG_VF))) // (VF^NF)=0
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -816,10 +828,10 @@ void mn10200_device::execute_run()
 
 		// ble label8
 		case 0xe3:
-			if((m_psw & FLAG_ZF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_NF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_VF)) // ((VF^NF)|ZF)=1
+			if ((m_psw & FLAG_ZF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_NF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_VF)) // ((VF^NF)|ZF)=1
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -830,10 +842,10 @@ void mn10200_device::execute_run()
 
 		// bcs label8
 		case 0xe4:
-			if(m_psw & FLAG_CF) // CF=1
+			if (m_psw & FLAG_CF) // CF=1
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -844,10 +856,10 @@ void mn10200_device::execute_run()
 
 		// bhi label8
 		case 0xe5:
-			if(!(m_psw & (FLAG_ZF|FLAG_CF))) // (CF|ZF)=0
+			if (!(m_psw & (FLAG_ZF|FLAG_CF))) // (CF|ZF)=0
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -858,10 +870,10 @@ void mn10200_device::execute_run()
 
 		// bcc label8
 		case 0xe6:
-			if(!(m_psw & FLAG_CF)) // CF=0
+			if (!(m_psw & FLAG_CF)) // CF=0
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -872,10 +884,10 @@ void mn10200_device::execute_run()
 
 		// bls label8
 		case 0xe7:
-			if(m_psw & (FLAG_ZF|FLAG_CF)) // (CF|ZF)=1
+			if (m_psw & (FLAG_ZF|FLAG_CF)) // (CF|ZF)=1
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -886,10 +898,10 @@ void mn10200_device::execute_run()
 
 		// beq label8
 		case 0xe8:
-			if(m_psw & FLAG_ZF) // ZF=1
+			if (m_psw & FLAG_ZF) // ZF=1
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -900,10 +912,10 @@ void mn10200_device::execute_run()
 
 		// bne label8
 		case 0xe9:
-			if(!(m_psw & FLAG_ZF)) // ZF=0
+			if (!(m_psw & FLAG_ZF)) // ZF=0
 			{
 				m_cycles -= 2;
-				mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+				mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			}
 			else
 			{
@@ -915,60 +927,63 @@ void mn10200_device::execute_run()
 		// bra label8
 		case 0xea:
 			m_cycles -= 2;
-			mn102_change_pc(m_pc+2+(INT8)read_arg8(m_pc+1));
+			mn102_change_pc(m_pc + 2 + (INT8)read_arg8(m_pc + 1));
 			break;
 
 		// rti
 		case 0xeb:
 			m_cycles -= 6;
 			m_psw = read_mem16(m_a[3]);
-			mn102_change_pc(read_mem24(m_a[3]+2));
+			mn102_change_pc(read_mem24(m_a[3] + 2));
 			m_a[3] += 6;
 			break;
 
 		// cmp imm16, an
 		case 0xec: case 0xed: case 0xee: case 0xef:
 			m_cycles -= 1;
-			do_sub(m_a[opcode & 3], read_arg16(m_pc+1), 0);
+			do_sub(m_a[opcode & 3], read_arg16(m_pc + 1), 0);
 			m_pc += 3;
 			break;
 
 		// extended code f0 (2 bytes)
 		case 0xf0:
-			opcode = read_arg8(m_pc+1);
-			switch(opcode) {
+			opcode = read_arg8(m_pc + 1);
+			switch (opcode)
+			{
 				// jmp (an)
 				case 0x00: case 0x04: case 0x08: case 0x0c:
-				m_cycles -= 3;
-				mn102_change_pc(m_a[(opcode>>2) & 3]);
-				break;
+					m_cycles -= 3;
+					mn102_change_pc(m_a[opcode >> 2 & 3]);
+					break;
 
 				// jsr (an)
 				case 0x01: case 0x05: case 0x09: case 0x0d:
-				m_cycles -= 5;
-				do_jsr(m_a[(opcode>>2) & 3], m_pc+2);
-				break;
+					m_cycles -= 5;
+					do_jsr(m_a[opcode >> 2 & 3], m_pc + 2);
+					break;
 
 				// bset dm, (an)
 				case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
-				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: {
-				m_cycles -= 5;
-				UINT8 v = read_mem8(m_a[(opcode>>2) & 3]);
-				test_nz16(v & m_d[opcode & 3]);
-				write_mem8(m_a[(opcode>>2) & 3], v | m_d[opcode & 3]);
-				m_pc += 2;
-				break;
+				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+				{
+					m_cycles -= 5;
+					UINT8 v = read_mem8(m_a[opcode >> 2 & 3]);
+					test_nz16(v & m_d[opcode & 3]);
+					write_mem8(m_a[opcode >> 2 & 3], v | m_d[opcode & 3]);
+					m_pc += 2;
+					break;
 				}
 
 				// bclr dm, (an)
 				case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
-				case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f: {
-				m_cycles -= 5;
-				UINT8 v = read_mem8(m_a[(opcode>>2) & 3]);
-				test_nz16(v & m_d[opcode & 3]);
-				write_mem8(m_a[(opcode>>2) & 3], v & ~m_d[opcode & 3]);
-				m_pc += 2;
-				break;
+				case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+				{
+					m_cycles -= 5;
+					UINT8 v = read_mem8(m_a[opcode >> 2 & 3]);
+					test_nz16(v & m_d[opcode & 3]);
+					write_mem8(m_a[opcode >> 2 & 3], v & ~m_d[opcode & 3]);
+					m_pc += 2;
+					break;
 				}
 
 				// movb (di, an), dm
@@ -980,10 +995,10 @@ void mn10200_device::execute_run()
 				case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
 				case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
 				case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-				m_cycles -= 2;
-				m_d[opcode & 3] = (INT8)read_mem8((m_a[(opcode>>2) & 3] + m_d[(opcode>>4) & 3]) & 0xffffff);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
+					m_pc += 2;
+					break;
 
 				// movbu (di, an), dm
 				case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
@@ -994,10 +1009,10 @@ void mn10200_device::execute_run()
 				case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
 				case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
 				case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
-				m_cycles -= 2;
-				m_d[opcode & 3] = read_mem8((m_a[(opcode>>2) & 3] + m_d[(opcode>>4) & 3]) & 0xffffff);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
+					m_pc += 2;
+					break;
 
 				// movb dm, (di, an)
 				case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
@@ -1008,783 +1023,793 @@ void mn10200_device::execute_run()
 				case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
 				case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
 				case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
-				m_cycles -= 2;
-				write_mem8((m_a[(opcode>>2) & 3] + m_d[(opcode>>4) & 3]) & 0xffffff, m_d[opcode & 3]);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					write_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_d[opcode & 3]);
+					m_pc += 2;
+					break;
 
 				default:
-				unemul();
-				break;
+					unemul();
+					break;
 			}
 			break;
 
 		// extended code f1 (2 bytes)
 		case 0xf1:
-			opcode = read_arg8(m_pc+1);
-			switch(opcode>>6) {
+			opcode = read_arg8(m_pc + 1);
+			switch (opcode >> 6)
+			{
 				// mov (di, an), am
 				case 0:
-				m_cycles -= 3;
-				m_a[opcode & 3] = read_mem24((m_a[(opcode>>2) & 3] + m_d[(opcode>>4) & 3]) & 0xffffff);
-				m_pc += 2;
-				break;
+					m_cycles -= 3;
+					m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
+					m_pc += 2;
+					break;
 
 				// mov (di, an), dm
 				case 1:
-				m_cycles -= 2;
-				m_d[opcode & 3] = (INT16)read_mem16((m_a[(opcode>>2) & 3] + m_d[(opcode>>4) & 3]) & 0xffffff);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
+					m_pc += 2;
+					break;
 
 				// mov am, (di, an)
 				case 2:
-				m_cycles -= 3;
-				write_mem24((m_a[(opcode>>2) & 3] + m_d[(opcode>>4) & 3]) & 0xffffff, m_a[opcode & 3]);
-				m_pc += 2;
-				break;
+					m_cycles -= 3;
+					write_mem24(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_a[opcode & 3]);
+					m_pc += 2;
+					break;
 
 				// mov dm, (di, an)
 				case 3:
-				m_cycles -= 2;
-				write_mem16((m_a[(opcode>>2) & 3] + m_d[(opcode>>4) & 3]) & 0xffffff, m_d[opcode & 3]);
-				m_pc += 2;
-				break;
-				}
+					m_cycles -= 2;
+					write_mem16(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_d[opcode & 3]);
+					m_pc += 2;
+					break;
+			}
 			break;
 
 		// extended code f2 (2 bytes)
 		case 0xf2:
-			opcode = read_arg8(m_pc+1);
-			switch(opcode>>4) {
+			opcode = read_arg8(m_pc + 1);
+			switch (opcode >> 4)
+			{
 				// add dm, an
 				case 0x0:
-				m_cycles -= 2;
-				m_a[opcode & 3] = do_add(m_a[opcode & 3], m_d[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = do_add(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// sub dm, an
 				case 0x1:
-				m_cycles -= 2;
-				m_a[opcode & 3] = do_sub(m_a[opcode & 3], m_d[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = do_sub(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// cmp dm, an
 				case 0x2:
-				m_cycles -= 2;
-				do_sub(m_a[opcode & 3], m_d[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					do_sub(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// mov am, dn
 				case 0x3:
-				m_cycles -= 2;
-				m_a[opcode & 3] = m_d[(opcode>>2) & 3];
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = m_d[opcode >> 2 & 3];
+					m_pc += 2;
+					break;
 
 				// add am, an
 				case 0x4:
-				m_cycles -= 2;
-				m_a[opcode & 3] = do_add(m_a[opcode & 3], m_a[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = do_add(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// sub am, an
 				case 0x5:
-				m_cycles -= 2;
-				m_a[opcode & 3] = do_sub(m_a[opcode & 3], m_a[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = do_sub(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// cmp am, an
 				case 0x6:
-				m_cycles -= 2;
-				do_sub(m_a[opcode & 3], m_a[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					do_sub(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// mov am, an
 				case 0x7:
-				m_cycles -= 2;
-				m_a[opcode & 3] = m_a[(opcode>>2) & 3];
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = m_a[opcode >> 2 & 3];
+					m_pc += 2;
+					break;
 
 				// addc dm, dn
 				case 0x8:
-				m_cycles -= 2;
-				m_d[opcode & 3] = do_add(m_d[opcode & 3], m_d[(opcode>>2) & 3], (m_psw & FLAG_CF) ? 1 : 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = do_add(m_d[opcode & 3], m_d[opcode >> 2 & 3], (m_psw & FLAG_CF) ? 1 : 0);
+					m_pc += 2;
+					break;
 
 				// subc dm, dn
 				case 0x9:
-				m_cycles -= 2;
-				m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_d[(opcode>>2) & 3], (m_psw & FLAG_CF) ? 1 : 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_d[opcode >> 2 & 3], (m_psw & FLAG_CF) ? 1 : 0);
+					m_pc += 2;
+					break;
 
 				// add am, dn
 				case 0xc:
-				m_cycles -= 2;
-				m_d[opcode & 3] = do_add(m_d[opcode & 3], m_a[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = do_add(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// sub am, dn
 				case 0xd:
-				m_cycles -= 2;
-				m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_a[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// cmp am, dn
 				case 0xe:
-				m_cycles -= 2;
-				do_sub(m_d[opcode & 3], m_a[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					do_sub(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// mov an, dm
 				case 0xf:
-				m_cycles -= 2;
-				m_d[opcode & 3] = m_a[(opcode>>2) & 3];
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = m_a[opcode >> 2 & 3];
+					m_pc += 2;
+					break;
 
 				default:
-				unemul();
-				break;
-				}
+					unemul();
+					break;
+			}
 			break;
 
 		// extended code f3 (2 bytes)
 		case 0xf3:
-			opcode = read_arg8(m_pc+1);
-			switch(opcode) {
+			opcode = read_arg8(m_pc + 1);
+			switch (opcode)
+			{
 				// and dm, dn
 				case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
 				case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] &= 0xff0000|m_d[(opcode>>2) & 3]);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] &= 0xff0000 | m_d[opcode >> 2 & 3]);
+					m_pc += 2;
+					break;
 
 				// or dm, dn
 				case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
 				case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] |= 0x00ffff&m_d[(opcode>>2) & 3]);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] |= 0x00ffff & m_d[opcode >> 2 & 3]);
+					m_pc += 2;
+					break;
 
 				// xor dm, dn
 				case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
 				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] ^= 0x00ffff&m_d[(opcode>>2) & 3]);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] ^= 0x00ffff & m_d[opcode >> 2 & 3]);
+					m_pc += 2;
+					break;
 
 				// rol dn
-				case 0x30: case 0x31: case 0x32: case 0x33: {
-				UINT32 d = m_d[opcode & 3];
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d << 1) & 0x00fffe) | ((m_psw & FLAG_CF) ? 1 : 0));
-				if(d & 0x8000)
-				m_psw |= FLAG_CF;
-				m_pc += 2;
-				break;
+				case 0x30: case 0x31: case 0x32: case 0x33:
+				{
+					UINT32 d = m_d[opcode & 3];
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d << 1) & 0x00fffe) | ((m_psw & FLAG_CF) ? 1 : 0));
+					if (d & 0x8000)
+						m_psw |= FLAG_CF;
+					m_pc += 2;
+					break;
 				}
 
 				// ror dn
-				case 0x34: case 0x35: case 0x36: case 0x37: {
-				UINT32 d = m_d[opcode & 3];
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d >> 1) & 0x007fff) | ((m_psw & FLAG_CF) ? 0x8000 : 0));
-				if(d & 1)
-				m_psw |= FLAG_CF;
-				m_pc += 2;
-				break;
+				case 0x34: case 0x35: case 0x36: case 0x37:
+				{
+					UINT32 d = m_d[opcode & 3];
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d >> 1) & 0x007fff) | ((m_psw & FLAG_CF) ? 0x8000 : 0));
+					if (d & 1)
+						m_psw |= FLAG_CF;
+					m_pc += 2;
+					break;
 				}
 
 				// asr dn
-				case 0x38: case 0x39: case 0x3a: case 0x3b: {
-				UINT32 d = m_d[opcode & 3];
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] = (d & 0xff8000) | ((d >> 1) & 0x007fff));
-				if(d & 1)
-				m_psw |= FLAG_CF;
-				m_pc += 2;
-				break;
+				case 0x38: case 0x39: case 0x3a: case 0x3b:
+				{
+					UINT32 d = m_d[opcode & 3];
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] = (d & 0xff8000) | ((d >> 1) & 0x007fff));
+					if (d & 1)
+						m_psw |= FLAG_CF;
+					m_pc += 2;
+					break;
 				}
 
 				// lsr dn
-				case 0x3c: case 0x3d: case 0x3e: case 0x3f: {
-				UINT32 d = m_d[opcode & 3];
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d >> 1) & 0x007fff));
-				if(d & 1)
-				m_psw |= FLAG_CF;
-				m_pc += 2;
+				case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+				{
+					UINT32 d = m_d[opcode & 3];
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d >> 1) & 0x007fff));
+					if (d & 1)
+						m_psw |= FLAG_CF;
+					m_pc += 2;
 				break;
 				}
 
 				// mul dn, dm
 				case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
-				case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f: {
-				UINT32 res;
-				m_cycles -= 12;
-				res = ((INT16)m_d[opcode & 3])*((INT16)m_d[(opcode>>2) & 3]);
-				m_d[opcode & 3] = res & 0xffffff;
-				m_psw &= 0xff00; // f4 is undefined
-				if(res & 0x80000000)
-				m_psw |= FLAG_NF;
-				if(!res)
-				m_psw |= FLAG_ZF;
-				m_mdr = res >> 16;
-				m_pc += 2;
-				break;
+				case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+				{
+					m_cycles -= 12;
+					UINT32 res = ((INT16)m_d[opcode & 3]) * ((INT16)m_d[opcode >> 2 & 3]);
+					m_d[opcode & 3] = res & 0xffffff;
+					m_psw &= 0xff00; // f4 is undefined
+					if (res & 0x80000000)
+						m_psw |= FLAG_NF;
+					else if (res == 0)
+						m_psw |= FLAG_ZF;
+					m_mdr = res >> 16;
+					m_pc += 2;
+					break;
 				}
 
 				// mulu dn, dm
 				case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
-				case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: {
-				UINT32 res;
-				m_cycles -= 12;
-				res = ((UINT16)m_d[opcode & 3])*((UINT16)m_d[(opcode>>2) & 3]);
-				m_d[opcode & 3] = res & 0xffffff;
-				m_psw &= 0xff00; // f4 is undefined
-				if(res & 0x80000000)
-				m_psw |= FLAG_NF;
-				if(!res)
-				m_psw |= FLAG_ZF;
-				m_mdr = res >> 16;
-				m_pc += 2;
-				break;
+				case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+				{
+					m_cycles -= 12;
+					UINT32 res = ((UINT16)m_d[opcode & 3]) * ((UINT16)m_d[opcode >> 2 & 3]);
+					m_d[opcode & 3] = res & 0xffffff;
+					m_psw &= 0xff00; // f4 is undefined
+					if (res & 0x80000000)
+						m_psw |= FLAG_NF;
+					else if (res == 0)
+						m_psw |= FLAG_ZF;
+					m_mdr = res >> 16;
+					m_pc += 2;
+					break;
 				}
 
 				// divu dn, dm
 				case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
-				case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: {
-				UINT32 n, d, q, r;
-				m_cycles -= 13;
-				m_pc += 2;
-				m_psw &= 0xff00; // f7 may be undefined
+				case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+				{
+					UINT32 n, d, q, r;
+					m_cycles -= 13;
+					m_pc += 2;
+					m_psw &= 0xff00; // f7 may be undefined
 
-				n = (m_mdr<<16)|(UINT16)m_d[opcode & 3];
-				d = (UINT16)m_d[(opcode>>2) & 3];
-				if(!d)
-				{
-					// divide by 0
-					m_psw |= FLAG_VF;
+					n = (m_mdr << 16) | (UINT16)m_d[opcode & 3];
+					d = (UINT16)m_d[opcode >> 2 & 3];
+					if (d == 0)
+					{
+						// divide by 0
+						m_psw |= FLAG_VF;
+						break;
+					}
+					q = n / d;
+					r = n % d;
+					if (q >= 0x10000)
+					{
+						// overflow (Dm and MDR are undefined)
+						m_psw |= FLAG_VF;
+						break;
+					}
+					m_d[opcode & 3] = q;
+					m_mdr = r;
+					if (q == 0)
+						m_psw |= FLAG_ZF | FLAG_ZX;
+					if (q & 0x8000)
+						m_psw |= FLAG_NF;
 					break;
 				}
-				q = n/d;
-				r = n%d;
-				if(q >= 0x10000)
-				{
-					// overflow (Dm and MDR are undefined)
-					m_psw |= FLAG_VF;
-					break;
-				}
-				m_d[opcode & 3] = q;
-				m_mdr = r;
-				if(!q)
-				m_psw |= FLAG_ZF|FLAG_ZX;
-				if(q & 0x8000)
-				m_psw |= FLAG_NF;
-				break;
-				}
 
 				// cmp dm, dn
 				case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
 				case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
-				m_cycles -= 2;
-				do_sub(m_d[opcode & 3], m_d[(opcode>>2) & 3], 0);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					do_sub(m_d[opcode & 3], m_d[opcode >> 2 & 3], 0);
+					m_pc += 2;
+					break;
 
 				// mov mdr, dn
 				case 0xc0: case 0xc4: case 0xc8: case 0xcc:
-				m_cycles -= 2;
-				m_mdr = m_d[(opcode>>2) & 3];
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_mdr = m_d[opcode >> 2 & 3];
+					m_pc += 2;
+					break;
 
 				// ext dn
 				case 0xc1: case 0xc5: case 0xc9: case 0xcd:
-				m_cycles -= 3;
-				m_mdr = m_d[(opcode>>2) & 3] & 0x8000 ? 0xffff : 0x0000;
-				m_pc += 2;
-				break;
+					m_cycles -= 3;
+					m_mdr = m_d[opcode >> 2 & 3] & 0x8000 ? 0xffff : 0x0000;
+					m_pc += 2;
+					break;
 
 				// mov dn, psw
 				case 0xd0: case 0xd4: case 0xd8: case 0xdc:
-				m_cycles -= 3;
-				m_psw = m_d[(opcode>>2) & 3];
-				m_pc += 2;
-				break;
+					m_cycles -= 3;
+					m_psw = m_d[opcode >> 2 & 3];
+					m_pc += 2;
+					break;
 
 				// mov dn, mdr
 				case 0xe0: case 0xe1: case 0xe2: case 0xe3:
-				m_cycles -= 2;
-				m_d[opcode & 3] = m_mdr;
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = m_mdr;
+					m_pc += 2;
+					break;
 
 				// not dn
 				case 0xe4: case 0xe5: case 0xe6: case 0xe7:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] ^= 0x00ffff);
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] ^= 0x00ffff);
+					m_pc += 2;
+					break;
 
 				// mov psw, dn
 				case 0xf0: case 0xf1: case 0xf2: case 0xf3:
-				m_cycles -= 2;
-				m_d[opcode & 3] = m_psw;
-				m_pc += 2;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = m_psw;
+					m_pc += 2;
+					break;
 
 				default:
-				unemul();
-				break;
-				}
+					unemul();
+					break;
+			}
 			break;
 
 		// extended code f4 (5 bytes)
 		case 0xf4:
-			opcode = read_arg8(m_pc+1);
-			switch(opcode) {
+			opcode = read_arg8(m_pc + 1);
+			switch (opcode)
+			{
 				// mov dm, (abs24, an)
 				case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
 				case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-				m_cycles -= 3;
-				write_mem16((read_arg24(m_pc+2) + m_a[(opcode>>2) & 3]) & 0xffffff, m_d[opcode & 3]);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					write_mem16(read_arg24(m_pc + 2) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
+					m_pc += 5;
+					break;
 
 				// mov am, (abs24, an)
 				case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
 				case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-				m_cycles -= 4;
-				write_mem24((read_arg24(m_pc+2) + m_a[(opcode>>2) & 3]) & 0xffffff, m_a[opcode & 3]);
-				m_pc += 5;
-				break;
+					m_cycles -= 4;
+					write_mem24(read_arg24(m_pc + 2) + m_a[opcode >> 2 & 3], m_a[opcode & 3]);
+					m_pc += 5;
+					break;
 
 				// movb dm, (abs24, an)
 				case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
 				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
-				m_cycles -= 3;
-				write_mem8((read_arg24(m_pc+2) + m_a[(opcode>>2) & 3]) & 0xffffff, m_d[opcode & 3]);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					write_mem8(read_arg24(m_pc + 2) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
+					m_pc += 5;
+					break;
 
 				// movx dm, (abs24, an)
 				case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
 				case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
-				m_cycles -= 4;
-				write_mem24((read_arg24(m_pc+2) + m_a[(opcode>>2) & 3]) & 0xffffff, m_d[opcode & 3]);
-				m_pc += 5;
-				break;
+					m_cycles -= 4;
+					write_mem24(read_arg24(m_pc + 2) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
+					m_pc += 5;
+					break;
 
 				// mov dn, (abs24)
 				case 0x40: case 0x41: case 0x42: case 0x43:
-				m_cycles -= 3;
-				write_mem16(read_arg24(m_pc+2), m_d[opcode & 3]);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					write_mem16(read_arg24(m_pc + 2), m_d[opcode & 3]);
+					m_pc += 5;
+					break;
 
 				// movb dn, (abs24)
 				case 0x44: case 0x45: case 0x46: case 0x47:
-				m_cycles -= 3;
-				write_mem8(read_arg24(m_pc+2), m_d[opcode & 3]);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					write_mem8(read_arg24(m_pc + 2), m_d[opcode & 3]);
+					m_pc += 5;
+					break;
 
 				// mov an, (abs24)
 				case 0x50: case 0x51: case 0x52: case 0x53:
-				m_cycles -= 4;
-				write_mem24(read_arg24(m_pc+2), m_a[opcode & 3]);
-				m_pc += 5;
-				break;
+					m_cycles -= 4;
+					write_mem24(read_arg24(m_pc + 2), m_a[opcode & 3]);
+					m_pc += 5;
+					break;
 
 				// add abs24, dn
 				case 0x60: case 0x61: case 0x62: case 0x63:
-				m_cycles -= 3;
-				m_d[opcode & 3] = do_add(m_d[opcode & 3], read_arg24(m_pc+2), 0);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = do_add(m_d[opcode & 3], read_arg24(m_pc + 2), 0);
+					m_pc += 5;
+					break;
 
 				// add abs24, an
 				case 0x64: case 0x65: case 0x66: case 0x67:
-				m_cycles -= 3;
-				m_a[opcode & 3] = do_add(m_a[opcode & 3], read_arg24(m_pc+2), 0);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_a[opcode & 3] = do_add(m_a[opcode & 3], read_arg24(m_pc + 2), 0);
+					m_pc += 5;
+					break;
 
 				// sub abs24, dn
 				case 0x68: case 0x69: case 0x6a: case 0x6b:
-				m_cycles -= 3;
-				m_d[opcode & 3] = do_sub(m_d[opcode & 3], read_arg24(m_pc+2), 0);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = do_sub(m_d[opcode & 3], read_arg24(m_pc + 2), 0);
+					m_pc += 5;
+					break;
 
 				// sub abs24, an
 				case 0x6c: case 0x6d: case 0x6e: case 0x6f:
-				m_cycles -= 3;
-				m_a[opcode & 3] = do_sub(m_a[opcode & 3], read_arg24(m_pc+2), 0);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_a[opcode & 3] = do_sub(m_a[opcode & 3], read_arg24(m_pc + 2), 0);
+					m_pc += 5;
+					break;
 
 				// mov imm24, dn
 				case 0x70: case 0x71: case 0x72: case 0x73:
-				m_cycles -= 3;
-				m_d[opcode & 3] = read_arg24(m_pc+2);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = read_arg24(m_pc + 2);
+					m_pc += 5;
+					break;
 
 				// mov imm24, an
 				case 0x74: case 0x75: case 0x76: case 0x77:
-				m_cycles -= 3;
-				m_a[opcode & 3] = read_arg24(m_pc+2);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_a[opcode & 3] = read_arg24(m_pc + 2);
+					m_pc += 5;
+					break;
 
 				// cmp abs24, dn
 				case 0x78: case 0x79: case 0x7a: case 0x7b:
-				m_cycles -= 3;
-				do_sub(m_d[opcode & 3], read_arg24(m_pc+2), 0);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					do_sub(m_d[opcode & 3], read_arg24(m_pc + 2), 0);
+					m_pc += 5;
+					break;
 
 				// cmp abs24, an
 				case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-				m_cycles -= 3;
-				do_sub(m_a[opcode & 3], read_arg24(m_pc+2), 0);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					do_sub(m_a[opcode & 3], read_arg24(m_pc + 2), 0);
+					m_pc += 5;
+					break;
 
 				// mov (abs24, an), dm
 				case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
 				case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
-				m_cycles -= 3;
-				m_d[opcode & 3] = (INT16)read_mem16((m_a[(opcode>>2) & 3] + read_arg24(m_pc+2)) & 0xffffff);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				// movbu (abs24, an), dm
 				case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
 				case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
-				m_cycles -= 3;
-				m_d[opcode & 3] = read_mem8((m_a[(opcode>>2) & 3] + read_arg24(m_pc+2)) & 0xffffff);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				// movb (abs24, an), dm
 				case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
 				case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
-				m_cycles -= 3;
-				m_d[opcode & 3] = (INT8)read_mem8((m_a[(opcode>>2) & 3] + read_arg24(m_pc+2)) & 0xffffff);
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				// movx (abs24, an), dm
 				case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
 				case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
-				m_cycles -= 4;
-				m_d[opcode & 3] = read_mem24((m_a[(opcode>>2) & 3] + read_arg24(m_pc+2)) & 0xffffff);
-				m_pc += 5;
-				break;
+					m_cycles -= 4;
+					m_d[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				// mov (abs24), dn
 				case 0xc0: case 0xc1: case 0xc2: case 0xc3:
-				m_cycles -= 3;
-				m_d[opcode & 3] = (INT16)read_mem16(read_arg24(m_pc+2));
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = (INT16)read_mem16(read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				// movb (abs24), dn
 				case 0xc4: case 0xc5: case 0xc6: case 0xc7:
-				m_cycles -= 3;
-				m_d[opcode & 3] = (INT8)read_mem8(read_arg24(m_pc+2));
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = (INT8)read_mem8(read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				// movbu (abs24), dn
 				case 0xc8: case 0xc9: case 0xca: case 0xcb:
-				m_cycles -= 3;
-				m_d[opcode & 3] = read_mem8(read_arg24(m_pc+2));
-				m_pc += 5;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = read_mem8(read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				// mov (abs24), an
 				case 0xd0: case 0xd1: case 0xd2: case 0xd3:
-				m_cycles -= 4;
-				m_a[opcode & 3] = read_mem24(read_arg24(m_pc+2));
-				m_pc += 5;
-				break;
+					m_cycles -= 4;
+					m_a[opcode & 3] = read_mem24(read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				// jmp imm24
 				case 0xe0:
-				m_cycles -= 4;
-				mn102_change_pc(m_pc+5+read_arg24(m_pc+2));
-				break;
+					m_cycles -= 4;
+					mn102_change_pc(m_pc + 5 + read_arg24(m_pc + 2));
+					break;
 
 				// jsr label24
 				case 0xe1:
-				m_cycles -= 5;
-				do_jsr(m_pc+5+read_arg24(m_pc+2), m_pc+5);
-				break;
+					m_cycles -= 5;
+					do_jsr(m_pc + 5 + read_arg24(m_pc + 2), m_pc + 5);
+					break;
 
 				// mov (abs24, an), am
 				case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
 				case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
-				m_cycles -= 4;
-				m_a[opcode & 3] = read_mem24((m_a[(opcode>>2) & 3] + read_arg24(m_pc+2)) & 0xffffff);
-				m_pc += 5;
-				break;
+					m_cycles -= 4;
+					m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
+					m_pc += 5;
+					break;
 
 				default:
-				unemul();
-				break;
-				}
+					unemul();
+					break;
+			}
 			break;
 
 		// extended code f5 (3 bytes)
 		case 0xf5:
-			opcode = read_arg8(m_pc+1);
-			switch(opcode) {
+			opcode = read_arg8(m_pc + 1);
+			switch (opcode)
+			{
 				// and imm8, dn
 				case 0x00: case 0x01: case 0x02: case 0x03:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] &= 0xff0000|read_arg8(m_pc+2));
-				m_pc += 3;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] &= 0xff0000 | read_arg8(m_pc + 2));
+					m_pc += 3;
+					break;
 
 				// btst imm8, dn
 				case 0x04: case 0x05: case 0x06: case 0x07:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] & read_arg8(m_pc+2));
-				m_pc += 3;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] & read_arg8(m_pc + 2));
+					m_pc += 3;
+					break;
 
 				// or imm8, dn
 				case 0x08: case 0x09: case 0x0a: case 0x0b:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] |= read_arg8(m_pc+2));
-				m_pc += 3;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] |= read_arg8(m_pc + 2));
+					m_pc += 3;
+					break;
 
 				// addnf imm8, an
 				case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-				m_cycles -= 2;
-				m_a[opcode & 3] = m_a[opcode & 3] + (INT8)read_arg8(m_pc+2);
-				m_pc += 3;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = m_a[opcode & 3] + (INT8)read_arg8(m_pc + 2);
+					m_pc += 3;
+					break;
 
 				// movb dm, (d8, an)
 				case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
 				case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-				m_cycles -= 2;
-				write_mem8((m_a[(opcode>>2) & 3]+(INT8)read_arg8(m_pc+2)) & 0xffffff, m_d[opcode & 3]);
-				m_pc += 3;
-				break;
+					m_cycles -= 2;
+					write_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2), m_d[opcode & 3]);
+					m_pc += 3;
+					break;
 
 				// movb (d8, an), dm
 				case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
 				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
-				m_cycles -= 2;
-				m_d[opcode & 3] = (INT8)read_mem8((m_a[(opcode>>2) & 3]+(INT8)read_arg8(m_pc+2)) & 0xffffff);
-				m_pc += 3;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2));
+					m_pc += 3;
+					break;
 
 				// movbu (d8, an), dm
 				case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
 				case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
-				m_cycles -= 2;
-				m_d[opcode & 3] = read_mem8((m_a[(opcode>>2) & 3]+(INT8)read_arg8(m_pc+2)) & 0xffffff);
-				m_pc += 3;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2));
+					m_pc += 3;
+					break;
 
 				// movx dm, (d8, an)
 				case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
 				case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
-				m_cycles -= 3;
-				write_mem24((m_a[(opcode>>2) & 3]+(INT8)read_arg8(m_pc+2)) & 0xffffff, m_d[opcode & 3]);
-				m_pc += 3;
-				break;
+					m_cycles -= 3;
+					write_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2), m_d[opcode & 3]);
+					m_pc += 3;
+					break;
 
 				// movx (d8, an), dm
 				case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
 				case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-				m_cycles -= 3;
-				m_d[opcode & 3] = read_mem24((m_a[(opcode>>2) & 3]+(INT8)read_arg8(m_pc+2)) & 0xffffff);
-				m_pc += 3;
-				break;
+					m_cycles -= 3;
+					m_d[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2));
+					m_pc += 3;
+					break;
 
 				// bltx label8
 				case 0xe0:
-				if(((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_NX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_VX)) // (VX^NX)=1
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_NX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_VX)) // (VX^NX)=1
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// bgtx label8
 				case 0xe1:
-				if(((m_psw & (FLAG_ZX|FLAG_NX|FLAG_VX)) == 0) || ((m_psw & (FLAG_ZX|FLAG_NX|FLAG_VX)) == (FLAG_NX|FLAG_VX))) // ((VX^NX)|ZX)=0
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (((m_psw & (FLAG_ZX|FLAG_NX|FLAG_VX)) == 0) || ((m_psw & (FLAG_ZX|FLAG_NX|FLAG_VX)) == (FLAG_NX|FLAG_VX))) // ((VX^NX)|ZX)=0
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// bgex label8
 				case 0xe2:
-				if(((m_psw & (FLAG_NX|FLAG_VX)) == 0) || ((m_psw & (FLAG_NX|FLAG_VX)) == (FLAG_NX|FLAG_VX))) // (VX^NX)=0
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (((m_psw & (FLAG_NX|FLAG_VX)) == 0) || ((m_psw & (FLAG_NX|FLAG_VX)) == (FLAG_NX|FLAG_VX))) // (VX^NX)=0
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// blex label8
 				case 0xe3:
-				if((m_psw & FLAG_ZX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_NX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_VX)) // ((VX^NX)|ZX)=1
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if ((m_psw & FLAG_ZX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_NX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_VX)) // ((VX^NX)|ZX)=1
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// bcsx label8
 				case 0xe4:
-				if(m_psw & FLAG_CX) // CX=1
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (m_psw & FLAG_CX) // CX=1
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// bhix label8
 				case 0xe5:
-				if(!(m_psw & (FLAG_ZX|FLAG_CX))) // (CX|ZX)=0
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (!(m_psw & (FLAG_ZX|FLAG_CX))) // (CX|ZX)=0
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// bccx label8
 				case 0xe6:
-				if(!(m_psw & FLAG_CX)) // CX=0
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (!(m_psw & FLAG_CX)) // CX=0
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// blsx label8
 				case 0xe7:
-				if(m_psw & (FLAG_ZX|FLAG_CX)) // (CX|ZX)=1
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (m_psw & (FLAG_ZX|FLAG_CX)) // (CX|ZX)=1
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// beqx label8
 				case 0xe8:
-				if(m_psw & FLAG_ZX) // ZX=1
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (m_psw & FLAG_ZX) // ZX=1
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// bnex label8
 				case 0xe9:
-				if(!(m_psw & FLAG_ZX)) // ZX=0
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (!(m_psw & FLAG_ZX)) // ZX=0
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				// bnc label8
 				case 0xfe:
-				if(!(m_psw & FLAG_NF)) // NF=0
-				{
-					m_cycles -= 3;
-					mn102_change_pc(m_pc+3+(INT8)read_arg8(m_pc+2));
-				}
-				else
-				{
-					m_cycles -= 2;
-					m_pc += 3;
-				}
-				break;
+					if (!(m_psw & FLAG_NF)) // NF=0
+					{
+						m_cycles -= 3;
+						mn102_change_pc(m_pc + 3 + (INT8)read_arg8(m_pc + 2));
+					}
+					else
+					{
+						m_cycles -= 2;
+						m_pc += 3;
+					}
+					break;
 
 				default:
-				unemul();
-				break;
-				}
+					unemul();
+					break;
+			}
 			break;
 
 		// nop
@@ -1795,124 +1820,125 @@ void mn10200_device::execute_run()
 
 		// extended code f7 (4 bytes)
 		case 0xf7:
-			opcode = read_arg8(m_pc+1);
-			switch(opcode) {
+			opcode = read_arg8(m_pc + 1);
+			switch (opcode)
+			{
 				// and imm16, dn
 				case 0x00: case 0x01: case 0x02: case 0x03:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] &= 0xff0000|read_arg16(m_pc+2));
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] &= 0xff0000 | read_arg16(m_pc + 2));
+					m_pc += 4;
+					break;
 
 				// btst imm16, dn
 				case 0x04: case 0x05: case 0x06: case 0x07:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] & read_arg16(m_pc+2));
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] & read_arg16(m_pc + 2));
+					m_pc += 4;
+					break;
 
 				// add imm16, an
 				case 0x08: case 0x09: case 0x0a: case 0x0b:
-				m_cycles -= 2;
-				m_a[opcode & 3] = do_add(m_a[opcode & 3], (INT16)read_arg16(m_pc+2), 0);
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = do_add(m_a[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
+					m_pc += 4;
+					break;
 
 				// sub imm16, an
 				case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-				m_cycles -= 2;
-				m_a[opcode & 3] = do_sub(m_a[opcode & 3], (INT16)read_arg16(m_pc+2), 0);
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					m_a[opcode & 3] = do_sub(m_a[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
+					m_pc += 4;
+					break;
 
 				// and imm16, psw
 				case 0x10:
-				m_cycles -= 3;
-				m_psw &= read_arg16(m_pc+2);
-				m_pc += 4;
-				break;
+					m_cycles -= 3;
+					m_psw &= read_arg16(m_pc+2);
+					m_pc += 4;
+					break;
 
 				// or imm16, psw
 				case 0x14:
-				m_cycles -= 3;
-				m_psw |= read_arg16(m_pc+2);
-				m_pc += 4;
-				break;
+					m_cycles -= 3;
+					m_psw |= read_arg16(m_pc+2);
+					m_pc += 4;
+					break;
 
 				// add imm16, dn
 				case 0x18: case 0x19: case 0x1a: case 0x1b:
-				m_cycles -= 2;
-				m_d[opcode & 3] = do_add(m_d[opcode & 3], (INT16)read_arg16(m_pc+2), 0);
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = do_add(m_d[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
+					m_pc += 4;
+					break;
 
 				// sub imm16, dn
 				case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-				m_cycles -= 2;
-				m_d[opcode & 3] = do_sub(m_d[opcode & 3], (INT16)read_arg16(m_pc+2), 0);
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = do_sub(m_d[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
+					m_pc += 4;
+					break;
 
 				// or imm16, dn
 				case 0x40: case 0x41: case 0x42: case 0x43:
-				m_cycles -= 2;
-				test_nz16(m_d[opcode & 3] |= read_arg16(m_pc+2));
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					test_nz16(m_d[opcode & 3] |= read_arg16(m_pc + 2));
+					m_pc += 4;
+					break;
 
 				// cmp imm16, dn
 				case 0x48: case 0x49: case 0x4a: case 0x4b:
-				m_cycles -= 2;
-				do_sub(m_d[opcode & 3], (INT16)read_arg16(m_pc+2), 0);
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					do_sub(m_d[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
+					m_pc += 4;
+					break;
 
 				// xor imm16, dn
 				case 0x4c: case 0x4d: case 0x4e: case 0x4f:
-				m_cycles -= 3;
-				test_nz16(m_d[opcode & 3] ^= read_arg16(m_pc+2));
-				m_pc += 4;
-				break;
+					m_cycles -= 3;
+					test_nz16(m_d[opcode & 3] ^= read_arg16(m_pc + 2));
+					m_pc += 4;
+					break;
 
 				// mov dm, (imm16, an)
 				case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
 				case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
-				m_cycles -= 2;
-				write_mem16((m_a[(opcode>>2)&3]+(INT16)read_arg16(m_pc+2)) & 0xffffff, (UINT16)m_d[opcode & 3]);
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					write_mem16(m_a[opcode >> 2 & 3] + (INT16)read_arg16(m_pc + 2), (UINT16)m_d[opcode & 3]);
+					m_pc += 4;
+					break;
 
 				// mov (imm16, an), dm
 				case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
 				case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
-				m_cycles -= 2;
-				m_d[opcode & 3] = (INT16)read_mem16((m_a[(opcode>>2) & 3] + (INT16)read_arg16(m_pc+2)) & 0xffffff);
-				m_pc += 4;
-				break;
+					m_cycles -= 2;
+					m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + (INT16)read_arg16(m_pc + 2));
+					m_pc += 4;
+					break;
 
 				default:
-				unemul();
-				break;
-				}
+					unemul();
+					break;
+			}
 			break;
 
 		// mov imm16, dn
 		case 0xf8: case 0xf9: case 0xfa: case 0xfb:
 			m_cycles -= 1;
-			m_d[opcode & 3] = (INT16)read_arg16(m_pc+1);
+			m_d[opcode & 3] = (INT16)read_arg16(m_pc + 1);
 			m_pc += 3;
 			break;
 
 		// jmp label16
 		case 0xfc:
 			m_cycles -= 2;
-			mn102_change_pc(m_pc+3+(INT16)read_arg16(m_pc+1));
+			mn102_change_pc(m_pc + 3 + (INT16)read_arg16(m_pc + 1));
 			break;
 
 		// jsr label16
 		case 0xfd:
 			m_cycles -= 4;
-			do_jsr(m_pc+3+(INT16)read_arg16(m_pc+1), m_pc+3);
+			do_jsr(m_pc + 3 + (INT16)read_arg16(m_pc + 1), m_pc + 3);
 			break;
 
 		// rts
diff --git a/src/emu/cpu/mn10200/mn10200.h b/src/emu/cpu/mn10200/mn10200.h
index 0290e0b4c69..47292984274 100644
--- a/src/emu/cpu/mn10200/mn10200.h
+++ b/src/emu/cpu/mn10200/mn10200.h
@@ -139,15 +139,15 @@ private:
 
 	UINT8 read_arg8(UINT32 address);
 	UINT16 read_arg16(UINT32 address);
-	INT32 read_arg24(offs_t adr);
+	UINT32 read_arg24(UINT32 address);
 
 	UINT8 read_mem8(UINT32 address);
 	UINT16 read_mem16(UINT32 address);
-	INT32 read_mem24(offs_t adr);
+	UINT32 read_mem24(UINT32 address);
 
 	void write_mem8(UINT32 address, UINT8 data);
 	void write_mem16(UINT32 address, UINT16 data);
-	void write_mem24(offs_t adr, UINT32 val);
+	void write_mem24(UINT32 address, UINT32 data);
 
 	void mn102_change_pc(UINT32 pc);
 	void mn102_take_irq(int level, int group);