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(mess) dp8390: don't hang when reg page 2 set (nw)

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(mess) ne1000,ne2000: ram on the 2000 is incompletely decoded, probably on 1000 also, needs verification (nw)
This commit is contained in:
cracyc 2013-04-13 03:04:07 +00:00
parent 07df4de8a9
commit 4a39209b73
3 changed files with 11 additions and 6 deletions
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13
src/mess/machine/dp8390.c
View File

@ -298,6 +298,9 @@ READ16_MEMBER(dp8390_device::dp8390_r) {
case 0x8f: case 0x8f:
data = m_regs.imr; data = m_regs.imr;
break; break;
case 0xc0:
data = m_regs.cr;
break;
default: default:
if(m_type == TYPE_RTL8019A) { if(m_type == TYPE_RTL8019A) {
switch((offset & 0x0f)|(m_regs.cr & 0xc0)) { switch((offset & 0x0f)|(m_regs.cr & 0xc0)) {
@ -307,9 +310,7 @@ READ16_MEMBER(dp8390_device::dp8390_r) {
case 0x0b: case 0x0b:
data = 'p'; data = 'p';
break; break;
case 0xc0:
data = m_regs.cr;
break;
case 0xc1: case 0xc1:
data = m_8019regs.cr9346; data = m_8019regs.cr9346;
break; break;
@ -465,12 +466,12 @@ WRITE16_MEMBER(dp8390_device::dp8390_w) {
case 0x87: case 0x87:
m_regs.ac = (m_regs.ac & 0xff00) | data; m_regs.ac = (m_regs.ac & 0xff00) | data;
break; break;
case 0xc0:
set_cr(data);
break;
default: default:
if(m_type == TYPE_RTL8019A) { if(m_type == TYPE_RTL8019A) {
switch((offset & 0x0f)|(m_regs.cr & 0xc0)) { switch((offset & 0x0f)|(m_regs.cr & 0xc0)) {
case 0xc0:
set_cr(data);
break;
// XXX: rest of the regs // XXX: rest of the regs
default: default:
logerror("rtl8019: invalid write page %01X reg %02X data %04X\n", (m_regs.cr & 0xc0) >> 6, offset & 0x0f, data); logerror("rtl8019: invalid write page %01X reg %02X data %04X\n", (m_regs.cr & 0xc0) >> 6, offset & 0x0f, data);

2
src/mess/machine/ne1000.c
View File

@ -97,6 +97,7 @@ WRITE_LINE_MEMBER(ne1000_device::ne1000_irq_w) {
} }
READ8_MEMBER(ne1000_device::ne1000_mem_read) { READ8_MEMBER(ne1000_device::ne1000_mem_read) {
offset &= ~0xc000; // verify
if(offset < 16) return m_prom[offset]; if(offset < 16) return m_prom[offset];
if((offset < (8*1024)) || (offset >= (16*1024))) { if((offset < (8*1024)) || (offset >= (16*1024))) {
logerror("ne1000: invalid memory read %04X\n", offset); logerror("ne1000: invalid memory read %04X\n", offset);
@ -106,6 +107,7 @@ READ8_MEMBER(ne1000_device::ne1000_mem_read) {
} }
WRITE8_MEMBER(ne1000_device::ne1000_mem_write) { WRITE8_MEMBER(ne1000_device::ne1000_mem_write) {
offset &= ~0xc000; // verify
if((offset < (8*1024)) || (offset >= (16*1024))) { if((offset < (8*1024)) || (offset >= (16*1024))) {
logerror("ne1000: invalid memory write %04X\n", offset); logerror("ne1000: invalid memory write %04X\n", offset);
return; return;

2
src/mess/machine/ne2000.c
View File

@ -107,6 +107,7 @@ WRITE_LINE_MEMBER(ne2000_device::ne2000_irq_w) {
} }
READ8_MEMBER(ne2000_device::ne2000_mem_read) { READ8_MEMBER(ne2000_device::ne2000_mem_read) {
offset &= ~0x8000;
if(offset < 32) return m_prom[offset>>1]; if(offset < 32) return m_prom[offset>>1];
if((offset < (16*1024)) || (offset >= (32*1024))) { if((offset < (16*1024)) || (offset >= (32*1024))) {
logerror("ne2000: invalid memory read %04X\n", offset); logerror("ne2000: invalid memory read %04X\n", offset);
@ -116,6 +117,7 @@ READ8_MEMBER(ne2000_device::ne2000_mem_read) {
} }
WRITE8_MEMBER(ne2000_device::ne2000_mem_write) { WRITE8_MEMBER(ne2000_device::ne2000_mem_write) {
offset &= ~0x8000;
if((offset < (16*1024)) || (offset >= (32*1024))) { if((offset < (16*1024)) || (offset >= (32*1024))) {
logerror("ne2000: invalid memory write %04X\n", offset); logerror("ne2000: invalid memory write %04X\n", offset);
return; return;