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MIE: handle Maple reset pattern, made a better hack for it, change frequency to more real (yes, its a 16 or more MHz Z80 core)

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TODO: findout why SH4 game code doesnt wait long enough for internal firmware RAM test completes after reset
This commit is contained in:
MetalliC 2015-01-27 15:22:36 +02:00
parent 12643dfbda
commit 4a8d4bd574
2 changed files with 15 additions and 6 deletions
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2
src/mame/drivers/naomi.c
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@ -2618,7 +2618,7 @@ static MACHINE_CONFIG_START( naomi_aw_base, naomi_state )
MACHINE_CONFIG_END MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( naomi_base, naomi_aw_base ) static MACHINE_CONFIG_DERIVED( naomi_base, naomi_aw_base )
MCFG_MIE_ADD("mie", 4000000, "maple_dc", 0, 0, 0, 0, ":MIE.3", 0, ":MIE.5", 0, 0) // Actual frequency unknown MCFG_MIE_ADD("mie", XTAL_32MHz/2, "maple_dc", 0, 0, 0, 0, ":MIE.3", 0, ":MIE.5", 0, 0) // Actual frequency unknown, most likely 1/2 of 32MHz XTAL or even 2/3 (yes, 21MHz Z80 core)
MCFG_SEGA_837_13551_DEVICE_ADD("837_13551", "mie", ":TILT", ":P1", ":P2", ":A0", ":A1", ":A2", ":A3", ":A4", ":A5", ":A6", ":A7", ":OUTPUT") MCFG_SEGA_837_13551_DEVICE_ADD("837_13551", "mie", ":TILT", ":P1", ":P2", ":A0", ":A1", ":A2", ":A3", ":A4", ":A5", ":A6", ":A7", ":OUTPUT")
MCFG_EEPROM_SERIAL_93C46_8BIT_ADD("mie_eeprom") MCFG_EEPROM_SERIAL_93C46_8BIT_ADD("mie_eeprom")

19
src/mame/machine/mie.c
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@ -103,6 +103,11 @@ void mie_device::device_start()
save_item(NAME(irq_enable)); save_item(NAME(irq_enable));
save_item(NAME(irq_pending)); save_item(NAME(irq_pending));
save_item(NAME(maple_irqlevel)); save_item(NAME(maple_irqlevel));
// patch out MIE RAM test
// TODO: figure out why SH4 code doesn't wait long enough for internal firmware's RAM test completed in the case of reset
UINT32 *rom = (UINT32*)memregion("mie")->base();
rom[0x144/4] = 0x0001d8c3;
} }
void mie_device::device_reset() void mie_device::device_reset()
@ -164,13 +169,17 @@ void mie_device::device_timer(emu_timer &_timer, device_timer_id id, int param,
control |= CTRL_TFB|CTRL_EMP; control |= CTRL_TFB|CTRL_EMP;
} }
} }
if(control & CTRL_HRES) {
raise_irq(maple_irqlevel);
}
} }
void mie_device::maple_w(const UINT32 *data, UINT32 in_size) void mie_device::maple_w(const UINT32 *data, UINT32 in_size)
{ {
memcpy(tbuf, data, in_size*4); memcpy(tbuf, data, in_size*4);
lreg = in_size-1; lreg = in_size-1;
control &= ~(CTRL_TXB|CTRL_TFB|CTRL_RFB|CTRL_BFOV); // currently not known how/then CTRL_HRES is cleared after reset, lets clear it at packet receive
control &= ~(CTRL_HRES|CTRL_TXB|CTRL_TFB|CTRL_RFB|CTRL_BFOV);
control |= CTRL_RXB; control |= CTRL_RXB;
timer->adjust(attotime::from_usec(20)); timer->adjust(attotime::from_usec(20));
@ -357,8 +366,8 @@ READ8_MEMBER(mie_device::jvs_sense_r)
void mie_device::maple_reset() void mie_device::maple_reset()
{ {
// ignoring reset maple pattern is HUGE HACK control &= ~(CTRL_RXB|CTRL_TXB|CTRL_TFB|CTRL_RFB|CTRL_BFOV);
// current implementation works only because of in such case procedure of firmware upload by games will be skipped at all control |= CTRL_HRES;
// so in better case - inputs doesnt work if game uses very different firmware version than already uploaded by BIOS, in worst case - game hang/reboot
// TODO: figure out why game code doesn't wait long enough for internal firmware's RAM test completed in the case of proper reset timer->adjust(attotime::from_usec(20));
} }