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https://github.com/holub/mame
synced 2025-04-21 07:52:35 +03:00
- Changed S14001A emulator to allow setting the clock frequency instead of the clock multiplier. This is how the real chip works
- Changed the Berzerk driver to set the S14001A clock as per the schematics. This proves that the schematics are correct and the comment suggesting the contrary can be removed.
This commit is contained in:
Zsolt Vasvari
parent
587c293ee0
commit
4ab04517cb
@ -13,6 +13,8 @@
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1.01 fixed clipping problem - LN (0.111u5)
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1.1 add VSU-1000 features, fully fixed stream update by fixing word latching - LN (0.111u6)
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1.11 fix signedness of output, pre-multiply, fixes clicking on VSU-1000 volume change - LN (0.111u7)
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1.20 supports setting the clock freq directly - reset is done by external hardware,
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the chip has no reset line ZV (0.122)
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TODO:
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* increase accuracy of internal S14001A 'filter' for both driven and undriven cycles (its not terribly inaccurate for undriven cycles, but the dc sliding of driven cycles is not emulated)
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@ -156,9 +158,7 @@ typedef struct
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UINT8 audioout; // filtered audio output
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UINT8 *SpeechRom; // array to hold rom contents, mame will not need this, will use a pointer
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UINT8 filtervals[8];
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UINT8 VSU1000_amp; // amplitude setting on VSU-1000 board
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UINT16 VSU1000_freq; // frequency setting on VSU-1000 board
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UINT16 VSU1000_counter; // counter for freq divider
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UINT8 VSU1000_amp; // amplitude setting on VSU-1000 board
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} S14001AChip;
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//#define DEBUGSTATE
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@ -437,11 +437,7 @@ static void s14001a_pcm_update(void *param, stream_sample_t **inputs, stream_sam
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mixp = &mix[0];
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for (i = 0; i < length; i++)
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{
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if (--chip->VSU1000_counter==0)
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{
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s14001a_clock(chip);
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chip->VSU1000_counter = chip->VSU1000_freq;
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}
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s14001a_clock(chip);
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outputs[0][i] = ((((INT16)chip->audioout)-128)<<6)*chip->VSU1000_amp;
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}
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}
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@ -459,9 +455,6 @@ static void *s14001a_start(int sndindex, int clock, const void *config)
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chip->GlobalSilenceState = 1;
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chip->OldDelta = 0x02;
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chip->DACOutput = SILENCE;
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chip->VSU1000_amp = 0; /* reset by /reset line */
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chip->VSU1000_freq = 1; /* base-1; reset by /reset line */
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chip->VSU1000_counter = 1; /* base-1; not reset by /reset line but this is the best place to reset it */
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for (i = 0; i < 8; i++)
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{
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@ -472,7 +465,7 @@ static void *s14001a_start(int sndindex, int clock, const void *config)
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chip->SpeechRom = memory_region(intf->region);
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chip->stream = stream_create(0, 1, clock, chip, s14001a_pcm_update);
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chip->stream = stream_create(0, 1, Machine->sample_rate, chip, s14001a_pcm_update);
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return chip;
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}
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@ -488,7 +481,7 @@ static void s14001a_set_info(void *token, UINT32 state, sndinfo *info)
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int S14001A_bsy_0_r(void)
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{
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S14001AChip *chip = sndti_token(SOUND_S14001A, 0);
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stream_update(chip->stream);
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stream_update(chip->stream);
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#ifdef DEBUGSTATE
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fprintf(stderr,"busy state checked: %d\n",(chip->machineState != 0) );
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#endif
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@ -506,43 +499,37 @@ void S14001A_rst_0_w(int data)
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{
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S14001AChip *chip = sndti_token(SOUND_S14001A, 0);
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stream_update(chip->stream);
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chip->LatchedWord = chip->WordInput;
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chip->LatchedWord = chip->WordInput;
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chip->resetState = (data==1);
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chip->machineState = chip->resetState ? 1 : chip->machineState;
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}
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void S14001A_set_rate(int newrate)
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void S14001A_set_clock(int clock)
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{
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S14001AChip *chip = sndti_token(SOUND_S14001A, 0);
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stream_update(chip->stream);
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chip->VSU1000_freq = newrate;
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S14001AChip *chip = sndti_token(SOUND_S14001A, 0);
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stream_set_sample_rate(chip->stream, clock);
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}
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void S14001A_set_volume(int volume)
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{
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S14001AChip *chip = sndti_token(SOUND_S14001A, 0);
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stream_update(chip->stream);
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chip->VSU1000_amp = volume;
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stream_update(chip->stream);
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chip->VSU1000_amp = volume;
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}
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void s14001a_get_info(void *token, UINT32 state, sndinfo *info)
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{
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switch (state)
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{
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/* --- the following bits of info are returned as 64-bit signed integers --- */
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/* --- the following bits of info are returned as pointers to data or functions --- */
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case SNDINFO_PTR_SET_INFO: info->set_info = s14001a_set_info; break;
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case SNDINFO_PTR_START: info->start = s14001a_start; break;
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case SNDINFO_PTR_STOP: /* Nothing */ break;
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case SNDINFO_PTR_RESET: /* Nothing */ break;
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/* --- the following bits of info are returned as NULL-terminated strings --- */
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case SNDINFO_STR_NAME: info->s = "S14001A"; break;
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case SNDINFO_STR_CORE_FAMILY: info->s = "TSI S14001A"; break;
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case SNDINFO_STR_CORE_VERSION: info->s = "1.11"; break;
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case SNDINFO_STR_NAME: info->s = "S14001A"; break;
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case SNDINFO_STR_CORE_FAMILY: info->s = "TSI S14001A"; break;
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case SNDINFO_STR_CORE_VERSION: info->s = "1.20"; break;
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case SNDINFO_STR_CORE_FILE: info->s = __FILE__; break;
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case SNDINFO_STR_CORE_CREDITS: info->s = "Copyright Jonathan Gevaryahu"; break;
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case SNDINFO_STR_CORE_CREDITS: info->s = "Copyright Jonathan Gevaryahu"; break;
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}
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}
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@ -9,7 +9,7 @@ struct S14001A_interface
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int S14001A_bsy_0_r(void); /* read BUSY pin */
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void S14001A_reg_0_w(int data); /* write to input latch */
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void S14001A_rst_0_w(int data); /* write to RESET pin */
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void S14001A_set_rate(int newrate); /* set VSU-1000 clock divider */
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void S14001A_set_clock(int clock); /* set VSU-1000 clock */
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void S14001A_set_volume(int volume); /* set VSU-1000 volume control */
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#endif
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@ -20,7 +20,7 @@
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#define MASTER_CLOCK (XTAL_10MHz)
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#define MAIN_CPU_CLOCK (MASTER_CLOCK / 4)
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#define PIXEL_CLOCK (MASTER_CLOCK / 2)
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#define S14001A_CLOCK (MASTER_CLOCK / 2)
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#define S14001_CLOCK (MASTER_CLOCK / 4)
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#define HTOTAL (0x140)
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#define HBEND (0x000)
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#define HBSTART (0x100)
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@ -481,41 +481,49 @@ static const struct CustomSound_interface berzerk_custom_interface =
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static WRITE8_HANDLER( berzerk_audio_w )
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{
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int clock_divisor;
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switch (offset)
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{
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/* offset 4 writes to the S14001A */
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case 4:
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switch (data >> 6)
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{
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/* write data to the S14001 */
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case 0:
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/* only if not busy */
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if (!S14001A_bsy_0_r())
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{
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S14001A_reg_0_w(data & 0x3f);
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/* clock the chip -- via a 555 timer */
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S14001A_rst_0_w(1);
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S14001A_rst_0_w(0);
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}
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break;
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case 1:
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/* volume */
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S14001A_set_volume(((data & 0x38) >> 3) + 1);
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/* clock control - the first LS161 divides the clock by 9 to 16, the 2nd by 8,
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giving a final clock from 19.5kHz to 34.7kHz */
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clock_divisor = 16 - (data & 0x07);
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S14001A_set_clock(S14001_CLOCK / clock_divisor / 8);
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break;
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default: break; /* 2 and 3 are not connected */
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}
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break;
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/* offset 6 writes to the sfxcontrol latch */
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case 6:
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exidy_sfxctrl_w(data >> 6, data);
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break;
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/* offset 4 writes to the S14001A */
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case 4:
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if ((data & 0xc0) == 0x40) /* VSU-1000 control write */
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{
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/* volume and frequency control goes here */
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/* mame_printf_debug("TODO: VSU-1000 Control write (ignored for now)\n");*/
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S14001A_set_volume(((data & 0x38) >> 3) + 1);
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S14001A_set_rate((16 - (data & 0x07)) * 16); /* second LS161 has load triggered by its own TC(when it equals 16) long before the first ls161 will TC and fire again, so effectively it only divides by 15 and not 16. If the clock, as opposed to the E enable, had been tied to the first LS161's TC instead, it would divide by 16 as expected */
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}
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else if ((data & 0xc0) != 0x00)
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/* vsu-1000 ignores these writes entirely */
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mame_printf_debug("bogus write ignored\n");
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else
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{
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/* select word input */
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if (S14001A_bsy_0_r()) /* skip if busy... */
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{
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mame_printf_debug("S14001A busy, ignoring write\n");
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break;
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}
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/* write to the register */
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S14001A_reg_0_w(data & 0x3f);
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S14001A_rst_0_w(1);
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S14001A_rst_0_w(0);
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}
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break;
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/* everything else writes to the 6840 */
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default:
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exidy_sh6840_w(offset, data);
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@ -532,6 +540,14 @@ static READ8_HANDLER( berzerk_audio_r )
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static SOUND_RESET(berzerk)
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{
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/* clears the flip-flop controlling the volume and freq on the speech chip */
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berzerk_audio_w(4, 0x40);
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}
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/*************************************
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*
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* Memory handlers
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@ -866,7 +882,9 @@ static MACHINE_DRIVER_START( berzerk )
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/* audio hardware */
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MDRV_SPEAKER_STANDARD_MONO("mono")
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MDRV_SOUND_ADD(S14001A, S14001A_CLOCK) /* CPU clock divided by 16 divided by a programmable TTL setup */
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MDRV_SOUND_RESET(berzerk)
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MDRV_SOUND_ADD(S14001A, 0) /* placeholder - the clock is software controllable */
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MDRV_SOUND_CONFIG(berzerk_s14001a_interface)
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MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
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