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Added emulation of background graphics (blitter), sound and inputs to skimaxx.c [Luca Elia]
New games added or promoted from NOT_WORKING status --------------------------------------------------- Skimaxx [Luca Elia, Phil Bennett] Note: 68EC030 disassembler is busted
This commit is contained in:
Luca Elia
parent
479de012c4
commit
4ae63a9782
@ -1,24 +1,43 @@
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/***************************************************************************
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/*****************************************************************************************************
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Skimaxx
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Skimaxx
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Preliminary driver by Phil Bennett
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driver by Phil Bennett and Luca Elia
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68030-40 * 2
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Top Board:
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TMS34010-50
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MSM6295 * 4
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Video hardware consists of scaling sprites with a Mode 7-style ground?
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68EC030-40
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TMS34010 seems to draws text, score etc.
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(MSM6295 + Crystal) * 4
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It looks like a bistream for a Xilinx FPGA is stored in ROM. The sub
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Bottom Board:
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CPU bit-bangs 30864 bits worth of data to 0x40000003 twice.
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***************************************************************************/
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68EC030-40
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TMS34010-50
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Video hardware:
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- Blitter that supports rotation and zoom (background and sprites)
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- TMS34010 (text, score)
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Notes:
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- It looks like a bistream for a Xilinx FPGA is stored in ROM.
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The sub CPU bit-bangs 30864 bits worth of data to 0x40000003 twice.
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- There seems to be a bug in the game code drawing routines, causing objects to have some pixels
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chopped off. This is most noticeable for distant thin objects (falgs, poles of the start banner).
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See maincpu routine at 387B8, specifically the jump at 3880E throws 4 horizontal pixels away.
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- The player often disappears (when she's too slow?). Is this normal ?
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- Are button 2 and analog input "Y" used ?
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*****************************************************************************************************/
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#include "driver.h"
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#include "driver.h"
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#include "cpu/m68000/m68000.h"
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#include "cpu/m68000/m68000.h"
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#include "cpu/tms34010/tms34010.h"
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#include "cpu/tms34010/tms34010.h"
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#include "sound/okim6295.h"
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/*************************************
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/*************************************
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@ -27,8 +46,8 @@
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*
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*
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*************************************/
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*************************************/
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static UINT32 *sprite_buffer;
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static UINT32 *bg_buffer; // i.e. background and sprites
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static UINT16 *frame_buffer;
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static UINT16 *fg_buffer; // i.e. text
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/*************************************
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/*************************************
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@ -37,11 +56,92 @@ static UINT16 *frame_buffer;
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*
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*
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*************************************/
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*************************************/
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static VIDEO_START( skimaxx )
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UINT32 *skimaxx_bg_buffer_front;
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{
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UINT32 *skimaxx_bg_buffer_back;
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UINT32 *skimaxx_blitter_regs;
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UINT16 *skimaxx_blitter_gfx;
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UINT32 skimaxx_blitter_gfx_len;
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UINT32 skimaxx_blitter_src_x, skimaxx_blitter_src_dx;
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UINT32 skimaxx_blitter_src_y, skimaxx_blitter_src_dy;
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// Set up blit parameters
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static WRITE32_HANDLER( skimaxx_blitter_w )
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{
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UINT32 newdata = COMBINE_DATA( &skimaxx_blitter_regs[offset] );
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switch (offset)
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{
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case 0:
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skimaxx_blitter_src_dy = (newdata & 0x7fff) - (newdata & 0x8000);
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break;
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case 1:
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skimaxx_blitter_src_x = (newdata & 0x1ff) << 8;
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skimaxx_blitter_src_y = (newdata >> 9) << 8;
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break;
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case 2:
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if (ACCESSING_BITS_16_31)
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skimaxx_blitter_src_dx = (newdata >> 16) & 0xffff;
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if (ACCESSING_BITS_0_15)
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skimaxx_blitter_src_dx = newdata & 0xffff;
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skimaxx_blitter_src_dx = (skimaxx_blitter_src_dx & 0x7fff) - (skimaxx_blitter_src_dx & 0x8000);
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break;
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case 3:
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// Usually 0. Set to 10 for water/sand near the horizon
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break;
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}
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}
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}
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// A read by the 68030 from this area blits one pixel to the back buffer (at the same offset)
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static READ32_HANDLER( skimaxx_blitter_r )
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{
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UINT32 penaddr = ((skimaxx_blitter_src_x >> 8) & 0x1ff) + ((skimaxx_blitter_src_y >> 8) << 9);
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UINT16 *src = skimaxx_blitter_gfx + (penaddr % skimaxx_blitter_gfx_len);
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UINT32 *dst = skimaxx_bg_buffer_back + offset;
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UINT16 pen = (*src) & 0x7fff;
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if (pen)
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{
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if (ACCESSING_BITS_16_31)
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*dst = (*dst & 0x0000ffff) | (pen << 16);
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else
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*dst = (*dst & 0xffff0000) | pen;
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}
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skimaxx_blitter_src_x = (skimaxx_blitter_src_x & 0x10000) | ((skimaxx_blitter_src_x + skimaxx_blitter_src_dx) & 0xffff);
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skimaxx_blitter_src_y = (skimaxx_blitter_src_y & 0xffff0000) | ((skimaxx_blitter_src_y + skimaxx_blitter_src_dy) & 0xffff);
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return 0;
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}
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static VIDEO_START( skimaxx )
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{
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skimaxx_blitter_gfx = (UINT16 *) memory_region( machine, "blitter" );
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skimaxx_blitter_gfx_len = memory_region_length( machine, "blitter" ) / 2;
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bg_buffer = auto_alloc_array(machine, UINT32, 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * 2); // 2 buffers
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skimaxx_bg_buffer_back = bg_buffer + 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * 0;
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skimaxx_bg_buffer_front = bg_buffer + 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * 1;
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memory_configure_bank(machine, 1, 0, 1, skimaxx_bg_buffer_back, 0);
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memory_configure_bank(machine, 1, 1, 1, skimaxx_bg_buffer_front, 0);
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}
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static VIDEO_UPDATE( skimaxx )
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{
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// popmessage("%02x %02x", input_port_read(screen->machine, "X"), input_port_read(screen->machine, "Y") );
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VIDEO_UPDATE_CALL(tms340x0);
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return 0;
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}
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/*************************************
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/*************************************
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*
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*
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@ -52,12 +152,12 @@ static VIDEO_START( skimaxx )
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// TODO: Might not be used
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// TODO: Might not be used
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static void skimaxx_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
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static void skimaxx_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
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{
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{
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memcpy(shiftreg, &frame_buffer[TOWORD(address)], 512 * sizeof(UINT16));
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memcpy(shiftreg, &fg_buffer[TOWORD(address)], 512 * sizeof(UINT16));
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}
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}
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static void skimaxx_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
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static void skimaxx_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
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{
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{
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memcpy(&frame_buffer[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
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memcpy(&fg_buffer[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
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}
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}
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@ -70,22 +170,35 @@ static void skimaxx_from_shiftreg(const address_space *space, UINT32 address, UI
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static void skimaxx_scanline_update(const device_config *screen, bitmap_t *bitmap, int scanline, const tms34010_display_params *params)
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static void skimaxx_scanline_update(const device_config *screen, bitmap_t *bitmap, int scanline, const tms34010_display_params *params)
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{
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{
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// TODO: This isn't correct. I just hacked it together quickly so I could see something!
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// TODO: This isn't correct. I just hacked it together quickly so I could see something!
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if (params->rowaddr >= 0x220)
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if (params->rowaddr >= 0x220)
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{
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{
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UINT32 rowaddr = (params->rowaddr - 0x220);
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UINT32 rowaddr = (params->rowaddr - 0x220);
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UINT16 *vram1 = &frame_buffer[rowaddr << 8];
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UINT16 *fg = &fg_buffer[rowaddr << 8];
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UINT32 *bg = &skimaxx_bg_buffer_front[rowaddr/2 * 1024/2];
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UINT16 *dest = BITMAP_ADDR16(bitmap, scanline, 0);
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UINT16 *dest = BITMAP_ADDR16(bitmap, scanline, 0);
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int coladdr = params->coladdr;
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int coladdr = params->coladdr;
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int x;
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int x;
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coladdr = 0;
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coladdr = 0;
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if (scanline >= 236)
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dest += params->heblnk;
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return;
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for (x = params->heblnk; x < params->hsblnk; x+=2)
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for (x = params->heblnk; x < params->hsblnk; ++x)
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{
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{
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UINT16 tmspix = vram1[coladdr++] & 0x7fff;
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UINT16 tmspix;
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dest[x] = tmspix;
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tmspix = *fg & 0x7fff;
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if (tmspix)
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{
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*dest++ = tmspix;
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*dest++ = tmspix;
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}
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else
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{
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UINT32 data = *bg & 0x7fff7fff;
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*dest++ = data >> 16;
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*dest++ = data;
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}
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fg++;
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bg++;
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}
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}
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}
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}
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}
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}
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@ -114,11 +227,73 @@ static READ32_HANDLER( m68k_tms_r )
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*
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*
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*************************************/
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*************************************/
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/*
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bit 7: 0->1 at the start, and before bit banging to 40000003 (Xilinx FPGA configuration write port?)
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bit 6: double buffering
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bit 5: 0/1 less oftenly
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bit 4: 0->1 clocks bit banging
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bit 3-1: 1?
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bit 0: bit banging data
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*/
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UINT32 *skimaxx_fpga_ctrl;
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static WRITE32_HANDLER( skimaxx_fpga_ctrl_w )
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{
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UINT32 newdata = COMBINE_DATA( skimaxx_fpga_ctrl );
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if (ACCESSING_BITS_0_7)
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{
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// double buffering
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UINT8 bank_bg_buffer = (newdata & 0x40) ? 1 : 0;
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skimaxx_bg_buffer_back = bg_buffer + 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * bank_bg_buffer;
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skimaxx_bg_buffer_front = bg_buffer + 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * (1 - bank_bg_buffer);
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memory_set_bank(space->machine, 1, bank_bg_buffer);
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}
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}
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// 0x2000004c: bit 7, bit 0
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static READ32_HANDLER( unk_r )
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static READ32_HANDLER( unk_r )
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{
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return (*skimaxx_fpga_ctrl & 0x20) ? 0x80 : 0x00;
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}
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// 0x20000023
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static READ32_HANDLER( skimaxx_unk1_r )
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{
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{
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return 0x80;
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return 0x80;
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}
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}
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static WRITE32_HANDLER( skimaxx_unk1_w )
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{
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}
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static WRITE32_HANDLER( skimaxx_sub_ctrl_w )
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{
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// 7e/7f at the start. 3f/7f, related to reads from 1018xxxx
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if (ACCESSING_BITS_0_7)
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{
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const device_config *subcpu = devtag_get_device(space->machine, "subcpu");
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cpu_set_input_line(subcpu, INPUT_LINE_RESET, (data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
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cpu_set_input_line(subcpu, INPUT_LINE_HALT, (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
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}
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}
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/*
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00 left max again
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01 right max
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..
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10 center
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..
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1f left max
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*/
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static READ32_HANDLER( skimaxx_analog_r )
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{
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return BITSWAP8(input_port_read(space->machine, offset ? "Y" : "X"), 0,1,2,3,4,5,6,7);
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}
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/*************************************
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/*************************************
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*
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*
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@ -128,40 +303,58 @@ static READ32_HANDLER( unk_r )
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static ADDRESS_MAP_START( 68030_1_map, ADDRESS_SPACE_PROGRAM, 32 )
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static ADDRESS_MAP_START( 68030_1_map, ADDRESS_SPACE_PROGRAM, 32 )
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AM_RANGE(0x00000000, 0x001fffff) AM_ROM
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AM_RANGE(0x00000000, 0x001fffff) AM_ROM
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AM_RANGE(0x10000000, 0x10000003) AM_RAM
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AM_RANGE(0x10000000, 0x10000003) AM_WRITE( skimaxx_sub_ctrl_w )
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AM_RANGE(0x10100000, 0x1010000f) AM_READWRITE(m68k_tms_r, m68k_tms_w)
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AM_RANGE(0x10100000, 0x1010000f) AM_READWRITE(m68k_tms_r, m68k_tms_w)//AM_NOP
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AM_RANGE(0x10180000, 0x10187fff) AM_RAM AM_SHARE(1)
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// AM_RANGE(0x10180000, 0x10187fff) AM_RAM AM_SHARE(1)
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AM_RANGE(0x20000000, 0x20000003) AM_RAM
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AM_RANGE(0x10180000, 0x1018ffff) AM_RAM AM_SHARE(1) // above 10188000 accessed at level end (game bug?)
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AM_RANGE(0x20000020, 0x20000023) AM_RAM
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AM_RANGE(0x20000000, 0x20000003) AM_READNOP // watchdog_r?
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AM_RANGE(0x20000024, 0x20000027) AM_RAM
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AM_RANGE(0x20000040, 0x20000043) AM_RAM
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AM_RANGE(0x20000010, 0x20000013) AM_DEVREADWRITE8("oki1", okim6295_r, okim6295_w, 0x00ff) // left
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AM_RANGE(0x20000044, 0x20000047) AM_RAM
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AM_RANGE(0x20000014, 0x20000017) AM_DEVREADWRITE8("oki2", okim6295_r, okim6295_w, 0x00ff) // left
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AM_RANGE(0x20000048, 0x2000004b) AM_RAM
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AM_RANGE(0x20000018, 0x2000001b) AM_DEVREADWRITE8("oki3", okim6295_r, okim6295_w, 0x00ff) // right
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AM_RANGE(0x2000004c, 0x2000004f) AM_READ(unk_r)
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AM_RANGE(0x2000001c, 0x2000001f) AM_DEVREADWRITE8("oki4", okim6295_r, okim6295_w, 0x00ff) // right
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AM_RANGE(0x20000050, 0x20000053) AM_RAM
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AM_RANGE(0x20000054, 0x20000057) AM_RAM
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AM_RANGE(0x20000020, 0x20000023) AM_READ ( skimaxx_unk1_r ) // units linking?
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AM_RANGE(0xfffc0000, 0xfffdffff) AM_RAM AM_MIRROR(0x00020000)
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AM_RANGE(0x20000024, 0x20000027) AM_WRITE( skimaxx_unk1_w ) // ""
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AM_RANGE(0x20000040, 0x20000043) AM_RAM // write
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AM_RANGE(0x20000044, 0x20000047) AM_READ_PORT( "DSW" )
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AM_RANGE(0x20000048, 0x2000004b) AM_READ_PORT( "COIN" )
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AM_RANGE(0x2000004c, 0x2000004f) AM_READ(unk_r) // bit 7, bit 0
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AM_RANGE(0x20000050, 0x20000057) AM_READ( skimaxx_analog_r ) AM_WRITENOP // read (0-1f), write motor?
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AM_RANGE(0xfffc0000, 0xffffffff) AM_RAM AM_MIRROR(0x00020000)
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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/*************************************
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/*************************************
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*
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*
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* Sub CPU memory map
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* Sub CPU memory map (Blitter control)
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*
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*
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*************************************/
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*************************************/
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|
|
||||||
static ADDRESS_MAP_START( 68030_2_map, ADDRESS_SPACE_PROGRAM, 32 )
|
static ADDRESS_MAP_START( 68030_2_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||||
AM_RANGE(0x00000000, 0x003fffff) AM_ROM
|
AM_RANGE(0x00000000, 0x003fffff) AM_ROM
|
||||||
AM_RANGE(0x40000000, 0x40000003) AM_RAM // Xilinx FPGA configuration write port?
|
|
||||||
AM_RANGE(0x50000000, 0x5007ffff) AM_RAM AM_BASE(&sprite_buffer) // Part of this is mixed with the TMS frame buffer
|
AM_RANGE(0x20000000, 0x2007ffff) AM_READ ( skimaxx_blitter_r ) // do blit
|
||||||
AM_RANGE(0xfffc0000, 0xfffc7fff) AM_RAM AM_SHARE(1)
|
AM_RANGE(0x30000000, 0x3000000f) AM_WRITE( skimaxx_blitter_w ) AM_BASE( &skimaxx_blitter_regs )
|
||||||
AM_RANGE(0xfffe0000, 0xffffffff) AM_RAM // I think this is banked with the shared RAM? (see CPU sync routines)
|
|
||||||
|
AM_RANGE(0x40000000, 0x40000003) AM_WRITE( skimaxx_fpga_ctrl_w ) AM_BASE( &skimaxx_fpga_ctrl )
|
||||||
|
|
||||||
|
AM_RANGE(0x50000000, 0x5007ffff) AM_RAMBANK(1) // background ram allocated here at video_start (skimaxx_bg_buffer_back/front)
|
||||||
|
// AM_RANGE(0xfffc0000, 0xfffc7fff) AM_RAM AM_SHARE(1)
|
||||||
|
AM_RANGE(0xfffc0000, 0xfffcffff) AM_RAM AM_SHARE(1)
|
||||||
|
// AM_RANGE(0xfffe0000, 0xffffffff) AM_RAM // I think this is banked with the shared RAM? (see CPU sync routines)
|
||||||
|
AM_RANGE(0xfffe0010, 0xfffeffff) AM_RAM // HACK
|
||||||
|
AM_RANGE(0xfffe0000, 0xfffeffff) AM_RAM AM_SHARE(1) // HACK
|
||||||
|
AM_RANGE(0xffff0000, 0xffffffff) AM_RAM
|
||||||
ADDRESS_MAP_END
|
ADDRESS_MAP_END
|
||||||
|
|
||||||
|
|
||||||
/*************************************
|
/*************************************
|
||||||
*
|
*
|
||||||
* Video CPU memory map
|
* Video CPU memory map (Text layer)
|
||||||
*
|
*
|
||||||
*************************************/
|
*************************************/
|
||||||
|
|
||||||
@ -169,7 +362,7 @@ static ADDRESS_MAP_START( tms_program_map, ADDRESS_SPACE_PROGRAM, 16 )
|
|||||||
AM_RANGE(0x00000000, 0x000100ff) AM_RAM
|
AM_RANGE(0x00000000, 0x000100ff) AM_RAM
|
||||||
AM_RANGE(0x00008000, 0x0003ffff) AM_RAM
|
AM_RANGE(0x00008000, 0x0003ffff) AM_RAM
|
||||||
AM_RANGE(0x00050000, 0x0005ffff) AM_RAM
|
AM_RANGE(0x00050000, 0x0005ffff) AM_RAM
|
||||||
AM_RANGE(0x00220000, 0x003fffff) AM_RAM AM_BASE(&frame_buffer)
|
AM_RANGE(0x00220000, 0x003fffff) AM_RAM AM_BASE(&fg_buffer)
|
||||||
AM_RANGE(0x02000000, 0x0200000f) AM_RAM
|
AM_RANGE(0x02000000, 0x0200000f) AM_RAM
|
||||||
AM_RANGE(0x02100000, 0x0210000f) AM_RAM
|
AM_RANGE(0x02100000, 0x0210000f) AM_RAM
|
||||||
AM_RANGE(0x04000000, 0x047fffff) AM_ROM AM_REGION("tmsgfx", 0)
|
AM_RANGE(0x04000000, 0x047fffff) AM_ROM AM_REGION("tmsgfx", 0)
|
||||||
@ -178,6 +371,44 @@ static ADDRESS_MAP_START( tms_program_map, ADDRESS_SPACE_PROGRAM, 16 )
|
|||||||
ADDRESS_MAP_END
|
ADDRESS_MAP_END
|
||||||
|
|
||||||
|
|
||||||
|
/*************************************
|
||||||
|
*
|
||||||
|
* Graphics decoding (for debug)
|
||||||
|
*
|
||||||
|
*************************************/
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
|
||||||
|
static const UINT32 texlayout_xoffset[512] =
|
||||||
|
{
|
||||||
|
STEP512(0,16)
|
||||||
|
};
|
||||||
|
|
||||||
|
static const UINT32 texlayout_yoffset[128] =
|
||||||
|
{
|
||||||
|
STEP128(0,512*16)
|
||||||
|
};
|
||||||
|
|
||||||
|
static const gfx_layout texlayout =
|
||||||
|
{
|
||||||
|
512, 128,
|
||||||
|
RGN_FRAC(1,1),
|
||||||
|
5,
|
||||||
|
{ 9,10,11,12,13 },
|
||||||
|
EXTENDED_XOFFS,
|
||||||
|
EXTENDED_YOFFS,
|
||||||
|
512*128*16,
|
||||||
|
texlayout_xoffset,
|
||||||
|
texlayout_yoffset
|
||||||
|
};
|
||||||
|
|
||||||
|
static GFXDECODE_START( skimaxx )
|
||||||
|
GFXDECODE_ENTRY( "blitter", 0, texlayout, 0, 1 )
|
||||||
|
GFXDECODE_END
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/*************************************
|
/*************************************
|
||||||
*
|
*
|
||||||
* Input definitions
|
* Input definitions
|
||||||
@ -185,8 +416,49 @@ ADDRESS_MAP_END
|
|||||||
*************************************/
|
*************************************/
|
||||||
|
|
||||||
static INPUT_PORTS_START( skimaxx )
|
static INPUT_PORTS_START( skimaxx )
|
||||||
PORT_START("DSW")
|
PORT_START("DSW") // 20000044.l & 0xff
|
||||||
// TODO
|
PORT_DIPNAME( 0x07, 0x07, DEF_STR( Unknown ) )
|
||||||
|
PORT_DIPSETTING( 0x05, "12" )
|
||||||
|
PORT_DIPSETTING( 0x04, "17" )
|
||||||
|
PORT_DIPSETTING( 0x03, "25" )
|
||||||
|
PORT_DIPSETTING( 0x02, "33" )
|
||||||
|
PORT_DIPSETTING( 0x01, "50" )
|
||||||
|
PORT_DIPSETTING( 0x07, "100" )
|
||||||
|
PORT_DIPSETTING( 0x06, "200" )
|
||||||
|
PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
|
||||||
|
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
|
||||||
|
PORT_DIPSETTING( 0x08, "0" )
|
||||||
|
PORT_DIPSETTING( 0x00, "1" )
|
||||||
|
PORT_DIPNAME( 0x70, 0x70, DEF_STR( Unknown ) )
|
||||||
|
PORT_DIPSETTING( 0x00, "2" )
|
||||||
|
PORT_DIPSETTING( 0x10, "4" )
|
||||||
|
PORT_DIPSETTING( 0x20, "8" )
|
||||||
|
PORT_DIPSETTING( 0x30, "10" )
|
||||||
|
PORT_DIPSETTING( 0x40, "12" )
|
||||||
|
PORT_DIPSETTING( 0x50, "15" )
|
||||||
|
PORT_DIPSETTING( 0x60, "20" )
|
||||||
|
PORT_DIPSETTING( 0x70, "30" )
|
||||||
|
PORT_DIPNAME( 0x80, 0x80, "Time For Super Course" )
|
||||||
|
PORT_DIPSETTING( 0x80, "50 s" ) // 3000
|
||||||
|
PORT_DIPSETTING( 0x00, "60 s" ) // 3600
|
||||||
|
|
||||||
|
PORT_START("COIN") // 20000048.l & 0xff
|
||||||
|
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||||
|
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||||
|
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) // ?
|
||||||
|
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 ) // coin
|
||||||
|
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 ) // coin
|
||||||
|
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) // start
|
||||||
|
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||||
|
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) // change course / letter
|
||||||
|
|
||||||
|
PORT_START("X")
|
||||||
|
PORT_BIT( 0x1f, 0x10, IPT_AD_STICK_X ) PORT_SENSITIVITY(10) PORT_KEYDELTA(1) PORT_MINMAX(0x00,0x1e) PORT_INVERT
|
||||||
|
|
||||||
|
PORT_START("Y")
|
||||||
|
PORT_BIT( 0x1f, 0x10, IPT_AD_STICK_Y ) PORT_SENSITIVITY(10) PORT_KEYDELTA(1) PORT_MINMAX(0x00,0x1e) PORT_INVERT
|
||||||
|
// PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(35) PORT_KEYDELTA(5)
|
||||||
|
|
||||||
INPUT_PORTS_END
|
INPUT_PORTS_END
|
||||||
|
|
||||||
|
|
||||||
@ -206,7 +478,7 @@ static const tms34010_config tms_config =
|
|||||||
FALSE, /* halt on reset */
|
FALSE, /* halt on reset */
|
||||||
"screen", /* the screen operated on */
|
"screen", /* the screen operated on */
|
||||||
50000000/8, /* pixel clock */
|
50000000/8, /* pixel clock */
|
||||||
1, /* pixels per clock */
|
2, /* pixels per clock */
|
||||||
skimaxx_scanline_update, /* scanline updater */
|
skimaxx_scanline_update, /* scanline updater */
|
||||||
skimaxx_tms_irq, /* generate interrupt */
|
skimaxx_tms_irq, /* generate interrupt */
|
||||||
skimaxx_to_shiftreg, /* write to shiftreg function */
|
skimaxx_to_shiftreg, /* write to shiftreg function */
|
||||||
@ -225,7 +497,6 @@ static MACHINE_RESET( skimaxx )
|
|||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/*************************************
|
/*************************************
|
||||||
*
|
*
|
||||||
* Machine driver
|
* Machine driver
|
||||||
@ -233,30 +504,55 @@ static MACHINE_RESET( skimaxx )
|
|||||||
*************************************/
|
*************************************/
|
||||||
|
|
||||||
static MACHINE_DRIVER_START( skimaxx )
|
static MACHINE_DRIVER_START( skimaxx )
|
||||||
MDRV_CPU_ADD("maincpu", M68020, XTAL_40MHz) // TODO: Should be a 68030!
|
MDRV_CPU_ADD("maincpu", M68EC030, XTAL_40MHz)
|
||||||
MDRV_CPU_PROGRAM_MAP(68030_1_map)
|
MDRV_CPU_PROGRAM_MAP(68030_1_map)
|
||||||
// MDRV_CPU_VBLANK_INT("screen", irq3_line_hold)
|
MDRV_CPU_VBLANK_INT("screen", irq3_line_hold) // 1,3,7 are identical, rest is RTE
|
||||||
|
|
||||||
MDRV_CPU_ADD("subcpu", M68020, XTAL_40MHz)
|
MDRV_CPU_ADD("subcpu", M68EC030, XTAL_40MHz)
|
||||||
MDRV_CPU_PROGRAM_MAP(68030_2_map) // TODO: Should be a 68030!
|
MDRV_CPU_PROGRAM_MAP(68030_2_map)
|
||||||
|
|
||||||
|
MDRV_MACHINE_RESET(skimaxx)
|
||||||
|
|
||||||
|
/* video hardware */
|
||||||
MDRV_CPU_ADD("tms", TMS34010, XTAL_50MHz)
|
MDRV_CPU_ADD("tms", TMS34010, XTAL_50MHz)
|
||||||
MDRV_CPU_CONFIG(tms_config)
|
MDRV_CPU_CONFIG(tms_config)
|
||||||
MDRV_CPU_PROGRAM_MAP(tms_program_map)
|
MDRV_CPU_PROGRAM_MAP(tms_program_map)
|
||||||
|
|
||||||
MDRV_MACHINE_RESET(skimaxx)
|
|
||||||
|
|
||||||
MDRV_SCREEN_ADD("screen", RASTER)
|
MDRV_SCREEN_ADD("screen", RASTER)
|
||||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||||
MDRV_SCREEN_RAW_PARAMS(40000000/4, 156*4, 0, 100*4, 328, 0, 300) // TODO - Wrong but TMS overrides it anyway
|
// MDRV_SCREEN_RAW_PARAMS(40000000/4, 156*4, 0, 100*4, 328, 0, 300) // TODO - Wrong but TMS overrides it anyway
|
||||||
|
MDRV_SCREEN_REFRESH_RATE(60)
|
||||||
|
MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
|
||||||
|
MDRV_SCREEN_SIZE(0x400, 0x100)
|
||||||
|
MDRV_SCREEN_VISIBLE_AREA(0, 0x280-1, 0, 0xf0-1)
|
||||||
|
|
||||||
|
MDRV_VIDEO_START(skimaxx)
|
||||||
|
// MDRV_VIDEO_UPDATE(tms340x0)
|
||||||
|
MDRV_VIDEO_UPDATE(skimaxx)
|
||||||
|
|
||||||
|
// MDRV_GFXDECODE( skimaxx )
|
||||||
|
|
||||||
MDRV_PALETTE_INIT(RRRRR_GGGGG_BBBBB)
|
MDRV_PALETTE_INIT(RRRRR_GGGGG_BBBBB)
|
||||||
MDRV_PALETTE_LENGTH(32768)
|
MDRV_PALETTE_LENGTH(32768)
|
||||||
|
|
||||||
MDRV_SPEAKER_STANDARD_MONO("mono")
|
/* sound hardware */
|
||||||
|
MDRV_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
|
||||||
|
|
||||||
MDRV_VIDEO_START(skimaxx)
|
MDRV_SOUND_ADD("oki1", OKIM6295, XTAL_4MHz) // ?
|
||||||
MDRV_VIDEO_UPDATE(tms340x0)
|
MDRV_SOUND_CONFIG(okim6295_interface_pin7low) // ?
|
||||||
|
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
|
||||||
|
|
||||||
|
MDRV_SOUND_ADD("oki2", OKIM6295, XTAL_4MHz/2) // ?
|
||||||
|
MDRV_SOUND_CONFIG(okim6295_interface_pin7high) // ?
|
||||||
|
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
|
||||||
|
|
||||||
|
MDRV_SOUND_ADD("oki3", OKIM6295, XTAL_4MHz) // ?
|
||||||
|
MDRV_SOUND_CONFIG(okim6295_interface_pin7low) // ?
|
||||||
|
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
|
||||||
|
|
||||||
|
MDRV_SOUND_ADD("oki4", OKIM6295, XTAL_4MHz/2) // ?
|
||||||
|
MDRV_SOUND_CONFIG(okim6295_interface_pin7high) // ?
|
||||||
|
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
|
||||||
MACHINE_DRIVER_END
|
MACHINE_DRIVER_END
|
||||||
|
|
||||||
|
|
||||||
@ -283,29 +579,29 @@ ROM_START( skimaxx )
|
|||||||
ROM_LOAD16_BYTE( "vc8v-2_0", 0x000000, 0x80000, CRC(a6e9ef81) SHA1(59a0fb149e17d3773adb980428a0b107647bd4fa) )
|
ROM_LOAD16_BYTE( "vc8v-2_0", 0x000000, 0x80000, CRC(a6e9ef81) SHA1(59a0fb149e17d3773adb980428a0b107647bd4fa) )
|
||||||
ROM_LOAD16_BYTE( "vc9v-2_0", 0x000001, 0x80000, CRC(b1e8ba65) SHA1(b91cf93ecd9b6067664780ab2c1b69f632c7ae05) )
|
ROM_LOAD16_BYTE( "vc9v-2_0", 0x000001, 0x80000, CRC(b1e8ba65) SHA1(b91cf93ecd9b6067664780ab2c1b69f632c7ae05) )
|
||||||
|
|
||||||
ROM_REGION( 0x600000, "tmsgfx", 0 )
|
ROM_REGION( 0x100000, "tmsgfx", 0 )
|
||||||
ROM_LOAD16_BYTE( "vc10v2_0", 0x000000, 0x80000, CRC(433651cd) SHA1(9b9801703d16adbbca2b03e1714490fb166d48a0) )
|
ROM_LOAD16_BYTE( "vc10v2_0", 0x000000, 0x80000, CRC(433651cd) SHA1(9b9801703d16adbbca2b03e1714490fb166d48a0) )
|
||||||
ROM_LOAD16_BYTE( "vc11v2_0", 0x000001, 0x80000, CRC(a906fc72) SHA1(c61ad560f203c7f507cc7b7dc8834f529a6501a7) )
|
ROM_LOAD16_BYTE( "vc11v2_0", 0x000001, 0x80000, CRC(a906fc72) SHA1(c61ad560f203c7f507cc7b7dc8834f529a6501a7) )
|
||||||
|
|
||||||
ROM_REGION( 0x600000, "gfx", 0 )
|
ROM_REGION16_LE( 0x600000, "blitter", 0 )
|
||||||
ROM_LOAD16_BYTE( "ve5v-2_0", 0x000000, 0x100000, CRC(b95544a3) SHA1(1ad49da54d36543229e241887c3dd8411ef5c89a) )
|
ROM_LOAD16_BYTE( "ve5v-2_0", 0x000000, 0x100000, CRC(b95544a3) SHA1(1ad49da54d36543229e241887c3dd8411ef5c89a) )
|
||||||
ROM_LOAD16_BYTE( "ve6v-2_0", 0x000001, 0x100000, CRC(d98bf89a) SHA1(f7fd66487f7696b53ee90a4cf45a810ec791df59) )
|
ROM_LOAD16_BYTE( "ve6v-2_0", 0x000001, 0x100000, CRC(d98bf89a) SHA1(f7fd66487f7696b53ee90a4cf45a810ec791df59) )
|
||||||
ROM_LOAD16_BYTE( "ve7v-2_0", 0x200000, 0x100000, CRC(a927716b) SHA1(0189d7b08b65b6a8a8d4c3e2affe93612db38155) )
|
ROM_LOAD16_BYTE( "ve10v2_0", 0x200000, 0x100000, CRC(c2a16a62) SHA1(3663c19a6517b0a01fb454523b995be3cdf2e4b3) )
|
||||||
ROM_LOAD16_BYTE( "ve8v-2_0", 0x200001, 0x100000, CRC(ad8ed4a4) SHA1(5d1339b3d6ce59fea062273fa2da35988ba94a80) )
|
ROM_LOAD16_BYTE( "ve9v-2_0", 0x200001, 0x100000, CRC(587b364d) SHA1(b53412bdcc804727990d959e5b2399a7e5e7fbf3) )
|
||||||
ROM_LOAD16_BYTE( "ve9v-2_0", 0x400000, 0x100000, CRC(587b364d) SHA1(b53412bdcc804727990d959e5b2399a7e5e7fbf3) )
|
ROM_LOAD16_BYTE( "ve7v-2_0", 0x400000, 0x100000, CRC(a927716b) SHA1(0189d7b08b65b6a8a8d4c3e2affe93612db38155) )
|
||||||
ROM_LOAD16_BYTE( "ve10v2_0", 0x400001, 0x100000, CRC(c2a16a62) SHA1(3663c19a6517b0a01fb454523b995be3cdf2e4b3) )
|
ROM_LOAD16_BYTE( "ve8v-2_0", 0x400001, 0x100000, CRC(ad8ed4a4) SHA1(5d1339b3d6ce59fea062273fa2da35988ba94a80) )
|
||||||
|
|
||||||
ROM_REGION( 0x80000, "oki1", 0 )
|
ROM_REGION( 0x80000, "oki1", 0 )
|
||||||
ROM_LOAD( "main2_0.u2", 0x000000, 0x80000, CRC(c84b3c46) SHA1(b956358518495aa822a5b699cbad1abac212dd09) )
|
|
||||||
|
|
||||||
ROM_REGION( 0x80000, "oki2", 0 )
|
|
||||||
ROM_LOAD( "main2_0.u4", 0x000000, 0x80000, CRC(c84b3c46) SHA1(b956358518495aa822a5b699cbad1abac212dd09) )
|
|
||||||
|
|
||||||
ROM_REGION( 0x80000, "oki3", 0 )
|
|
||||||
ROM_LOAD( "main2_0.u3", 0x000000, 0x80000, CRC(24d8c6ad) SHA1(06f51a4c380c91c930d646826246f62c4e1f9cda) )
|
ROM_LOAD( "main2_0.u3", 0x000000, 0x80000, CRC(24d8c6ad) SHA1(06f51a4c380c91c930d646826246f62c4e1f9cda) )
|
||||||
|
|
||||||
ROM_REGION( 0x80000, "oki4", 0 )
|
ROM_REGION( 0x80000, "oki2", 0 )
|
||||||
|
ROM_LOAD( "main2_0.u2", 0x000000, 0x80000, CRC(c84b3c46) SHA1(b956358518495aa822a5b699cbad1abac212dd09) ) // identical to main2_0.u4
|
||||||
|
|
||||||
|
ROM_REGION( 0x80000, "oki3", 0 )
|
||||||
ROM_LOAD( "main2_0.u5", 0x000000, 0x80000, CRC(e2ba07ad) SHA1(cf82753975f7b6756cca4e10b5372e00135440bf) )
|
ROM_LOAD( "main2_0.u5", 0x000000, 0x80000, CRC(e2ba07ad) SHA1(cf82753975f7b6756cca4e10b5372e00135440bf) )
|
||||||
|
|
||||||
|
ROM_REGION( 0x80000, "oki4", 0 )
|
||||||
|
ROM_LOAD( "main2_0.u4", 0x000000, 0x80000, CRC(c84b3c46) SHA1(b956358518495aa822a5b699cbad1abac212dd09) ) // identical to main2_0.u2
|
||||||
ROM_END
|
ROM_END
|
||||||
|
|
||||||
|
|
||||||
@ -315,4 +611,4 @@ ROM_END
|
|||||||
*
|
*
|
||||||
*************************************/
|
*************************************/
|
||||||
|
|
||||||
GAME( 1996, skimaxx, 0, skimaxx, skimaxx, 0, ROT0, "Kyle Hodgetts/ICE", "Skimaxx", GAME_NOT_WORKING | GAME_NO_SOUND )
|
GAME( 1996, skimaxx, 0, skimaxx, skimaxx, 0, ROT0, "Kyle Hodgetts / ICE", "Skimaxx", GAME_IMPERFECT_GRAPHICS )
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user