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Revert " AICA Cleanups & Internalize CPU Core (#3423)"

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This reverts commit 36eb386c19.
This commit is contained in:
R. Belmont 2018-04-07 14:29:24 -04:00 committed by GitHub
parent 36eb386c19
commit 4aefc37f72
12 changed files with 453 additions and 488 deletions
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516
src/devices/sound/aica.cpp
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@ -8,7 +8,6 @@
- No FM mode - No FM mode
- A third sample format (ADPCM) has been added - A third sample format (ADPCM) has been added
- Some minor other tweeks (no EGHOLD, slighly more capable DSP) - Some minor other tweeks (no EGHOLD, slighly more capable DSP)
- Internal ARM7DI Core
*/ */
#include "emu.h" #include "emu.h"
@ -42,56 +41,42 @@
#define LPCTL(slot) ((slot->udata.data[0x0]>>0x9)&0x0001) #define LPCTL(slot) ((slot->udata.data[0x0]>>0x9)&0x0001)
#define PCMS(slot) ((slot->udata.data[0x0]>>0x7)&0x0003) #define PCMS(slot) ((slot->udata.data[0x0]>>0x7)&0x0003)
#define SA(slot) (((slot->udata.data[0x0]&0x7f)<<16)|(slot->udata.data[0x4/2])) #define SA(slot) (((slot->udata.data[0x0]&0x7F)<<16)|(slot->udata.data[0x4/2]))
#define LSA(slot) (slot->udata.data[0x8/2]) #define LSA(slot) (slot->udata.data[0x8/2])
#define LEA(slot) (slot->udata.data[0xc/2]) #define LEA(slot) (slot->udata.data[0xc/2])
#define D2R(slot) ((slot->udata.data[0x10/2]>>0xB)&0x001f) #define D2R(slot) ((slot->udata.data[0x10/2]>>0xB)&0x001F)
#define D1R(slot) ((slot->udata.data[0x10/2]>>0x6)&0x001f) #define D1R(slot) ((slot->udata.data[0x10/2]>>0x6)&0x001F)
#define AR(slot) ((slot->udata.data[0x10/2]>>0x0)&0x001f) #define AR(slot) ((slot->udata.data[0x10/2]>>0x0)&0x001F)
#define LPSLNK(slot) ((slot->udata.data[0x14/2]>>0x0)&0x4000) #define LPSLNK(slot) ((slot->udata.data[0x14/2]>>0x0)&0x4000)
#define KRS(slot) ((slot->udata.data[0x14/2]>>0xA)&0x000f) #define KRS(slot) ((slot->udata.data[0x14/2]>>0xA)&0x000F)
#define DL(slot) ((slot->udata.data[0x14/2]>>0x5)&0x001f) #define DL(slot) ((slot->udata.data[0x14/2]>>0x5)&0x001F)
#define RR(slot) ((slot->udata.data[0x14/2]>>0x0)&0x001f) #define RR(slot) ((slot->udata.data[0x14/2]>>0x0)&0x001F)
#define TL(slot) ((slot->udata.data[0x28/2]>>0x8)&0x00ff) #define TL(slot) ((slot->udata.data[0x28/2]>>0x8)&0x00FF)
#define OCT(slot) ((slot->udata.data[0x18/2]>>0xB)&0x000f) #define OCT(slot) ((slot->udata.data[0x18/2]>>0xB)&0x000F)
#define FNS(slot) ((slot->udata.data[0x18/2]>>0x0)&0x03FF) #define FNS(slot) ((slot->udata.data[0x18/2]>>0x0)&0x03FF)
#define LFORE(slot) ((slot->udata.data[0x1c/2]>>0x0)&0x8000) #define LFORE(slot) ((slot->udata.data[0x1c/2]>>0x0)&0x8000)
#define LFOF(slot) ((slot->udata.data[0x1c/2]>>0xA)&0x001f) #define LFOF(slot) ((slot->udata.data[0x1c/2]>>0xA)&0x001F)
#define PLFOWS(slot) ((slot->udata.data[0x1c/2]>>0x8)&0x0003) #define PLFOWS(slot) ((slot->udata.data[0x1c/2]>>0x8)&0x0003)
#define PLFOS(slot) ((slot->udata.data[0x1c/2]>>0x5)&0x0007) #define PLFOS(slot) ((slot->udata.data[0x1c/2]>>0x5)&0x0007)
#define ALFOWS(slot) ((slot->udata.data[0x1c/2]>>0x3)&0x0003) #define ALFOWS(slot) ((slot->udata.data[0x1c/2]>>0x3)&0x0003)
#define ALFOS(slot) ((slot->udata.data[0x1c/2]>>0x0)&0x0007) #define ALFOS(slot) ((slot->udata.data[0x1c/2]>>0x0)&0x0007)
#define ISEL(slot) ((slot->udata.data[0x20/2]>>0x0)&0x000f) #define ISEL(slot) ((slot->udata.data[0x20/2]>>0x0)&0x000F)
#define IMXL(slot) ((slot->udata.data[0x20/2]>>0x4)&0x000f) #define IMXL(slot) ((slot->udata.data[0x20/2]>>0x4)&0x000F)
#define DISDL(slot) ((slot->udata.data[0x24/2]>>0x8)&0x000f) #define DISDL(slot) ((slot->udata.data[0x24/2]>>0x8)&0x000F)
#define DIPAN(slot) ((slot->udata.data[0x24/2]>>0x0)&0x001f) #define DIPAN(slot) ((slot->udata.data[0x24/2]>>0x0)&0x001F)
#define EFSDL(slot) ((m_EFSPAN[slot*4]>>8)&0x000f) #define EFSDL(slot) ((m_EFSPAN[slot*4]>>8)&0x000f)
#define EFPAN(slot) ((m_EFSPAN[slot*4]>>0)&0x001f) #define EFPAN(slot) ((m_EFSPAN[slot*4]>>0)&0x001f)
/*
Unimplemented Registers
#define Q(slot) ((slot->udata.data[0x28/2]>>0x0)&0x001f) // resonance; (0.75 * Q - 3)dB
#define FLV0(slot) ((slot->udata.data[0x2c/2]>>0x0)&0x1fff) // FLV0 : Cutoff frequency at attack start
#define FLV1(slot) ((slot->udata.data[0x30/2]>>0x0)&0x1fff) // FLV1 : Cutoff frequency at attack End(decay start)
#define FLV2(slot) ((slot->udata.data[0x34/2]>>0x0)&0x1fff) // FLV2 : Cutoff frequency at decay End(sustain start)
#define FLV3(slot) ((slot->udata.data[0x38/2]>>0x0)&0x1fff) // FLV3 : Cutoff frequency at KOFF
#define FLV4(slot) ((slot->udata.data[0x3c/2]>>0x0)&0x1fff) // FLV4 : Cutoff frequency after release
#define FAR(slot) ((slot->udata.data[0x40/2]>>0x8)&0x001f)
#define FD1R(slot) ((slot->udata.data[0x40/2]>>0x0)&0x001f)
#define FD2R(slot) ((slot->udata.data[0x44/2]>>0x8)&0x001f)
#define FRR(slot) ((slot->udata.data[0x44/2]>>0x0)&0x001f)
*/
//Envelope times in ms //Envelope times in ms
static constexpr double ARTimes[64]={100000/*infinity*/,100000/*infinity*/,8100.0,6900.0,6000.0,4800.0,4000.0,3400.0,3000.0,2400.0,2000.0,1700.0,1500.0, static constexpr double ARTimes[64]={100000/*infinity*/,100000/*infinity*/,8100.0,6900.0,6000.0,4800.0,4000.0,3400.0,3000.0,2400.0,2000.0,1700.0,1500.0,
1200.0,1000.0,860.0,760.0,600.0,500.0,430.0,380.0,300.0,250.0,220.0,190.0,150.0,130.0,110.0,95.0, 1200.0,1000.0,860.0,760.0,600.0,500.0,430.0,380.0,300.0,250.0,220.0,190.0,150.0,130.0,110.0,95.0,
@ -102,10 +87,9 @@ static constexpr double DRTimes[64]={100000/*infinity*/,100000/*infinity*/,11820
920.0,790.0,690.0,550.0,460.0,390.0,340.0,270.0,230.0,200.0,170.0,140.0,110.0,98.0,85.0,68.0,57.0,49.0,43.0,34.0, 920.0,790.0,690.0,550.0,460.0,390.0,340.0,270.0,230.0,200.0,170.0,140.0,110.0,98.0,85.0,68.0,57.0,49.0,43.0,34.0,
28.0,25.0,22.0,18.0,14.0,12.0,11.0,8.5,7.1,6.1,5.4,4.3,3.6,3.1}; 28.0,25.0,22.0,18.0,14.0,12.0,11.0,8.5,7.1,6.1,5.4,4.3,3.6,3.1};
#define MN(aica) ((m_udata.data[0]>>0x0)&0x8000) #define MEM4B(aica) ((m_udata.data[0]>>0x0)&0x0200)
#define MEM8B(aica) ((m_udata.data[0]>>0x0)&0x0200)
#define DAC18B(aica) ((m_udata.data[0]>>0x0)&0x0100) #define DAC18B(aica) ((m_udata.data[0]>>0x0)&0x0100)
#define MVOL(aica) ((m_udata.data[0]>>0x0)&0x000f) #define MVOL(aica) ((m_udata.data[0]>>0x0)&0x000F)
#define RBL(aica) ((m_udata.data[2]>>0xD)&0x0003) #define RBL(aica) ((m_udata.data[2]>>0xD)&0x0003)
#define RBP(aica) ((m_udata.data[2]>>0x0)&0x0fff) #define RBP(aica) ((m_udata.data[2]>>0x0)&0x0fff)
#define MOFULL(aica) ((m_udata.data[4]>>0x0)&0x1000) #define MOFULL(aica) ((m_udata.data[4]>>0x0)&0x1000)
@ -115,7 +99,7 @@ static constexpr double DRTimes[64]={100000/*infinity*/,100000/*infinity*/,11820
#define MIEMPTY(aica) ((m_udata.data[4]>>0x0)&0x0100) #define MIEMPTY(aica) ((m_udata.data[4]>>0x0)&0x0100)
#define AFSEL(aica) ((m_udata.data[0xc/2]>>0x0)&0x4000) #define AFSEL(aica) ((m_udata.data[0xc/2]>>0x0)&0x4000)
#define MSLC(aica) ((m_udata.data[0xc/2]>>0x8)&0x3f) #define MSLC(aica) ((m_udata.data[0xc/2]>>0x8)&0x3F)
#define SCILV0(aica) ((m_udata.data[0xa8/2]>>0x0)&0xff) #define SCILV0(aica) ((m_udata.data[0xa8/2]>>0x0)&0xff)
#define SCILV1(aica) ((m_udata.data[0xac/2]>>0x0)&0xff) #define SCILV1(aica) ((m_udata.data[0xac/2]>>0x0)&0xff)
@ -124,7 +108,6 @@ static constexpr double DRTimes[64]={100000/*infinity*/,100000/*infinity*/,11820
#define MCIEB(aica) ((m_udata.data[0xb4/2]>>0x0)&0xff) #define MCIEB(aica) ((m_udata.data[0xb4/2]>>0x0)&0xff)
#define MCIPD(aica) ((m_udata.data[0xb8/2]>>0x0)&0xff) #define MCIPD(aica) ((m_udata.data[0xb8/2]>>0x0)&0xff)
#define MCIRE(aica) ((m_udata.data[0xbc/2]>>0x0)&0xff) #define MCIRE(aica) ((m_udata.data[0xbc/2]>>0x0)&0xff)
#define MCIEB(aica) ((m_udata.data[0xb4/2]>>0x0)&0xff)
#define SCIEX0 0 #define SCIEX0 0
#define SCIEX1 1 #define SCIEX1 1
@ -150,29 +133,16 @@ unsigned char aica_device::DecodeSCI(unsigned char irq)
return SCI; return SCI;
} }
void aica_device::InterruptUpdate(int line, int state)
{
switch(line)
{
case 0: m_armirq->in_w<0>(state); break;
case 1: m_armirq->in_w<1>(state); break;
case 2: m_armirq->in_w<2>(state); break;
case 3: m_armirq->in_w<3>(state); break;
case 4: m_armirq->in_w<4>(state); break;
case 5: m_armirq->in_w<5>(state); break;
case 6: m_armirq->in_w<6>(state); break;
case 7: m_armirq->in_w<7>(state); break;
}
}
void aica_device::ResetInterrupts() void aica_device::ResetInterrupts()
{ {
#if 0
uint32_t reset = m_udata.data[0xa4/2]; uint32_t reset = m_udata.data[0xa4/2];
if (reset & 0x40) if (reset & 0x40)
InterruptUpdate(m_IrqTimA, CLEAR_LINE); m_irq_cb(-m_IrqTimA);
if (reset & 0x180) if (reset & 0x180)
InterruptUpdate(m_IrqTimBC, CLEAR_LINE); m_irq_cb(-m_IrqTimBC);
#endif
} }
void aica_device::CheckPendingIRQ() void aica_device::CheckPendingIRQ()
@ -183,7 +153,7 @@ void aica_device::CheckPendingIRQ()
if(m_MidiW!=m_MidiR) if(m_MidiW!=m_MidiR)
{ {
m_IRQL = m_IrqMidi; m_IRQL = m_IrqMidi;
InterruptUpdate(m_IrqMidi, ASSERT_LINE); m_irq_cb(1);
return; return;
} }
if(!pend) if(!pend)
@ -192,21 +162,21 @@ void aica_device::CheckPendingIRQ()
if(en&0x40) if(en&0x40)
{ {
m_IRQL = m_IrqTimA; m_IRQL = m_IrqTimA;
InterruptUpdate(m_IrqTimA, ASSERT_LINE); m_irq_cb(1);
return; return;
} }
if(pend&0x80) if(pend&0x80)
if(en&0x80) if(en&0x80)
{ {
m_IRQL = m_IrqTimBC; m_IRQL = m_IrqTimBC;
InterruptUpdate(m_IrqTimBC, ASSERT_LINE); m_irq_cb(1);
return; return;
} }
if(pend&0x100) if(pend&0x100)
if(en&0x100) if(en&0x100)
{ {
m_IRQL = m_IrqTimBC; m_IRQL = m_IrqTimBC;
InterruptUpdate(m_IrqTimBC, ASSERT_LINE); m_irq_cb(1);
return; return;
} }
} }
@ -222,7 +192,7 @@ void aica_device::CheckPendingIRQ_SH4()
TIMER_CALLBACK_MEMBER( aica_device::timerA_cb ) TIMER_CALLBACK_MEMBER( aica_device::timerA_cb )
{ {
m_TimCnt[0] = 0xffff; m_TimCnt[0] = 0xFFFF;
m_udata.data[0xa0/2]|=0x40; m_udata.data[0xa0/2]|=0x40;
m_mcipd |= 0x40; m_mcipd |= 0x40;
m_udata.data[0x90/2]&=0xff00; m_udata.data[0x90/2]&=0xff00;
@ -235,7 +205,7 @@ TIMER_CALLBACK_MEMBER( aica_device::timerA_cb )
TIMER_CALLBACK_MEMBER( aica_device::timerB_cb ) TIMER_CALLBACK_MEMBER( aica_device::timerB_cb )
{ {
m_TimCnt[1] = 0xffff; m_TimCnt[1] = 0xFFFF;
m_udata.data[0xa0/2]|=0x80; m_udata.data[0xa0/2]|=0x80;
m_mcipd |= 0x80; m_mcipd |= 0x80;
m_udata.data[0x94/2]&=0xff00; m_udata.data[0x94/2]&=0xff00;
@ -247,7 +217,7 @@ TIMER_CALLBACK_MEMBER( aica_device::timerB_cb )
TIMER_CALLBACK_MEMBER( aica_device::timerC_cb ) TIMER_CALLBACK_MEMBER( aica_device::timerC_cb )
{ {
m_TimCnt[2] = 0xffff; m_TimCnt[2] = 0xFFFF;
m_udata.data[0xa0/2]|=0x100; m_udata.data[0xa0/2]|=0x100;
m_mcipd |= 0x100; m_mcipd |= 0x100;
m_udata.data[0x98/2]&=0xff00; m_udata.data[0x98/2]&=0xff00;
@ -295,6 +265,7 @@ void aica_device::Compute_EG(AICA_SLOT *slot)
slot->EG.D1R=Get_DR(rate,D1R(slot)); slot->EG.D1R=Get_DR(rate,D1R(slot));
slot->EG.D2R=Get_DR(rate,D2R(slot)); slot->EG.D2R=Get_DR(rate,D2R(slot));
slot->EG.RR=Get_RR(rate,RR(slot)); slot->EG.RR=Get_RR(rate,RR(slot));
slot->EG.RR=Get_RR(rate,RR(slot));
slot->EG.DL=0x1f-DL(slot); slot->EG.DL=0x1f-DL(slot);
} }
@ -357,6 +328,7 @@ uint32_t aica_device::Step(AICA_SLOT *slot)
return Fn; return Fn;
} }
void aica_device::Compute_LFO(AICA_SLOT *slot) void aica_device::Compute_LFO(AICA_SLOT *slot)
{ {
if(PLFOS(slot)!=0) if(PLFOS(slot)!=0)
@ -380,7 +352,7 @@ void aica_device::InitADPCM(int *PrevSignal, int *PrevQuant)
signed short aica_device::DecodeADPCM(int *PrevSignal, unsigned char Delta, int *PrevQuant) signed short aica_device::DecodeADPCM(int *PrevSignal, unsigned char Delta, int *PrevQuant)
{ {
int x = (*PrevQuant * quant_mul[Delta & 7]) / 8; int x = (*PrevQuant * quant_mul[Delta & 7]) / 8;
if (x > 0x7fff) x = 0x7fff; if (x > 0x7FFF) x = 0x7FFF;
if (Delta & 8) x = -x; if (Delta & 8) x = -x;
x += *PrevSignal; x += *PrevSignal;
#if 0 // older implementation #if 0 // older implementation
@ -446,13 +418,16 @@ void aica_device::Init()
m_MidiOutR=m_MidiOutW=0; m_MidiOutR=m_MidiOutW=0;
// get AICA RAM // get AICA RAM
m_AICARAM = m_ram->pointer(); if (m_ram_region != nullptr)
m_AICARAM += m_roffset; {
m_AICARAM_LENGTH = m_ram->size(); m_AICARAM = m_ram_region->base();
m_RAM_MASK = m_AICARAM_LENGTH-1; m_AICARAM += m_roffset;
m_RAM_MASK16 = m_RAM_MASK & ~1; m_AICARAM_LENGTH = m_ram_region->bytes();
m_DSP.AICARAM = (uint16_t *)m_AICARAM; m_RAM_MASK = m_AICARAM_LENGTH-1;
m_DSP.AICARAM_LENGTH = m_AICARAM_LENGTH/2; m_RAM_MASK16 = m_RAM_MASK & 0x7ffffe;
m_DSP.AICARAM = (uint16_t *)m_AICARAM;
m_DSP.AICARAM_LENGTH = m_AICARAM_LENGTH/2;
}
m_timerA = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(aica_device::timerA_cb), this)); m_timerA = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(aica_device::timerA_cb), this));
m_timerB = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(aica_device::timerB_cb), this)); m_timerB = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(aica_device::timerB_cb), this));
@ -469,7 +444,7 @@ void aica_device::Init()
{ {
int iTL =(i>>0x0)&0xff; int iTL =(i>>0x0)&0xff;
int iPAN=(i>>0x8)&0x1f; int iPAN=(i>>0x8)&0x1f;
int iSDL=(i>>0xD)&0x0f; int iSDL=(i>>0xD)&0x0F;
float TL; float TL;
float SegaDB=0; float SegaDB=0;
float fSDL; float fSDL;
@ -548,6 +523,8 @@ void aica_device::Init()
} }
AICALFO_Init(); AICALFO_Init();
m_buffertmpl=make_unique_clear<int32_t[]>(44100);
m_buffertmpr=make_unique_clear<int32_t[]>(44100);
// no "pend" // no "pend"
m_udata.data[0xa0/2] = 0; m_udata.data[0xa0/2] = 0;
@ -677,49 +654,58 @@ void aica_device::UpdateReg(address_space &space, int reg)
case 0x90: case 0x90:
case 0x91: case 0x91:
uint32_t time; if(m_master)
m_TimPris[0]=1<<((m_udata.data[0x90/2]>>8)&0x7);
m_TimCnt[0]=(m_udata.data[0x90/2]&0xff)<<8;
if ((m_udata.data[0x90/2]&0xff) != 255)
{ {
time = (m_clock / m_TimPris[0]) / (255-(m_udata.data[0x90/2]&0xff)); uint32_t time;
if (time)
m_TimPris[0]=1<<((m_udata.data[0x90/2]>>8)&0x7);
m_TimCnt[0]=(m_udata.data[0x90/2]&0xff)<<8;
if ((m_udata.data[0x90/2]&0xff) != 255)
{ {
m_timerA->adjust(attotime::from_ticks(768, time)); time = (44100 / m_TimPris[0]) / (255-(m_udata.data[0x90/2]&0xff));
if (time)
{
m_timerA->adjust(attotime::from_hz(time));
}
} }
} }
break; break;
case 0x94: case 0x94:
case 0x95: case 0x95:
uint32_t time; if(m_master)
m_TimPris[1]=1<<((m_udata.data[0x94/2]>>8)&0x7);
m_TimCnt[1]=(m_udata.data[0x94/2]&0xff)<<8;
if ((m_udata.data[0x94/2]&0xff) != 255)
{ {
time = (m_clock / m_TimPris[1]) / (255-(m_udata.data[0x94/2]&0xff)); uint32_t time;
if (time)
m_TimPris[1]=1<<((m_udata.data[0x94/2]>>8)&0x7);
m_TimCnt[1]=(m_udata.data[0x94/2]&0xff)<<8;
if ((m_udata.data[0x94/2]&0xff) != 255)
{ {
m_timerB->adjust(attotime::from_ticks(768, time)); time = (44100 / m_TimPris[1]) / (255-(m_udata.data[0x94/2]&0xff));
if (time)
{
m_timerB->adjust(attotime::from_hz(time));
}
} }
} }
break; break;
case 0x98: case 0x98:
case 0x99: case 0x99:
uint32_t time; if(m_master)
m_TimPris[2]=1<<((m_udata.data[0x98/2]>>8)&0x7);
m_TimCnt[2]=(m_udata.data[0x98/2]&0xff)<<8;
if ((m_udata.data[0x98/2]&0xff) != 255)
{ {
time = (m_clock / m_TimPris[2]) / (255-(m_udata.data[0x98/2]&0xff)); uint32_t time;
if (time)
m_TimPris[2]=1<<((m_udata.data[0x98/2]>>8)&0x7);
m_TimCnt[2]=(m_udata.data[0x98/2]&0xff)<<8;
if ((m_udata.data[0x98/2]&0xff) != 255)
{ {
m_timerC->adjust(attotime::from_ticks(768, time)); time = (44100 / m_TimPris[2]) / (255-(m_udata.data[0x98/2]&0xff));
if (time)
{
m_timerC->adjust(attotime::from_hz(time));
}
} }
} }
break; break;
@ -733,22 +719,25 @@ void aica_device::UpdateReg(address_space &space, int reg)
case 0xa4: //SCIRE case 0xa4: //SCIRE
case 0xa5: case 0xa5:
m_udata.data[0xa0/2] &= ~m_udata.data[0xa4/2]; if(m_master)
ResetInterrupts(); {
m_udata.data[0xa0/2] &= ~m_udata.data[0xa4/2];
ResetInterrupts();
// behavior from real hardware (SCSP, assumed to carry over): if you SCIRE a timer that's expired, // behavior from real hardware (SCSP, assumed to carry over): if you SCIRE a timer that's expired,
// it'll immediately pop up again // it'll immediately pop up again
if (m_TimCnt[0] >= 0xff00) if (m_TimCnt[0] >= 0xff00)
{ {
m_udata.data[0xa0/2] |= 0x40; m_udata.data[0xa0/2] |= 0x40;
} }
if (m_TimCnt[1] >= 0xff00) if (m_TimCnt[1] >= 0xff00)
{ {
m_udata.data[0xa0/2] |= 0x80; m_udata.data[0xa0/2] |= 0x80;
} }
if (m_TimCnt[2] >= 0xff00) if (m_TimCnt[2] >= 0xff00)
{ {
m_udata.data[0xa0/2] |= 0x100; m_udata.data[0xa0/2] |= 0x100;
}
} }
break; break;
case 0xa8: case 0xa8:
@ -757,9 +746,12 @@ void aica_device::UpdateReg(address_space &space, int reg)
case 0xad: case 0xad:
case 0xb0: case 0xb0:
case 0xb1: case 0xb1:
m_IrqTimA=DecodeSCI(SCITMA); if(m_master)
m_IrqTimBC=DecodeSCI(SCITMB); {
m_IrqMidi=DecodeSCI(SCIMID); m_IrqTimA=DecodeSCI(SCITMA);
m_IrqTimBC=DecodeSCI(SCITMB);
m_IrqMidi=DecodeSCI(SCIMID);
}
break; break;
case 0xb4: //MCIEB case 0xb4: //MCIEB
@ -793,17 +785,13 @@ void aica_device::UpdateRegR(address_space &space, int reg)
{ {
switch(reg&0xff) switch(reg&0xff)
{ {
case 0x0:
m_stream->set_output_gain(0,MVOL() / 15.0);
m_stream->set_output_gain(1,MVOL() / 15.0);
break;
case 8: case 8:
case 9: case 9:
{ {
unsigned short v=m_udata.data[0x8/2]; unsigned short v=m_udata.data[0x8/2];
v&=0xff00; v&=0xff00;
v|=m_MidiStack[m_MidiR]; v|=m_MidiStack[m_MidiR];
InterruptUpdate(m_IrqMidi, CLEAR_LINE); // cancel the IRQ m_irq_cb(0); // cancel the IRQ
if(m_MidiR!=m_MidiW) if(m_MidiR!=m_MidiW)
{ {
++m_MidiR; ++m_MidiR;
@ -829,10 +817,10 @@ void aica_device::UpdateRegR(address_space &space, int reg)
SGC = (slot->EG.state << 13) & 0x6000; SGC = (slot->EG.state << 13) & 0x6000;
EG = slot->active ? slot->EG.volume : 0; EG = slot->active ? slot->EG.volume : 0;
EG >>= (EG_SHIFT - 13); EG >>= (EG_SHIFT - 13);
EG = 0x1fff - EG; EG = 0x1FFF - EG;
if (EG < 0) EG = 0; if (EG < 0) EG = 0;
m_udata.data[0x10/2] = (EG & 0x1ff8) | SGC | LP; m_udata.data[0x10/2] = (EG & 0x1FF8) | SGC | LP;
} }
else else
{ {
@ -884,10 +872,6 @@ void aica_device::w16(address_space &space,unsigned int addr,unsigned short val)
} }
else if (addr < 0x2800) else if (addr < 0x2800)
{ {
if (addr == 0x2000)
{
m_ram_size = MEM8B() ? 0x800000 : 0x200000;
}
if (addr <= 0x2044) if (addr <= 0x2044)
{ {
// printf("%x to EFSxx slot %d (addr %x)\n", val, (addr-0x2000)/4, addr&0x7f); // printf("%x to EFSxx slot %d (addr %x)\n", val, (addr-0x2000)/4, addr&0x7f);
@ -903,6 +887,25 @@ void aica_device::w16(address_space &space,unsigned int addr,unsigned short val)
UpdateReg(space, addr&0xff); UpdateReg(space, addr&0xff);
} }
else if (addr == 0x2d00)
{
m_IRQL = val;
popmessage("AICA: write to IRQL?");
}
else if (addr == 0x2d04)
{
m_IRQR = val;
if (val & 1)
{
m_irq_cb(0);
}
if (val & 0x100)
popmessage("AICA: SH-4 write protection enabled!");
if (val & 0xfefe)
popmessage("AICA: IRQR %04x!",val);
}
} }
else else
{ {
@ -977,7 +980,16 @@ unsigned short aica_device::r16(address_space &space, unsigned int addr)
{ {
UpdateRegR(space, addr&0xff); UpdateRegR(space, addr&0xff);
v= *((unsigned short *) (m_udata.datab+((addr&0xff)))); v= *((unsigned short *) (m_udata.datab+((addr&0xff))));
if((addr&0xfffe)==0x2810) m_udata.data[0x10/2] &= 0x7fff; // reset LP on read if((addr&0xfffe)==0x2810) m_udata.data[0x10/2] &= 0x7FFF; // reset LP on read
}
else if (addr == 0x2d00)
{
return m_IRQL;
}
else if (addr == 0x2d04)
{
//popmessage("AICA: read to IRQR?");
return m_IRQR;
} }
} }
else else
@ -1030,9 +1042,9 @@ void aica_device::TimersAddTicks(int ticks)
if(m_TimCnt[0]<=0xff00) if(m_TimCnt[0]<=0xff00)
{ {
m_TimCnt[0] += ticks << (8-((m_udata.data[0x18/2]>>8)&0x7)); m_TimCnt[0] += ticks << (8-((m_udata.data[0x18/2]>>8)&0x7));
if (m_TimCnt[0] > 0xfF00) if (m_TimCnt[0] > 0xFF00)
{ {
m_TimCnt[0] = 0xffff; m_TimCnt[0] = 0xFFFF;
m_udata.data[0xa0/2]|=0x40; m_udata.data[0xa0/2]|=0x40;
} }
m_udata.data[0x90/2]&=0xff00; m_udata.data[0x90/2]&=0xff00;
@ -1042,9 +1054,9 @@ void aica_device::TimersAddTicks(int ticks)
if(m_TimCnt[1]<=0xff00) if(m_TimCnt[1]<=0xff00)
{ {
m_TimCnt[1] += ticks << (8-((m_udata.data[0x1a/2]>>8)&0x7)); m_TimCnt[1] += ticks << (8-((m_udata.data[0x1a/2]>>8)&0x7));
if (m_TimCnt[1] > 0xfF00) if (m_TimCnt[1] > 0xFF00)
{ {
m_TimCnt[1] = 0xffff; m_TimCnt[1] = 0xFFFF;
m_udata.data[0xa0/2]|=0x80; m_udata.data[0xa0/2]|=0x80;
} }
m_udata.data[0x94/2]&=0xff00; m_udata.data[0x94/2]&=0xff00;
@ -1054,9 +1066,9 @@ void aica_device::TimersAddTicks(int ticks)
if(m_TimCnt[2]<=0xff00) if(m_TimCnt[2]<=0xff00)
{ {
m_TimCnt[2] += ticks << (8-((m_udata.data[0x1c/2]>>8)&0x7)); m_TimCnt[2] += ticks << (8-((m_udata.data[0x1c/2]>>8)&0x7));
if (m_TimCnt[2] > 0xfF00) if (m_TimCnt[2] > 0xFF00)
{ {
m_TimCnt[2] = 0xffff; m_TimCnt[2] = 0xFFFF;
m_udata.data[0xa0/2]|=0x100; m_udata.data[0xa0/2]|=0x100;
} }
m_udata.data[0x98/2]&=0xff00; m_udata.data[0x98/2]&=0xff00;
@ -1279,16 +1291,8 @@ void aica_device::DoMasterSamples(int nsamples)
} }
} }
if (MN()) // Mono *bufl++ = ICLIP16(smpl>>3);
{ *bufr++ = ICLIP16(smpr>>3);
*bufl++ = ICLIP16((smpl+smpr)>>4);
*bufr++ = ICLIP16((smpl+smpr)>>4);
}
else
{
*bufl++ = ICLIP16(smpl>>3);
*bufr++ = ICLIP16(smpr>>3);
}
} }
} }
@ -1328,7 +1332,7 @@ void aica_device::aica_exec_dma(address_space &space)
for(i=0;i < m_dma.dlg;i+=2) for(i=0;i < m_dma.dlg;i+=2)
{ {
uint16_t tmp; uint16_t tmp;
tmp = r16(space, m_dma.drga); tmp = r16(space, m_dma.drga);;
m_AICARAM[m_dma.dmea] = tmp & 0xff; m_AICARAM[m_dma.dmea] = tmp & 0xff;
m_AICARAM[m_dma.dmea+1] = tmp>>8; m_AICARAM[m_dma.dmea+1] = tmp>>8;
m_dma.dmea+=4; m_dma.dmea+=4;
@ -1394,36 +1398,20 @@ void aica_device::sound_stream_update(sound_stream &stream, stream_sample_t **in
DoMasterSamples(samples); DoMasterSamples(samples);
} }
//-------------------------------------------------
// device_add_mconfig - add device configuration
//-------------------------------------------------
MACHINE_CONFIG_START(aica_device::device_add_mconfig)
MCFG_CPU_ADD("arm7di", ARM7, DERIVED_CLOCK(2, 3*8)) // ARM7DI; AICA bus clock is 2/3rds * 33.8688. ARM7 gets 1 bus cycle out of each 8.
MCFG_CPU_PROGRAM_MAP(internal_map)
MCFG_INPUT_MERGER_ANY_HIGH("armirq")
MCFG_INPUT_MERGER_OUTPUT_HANDLER(INPUTLINE("arm7di", ARM7_FIRQ_LINE))
MCFG_RAM_ADD("ram")
MCFG_RAM_DEFAULT_VALUE(0xff) // TODO : Correct?
MACHINE_CONFIG_END
//------------------------------------------------- //-------------------------------------------------
// device_start - device-specific startup // device_start - device-specific startup
//------------------------------------------------- //-------------------------------------------------
void aica_device::device_start() void aica_device::device_start()
{ {
m_clock = clock();
m_rate = clock()/768;
// init the emulation // init the emulation
Init(); Init();
// set up the IRQ callbacks // set up the IRQ callbacks
m_irq_cb.resolve_safe();
m_main_irq_cb.resolve_safe(); m_main_irq_cb.resolve_safe();
m_stream = machine().sound().stream_alloc(*this, 0, 2, m_rate); m_stream = machine().sound().stream_alloc(*this, 0, 2, 44100);
// save state // save state
save_item(NAME(m_IrqTimA)); save_item(NAME(m_IrqTimA));
@ -1440,148 +1428,28 @@ void aica_device::device_start()
save_item(NAME(m_TimCnt),3); save_item(NAME(m_TimCnt),3);
} }
//------------------------------------------------- void aica_device::set_ram_base(void *base, int size)
// device_reset - device-specific reset
//-------------------------------------------------
void aica_device::device_reset()
{ {
/* halt the ARM7 */ m_AICARAM = (unsigned char *)base;
m_armrst = 1; m_AICARAM_LENGTH = size;
m_arm7di->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); m_RAM_MASK = m_AICARAM_LENGTH-1;
} m_RAM_MASK16 = m_RAM_MASK & 0x7ffffe;
m_DSP.AICARAM = (uint16_t *)base;
//------------------------------------------------- m_DSP.AICARAM_LENGTH = size;
// device_clock_changed - called if the clock
// changes
//-------------------------------------------------
void aica_device::device_clock_changed()
{
if (m_clock != clock())
{
m_clock = clock();
m_rate = clock()/768;
m_stream->set_sample_rate(m_rate);
}
}
READ32_MEMBER( aica_device::host_aica_reg_r )
{
// osd_printf_verbose("%s",string_format("AICA REG: [%08x] read %x, mask %x\n", 0x700000+reg*4, (uint64_t)offset, mem_mask).c_str());
if(offset == 0x2c00/4)
return m_armrst;
return r16(space,offset*4);
}
WRITE32_MEMBER( aica_device::host_aica_reg_w )
{
// these are can accessed only on SH4
if (offset == (0x2c00/4))
{
if(ACCESSING_BITS_0_7)
{
m_armrst = data & 1;
if (data & 1)
{
/* halt the ARM7 */
m_arm7di->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
}
else
{
/* it's alive ! */
m_arm7di->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
}
}
}
else
{
mem_mask = 0xffff; // TODO
uint16_t tmp;
tmp = r16(space, offset*4);
COMBINE_DATA(&tmp);
w16(space, offset*4, tmp);
}
// osd_printf_verbose("%s",string_format("AICA REG: [%08x=%x] write %x to %x, mask %x\n", 0x700000+reg*4, data, offset, mem_mask).c_str());
}
READ8_MEMBER( aica_device::ram_r )
{
if (offset < std::min(m_ram->size(), m_ram_size))
{
return m_ram->read(offset);
}
return 0xff;
}
READ8_MEMBER( aica_device::ram_host_r )
{
if ((m_rp == 0) && (offset < std::min(m_ram->size(), m_ram_size)))
{
return m_ram->read(offset);
}
return 0xff; // Unverified
}
WRITE8_MEMBER( aica_device::ram_w )
{
assert(offset < std::min(m_ram->size(), m_ram_size));
m_ram->write(offset, data);
} }
READ16_MEMBER( aica_device::read ) READ16_MEMBER( aica_device::read )
{ {
if ((offset*4) == 0x2d00) return r16(space,offset*2);
{
return m_IRQL;
}
else if ((offset*4) == 0x2d04)
{
//popmessage("AICA: read to IRQR?");
return m_IRQR;
}
return r16(space,offset*4);
} }
WRITE16_MEMBER( aica_device::write ) WRITE16_MEMBER( aica_device::write )
{ {
// these are can accessed only on internal ARM7DI core uint16_t tmp;
if ((offset*4) == 0x2d00)
{
m_IRQL = data;
popmessage("AICA: write to IRQL?");
}
else if ((offset*4) == 0x2d04)
{
m_IRQR = data;
if (data & 1) tmp = r16(space, offset*2);
{ COMBINE_DATA(&tmp);
for (int i = 0; i < 8; i++) w16(space, offset*2, tmp);
{
InterruptUpdate(i,CLEAR_LINE);
}
}
m_rp = data & 0x100;
if (data & 0xfefe)
popmessage("AICA: IRQR %04x!",data);
}
else
{
uint16_t tmp;
tmp = r16(space, offset*4);
COMBINE_DATA(&tmp);
w16(space, offset*4, tmp);
}
} }
WRITE16_MEMBER( aica_device::midi_in ) WRITE16_MEMBER( aica_device::midi_in )
@ -1599,46 +1467,38 @@ READ16_MEMBER( aica_device::midi_out_r )
return val; return val;
} }
void aica_device::internal_map(address_map &map)
{
map.unmap_value_high();
map(0x00000000, 0x007fffff).rw(this, FUNC(aica_device::ram_r), FUNC(aica_device::ram_w))
map(0x00800000, 0x00807fff).rw(this, FUNC(aica_device::read), FUNC(aica_device::write)).umask32(0x0000ffff);
}
DEFINE_DEVICE_TYPE(AICA, aica_device, "aica", "AICA") DEFINE_DEVICE_TYPE(AICA, aica_device, "aica", "AICA")
aica_device::aica_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) aica_device::aica_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, AICA, tag, owner, clock) : device_t(mconfig, AICA, tag, owner, clock),
, device_sound_interface(mconfig, *this) device_sound_interface(mconfig, *this),
, m_arm7di(*this, "arm7di") m_master(false),
, m_armirq(*this, "armirq") m_roffset(0),
, m_ram(*this, "ram") m_irq_cb(*this),
, m_ram_size(0x200000) m_main_irq_cb(*this),
, m_roffset(0) m_ram_region(*this, this->tag()),
, m_main_irq_cb(*this) m_IRQL(0),
, m_IRQL(0) m_IRQR(0),
, m_IRQR(0) m_BUFPTR(0),
, m_BUFPTR(0) m_AICARAM(nullptr),
, m_AICARAM(nullptr) m_AICARAM_LENGTH(0),
, m_AICARAM_LENGTH(0) m_RAM_MASK(0),
, m_RAM_MASK(0) m_RAM_MASK16(0),
, m_RAM_MASK16(0) m_buffertmpl(nullptr),
, m_IrqTimA(0) m_buffertmpr(nullptr),
, m_IrqTimBC(0) m_IrqTimA(0),
, m_IrqMidi(0) m_IrqTimBC(0),
, m_MidiOutW(0) m_IrqMidi(0),
, m_MidiOutR(0) m_MidiOutW(0),
, m_MidiW(0) m_MidiOutR(0),
, m_MidiR(0) m_MidiW(0),
, m_armrst(0) m_MidiR(0),
, m_rp(0) m_mcieb(0),
, m_mcieb(0) m_mcipd(0),
, m_mcipd(0) m_bufferl(nullptr),
, m_bufferl(nullptr) m_bufferr(nullptr),
, m_bufferr(nullptr) m_length(0),
, m_length(0) m_RBUFDST(nullptr)
, m_RBUFDST(nullptr)
{ {
memset(&m_udata.data, 0, sizeof(m_udata.data)); memset(&m_udata.data, 0, sizeof(m_udata.data));

43
src/devices/sound/aica.h
View File

@ -12,15 +12,17 @@
#pragma once #pragma once
#include "aicadsp.h" #include "aicadsp.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/input_merger.h"
#include "machine/ram.h"
#define MCFG_AICA_MASTER \
downcast<aica_device &>(*device).set_master(true);
#define MCFG_AICA_ROFFSET(offs) \ #define MCFG_AICA_ROFFSET(offs) \
downcast<aica_device &>(*device).set_roffset((offs)); downcast<aica_device &>(*device).set_roffset((offs));
#define MCFG_AICA_IRQ_CB(cb) \
devcb = &downcast<aica_device &>(*device).set_irq_callback((DEVCB_##cb));
#define MCFG_AICA_MAIN_IRQ_CB(cb) \ #define MCFG_AICA_MAIN_IRQ_CB(cb) \
devcb = &downcast<aica_device &>(*device).set_main_irq_callback((DEVCB_##cb)); devcb = &downcast<aica_device &>(*device).set_main_irq_callback((DEVCB_##cb));
@ -28,18 +30,13 @@ class aica_device : public device_t,
public device_sound_interface public device_sound_interface
{ {
public: public:
static constexpr feature_type imperfect_features() { return feature::SOUND; }
aica_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); aica_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void set_master(bool master) { m_master = master; }
void set_roffset(int roffset) { m_roffset = roffset; } void set_roffset(int roffset) { m_roffset = roffset; }
template <class Object> devcb_base &set_irq_callback(Object &&cb) { return m_irq_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_main_irq_callback(Object &&cb) { return m_main_irq_cb.set_callback(std::forward<Object>(cb)); } template <class Object> devcb_base &set_main_irq_callback(Object &&cb) { return m_main_irq_cb.set_callback(std::forward<Object>(cb)); }
// AICA RAM access
DECLARE_READ8_MEMBER( ram_r );
DECLARE_READ8_MEMBER( ram_host_r );
DECLARE_WRITE8_MEMBER( ram_w );
// AICA register access // AICA register access
DECLARE_READ16_MEMBER( read ); DECLARE_READ16_MEMBER( read );
DECLARE_WRITE16_MEMBER( write ); DECLARE_WRITE16_MEMBER( write );
@ -48,13 +45,11 @@ public:
DECLARE_WRITE16_MEMBER( midi_in ); DECLARE_WRITE16_MEMBER( midi_in );
DECLARE_READ16_MEMBER( midi_out_r ); DECLARE_READ16_MEMBER( midi_out_r );
void internal_map(address_map &map); void set_ram_base(void *base, int size);
protected: protected:
// device-level overrides // device-level overrides
virtual void device_add_mconfig() override;
virtual void device_start() override; virtual void device_start() override;
virtual void device_reset() override;
virtual void device_clock_changed() override;
// sound stream update overrides // sound stream update overrides
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples) override; virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples) override;
@ -111,8 +106,8 @@ private:
uint8_t lpend; uint8_t lpend;
}; };
unsigned char DecodeSCI(unsigned char irq); unsigned char DecodeSCI(unsigned char irq);
void InterruptUpdate(int line, int state);
void ResetInterrupts(); void ResetInterrupts();
void CheckPendingIRQ(); void CheckPendingIRQ();
@ -148,15 +143,11 @@ private:
inline signed int AICAALFO_Step(AICA_LFO_t *LFO); inline signed int AICAALFO_Step(AICA_LFO_t *LFO);
void AICALFO_ComputeStep(AICA_LFO_t *LFO,uint32_t LFOF,uint32_t LFOWS,uint32_t LFOS,int ALFO); void AICALFO_ComputeStep(AICA_LFO_t *LFO,uint32_t LFOF,uint32_t LFOWS,uint32_t LFOS,int ALFO);
required_device<arm7_cpu_device> m_arm7di; bool m_master;
required_device<input_merger_any_high_device> m_armirq;
required_device<ram_device> m_ram;
int m_ram_size;
uint32_t m_clock, m_rate;
int m_roffset; /* offset in the region */ int m_roffset; /* offset in the region */
devcb_write_line m_irq_cb;
devcb_write_line m_main_irq_cb; devcb_write_line m_main_irq_cb;
optional_memory_region m_ram_region;
union union
{ {
@ -173,6 +164,9 @@ private:
uint32_t m_AICARAM_LENGTH, m_RAM_MASK, m_RAM_MASK16; uint32_t m_AICARAM_LENGTH, m_RAM_MASK, m_RAM_MASK16;
sound_stream * m_stream; sound_stream * m_stream;
std::unique_ptr<int32_t[]> m_buffertmpl;
std::unique_ptr<int32_t[]> m_buffertmpr;
uint32_t m_IrqTimA; uint32_t m_IrqTimA;
uint32_t m_IrqTimBC; uint32_t m_IrqTimBC;
uint32_t m_IrqMidi; uint32_t m_IrqMidi;
@ -187,9 +181,6 @@ private:
int m_TimPris[3]; int m_TimPris[3];
int m_TimCnt[3]; int m_TimCnt[3];
int m_armrst;
int m_rp;
uint16_t m_mcieb, m_mcipd; uint16_t m_mcieb, m_mcipd;
// timers // timers

64
src/devices/sound/aicadsp.cpp
View File

@ -10,7 +10,7 @@ static uint16_t PACK(int32_t val)
int sign,exponent,k; int sign,exponent,k;
sign = (val >> 23) & 0x1; sign = (val >> 23) & 0x1;
temp = (val ^ (val << 1)) & 0xffffff; temp = (val ^ (val << 1)) & 0xFFFFFF;
exponent = 0; exponent = 0;
for (k=0; k<12; k++) for (k=0; k<12; k++)
{ {
@ -20,11 +20,11 @@ static uint16_t PACK(int32_t val)
exponent += 1; exponent += 1;
} }
if (exponent < 12) if (exponent < 12)
val = (val << exponent) & 0x3fffff; val = (val << exponent) & 0x3FFFFF;
else else
val <<= 11; val <<= 11;
val >>= 11; val >>= 11;
val &= 0x7ff; val &= 0x7FF;
val |= sign << 15; val |= sign << 15;
val |= exponent << 11; val |= exponent << 11;
@ -37,8 +37,8 @@ static int32_t UNPACK(uint16_t val)
int32_t uval; int32_t uval;
sign = (val >> 15) & 0x1; sign = (val >> 15) & 0x1;
exponent = (val >> 11) & 0xf; exponent = (val >> 11) & 0xF;
mantissa = val & 0x7ff; mantissa = val & 0x7FF;
uval = mantissa << 11; uval = mantissa << 11;
if (exponent > 11) if (exponent > 11)
{ {
@ -94,21 +94,21 @@ void AICADSP::step()
// if(IPtr[0]==0 && IPtr[1]==0 && IPtr[2]==0 && IPtr[3]==0) // if(IPtr[0]==0 && IPtr[1]==0 && IPtr[2]==0 && IPtr[3]==0)
// break; // break;
uint32_t TRA=(IPtr[0]>>9)&0x7f; uint32_t TRA=(IPtr[0]>>9)&0x7F;
uint32_t TWT=(IPtr[0]>>8)&0x01; uint32_t TWT=(IPtr[0]>>8)&0x01;
uint32_t TWA=(IPtr[0]>>1)&0x7f; uint32_t TWA=(IPtr[0]>>1)&0x7F;
uint32_t XSEL=(IPtr[2]>>15)&0x01; uint32_t XSEL=(IPtr[2]>>15)&0x01;
uint32_t YSEL=(IPtr[2]>>13)&0x03; uint32_t YSEL=(IPtr[2]>>13)&0x03;
uint32_t IRA=(IPtr[2]>>7)&0x3f; uint32_t IRA=(IPtr[2]>>7)&0x3F;
uint32_t IWT=(IPtr[2]>>6)&0x01; uint32_t IWT=(IPtr[2]>>6)&0x01;
uint32_t IWA=(IPtr[2]>>1)&0x1f; uint32_t IWA=(IPtr[2]>>1)&0x1F;
uint32_t TABLE=(IPtr[4]>>15)&0x01; uint32_t TABLE=(IPtr[4]>>15)&0x01;
uint32_t MWT=(IPtr[4]>>14)&0x01; uint32_t MWT=(IPtr[4]>>14)&0x01;
uint32_t MRD=(IPtr[4]>>13)&0x01; uint32_t MRD=(IPtr[4]>>13)&0x01;
uint32_t EWT=(IPtr[4]>>12)&0x01; uint32_t EWT=(IPtr[4]>>12)&0x01;
uint32_t EWA=(IPtr[4]>>8)&0x0f; uint32_t EWA=(IPtr[4]>>8)&0x0F;
uint32_t ADRL=(IPtr[4]>>7)&0x01; uint32_t ADRL=(IPtr[4]>>7)&0x01;
uint32_t FRCL=(IPtr[4]>>6)&0x01; uint32_t FRCL=(IPtr[4]>>6)&0x01;
uint32_t SHIFT=(IPtr[4]>>4)&0x03; uint32_t SHIFT=(IPtr[4]>>4)&0x03;
@ -166,7 +166,7 @@ void AICADSP::step()
INPUTS<<=8; INPUTS<<=8;
INPUTS>>=8; INPUTS>>=8;
//if(INPUTS&0x00800000) //if(INPUTS&0x00800000)
// INPUTS|=0xff000000; // INPUTS|=0xFF000000;
if(IWT) if(IWT)
{ {
@ -183,11 +183,11 @@ void AICADSP::step()
B=ACC; B=ACC;
else else
{ {
B=TEMP[(TRA+DEC)&0x7f]; B=TEMP[(TRA+DEC)&0x7F];
B<<=8; B<<=8;
B>>=8; B>>=8;
//if(B&0x00800000) //if(B&0x00800000)
// B|=0xff000000; //Sign extend // B|=0xFF000000; //Sign extend
} }
if(NEGB) if(NEGB)
B=0-B; B=0-B;
@ -200,11 +200,11 @@ void AICADSP::step()
X=INPUTS; X=INPUTS;
else else
{ {
X=TEMP[(TRA+DEC)&0x7f]; X=TEMP[(TRA+DEC)&0x7F];
X<<=8; X<<=8;
X>>=8; X>>=8;
//if(X&0x00800000) //if(X&0x00800000)
// X|=0xff000000; // X|=0xFF000000;
} }
//Y //Y
@ -213,9 +213,9 @@ void AICADSP::step()
else if(YSEL==1) else if(YSEL==1)
Y=this->COEF[COEF<<1]>>3; //COEF is 16 bits Y=this->COEF[COEF<<1]>>3; //COEF is 16 bits
else if(YSEL==2) else if(YSEL==2)
Y=(Y_REG>>11)&0x1fff; Y=(Y_REG>>11)&0x1FFF;
else if(YSEL==3) else if(YSEL==3)
Y=(Y_REG>>4)&0x0fff; Y=(Y_REG>>4)&0x0FFF;
if(YRL) if(YRL)
Y_REG=INPUTS; Y_REG=INPUTS;
@ -224,16 +224,16 @@ void AICADSP::step()
if(SHIFT==0) if(SHIFT==0)
{ {
SHIFTED=ACC; SHIFTED=ACC;
if(SHIFTED>0x007fffff) if(SHIFTED>0x007FFFFF)
SHIFTED=0x007fffff; SHIFTED=0x007FFFFF;
if(SHIFTED<(-0x00800000)) if(SHIFTED<(-0x00800000))
SHIFTED=-0x00800000; SHIFTED=-0x00800000;
} }
else if(SHIFT==1) else if(SHIFT==1)
{ {
SHIFTED=ACC*2; SHIFTED=ACC*2;
if(SHIFTED>0x007fffff) if(SHIFTED>0x007FFFFF)
SHIFTED=0x007fffff; SHIFTED=0x007FFFFF;
if(SHIFTED<(-0x00800000)) if(SHIFTED<(-0x00800000))
SHIFTED=-0x00800000; SHIFTED=-0x00800000;
} }
@ -242,38 +242,38 @@ void AICADSP::step()
SHIFTED=ACC*2; SHIFTED=ACC*2;
SHIFTED<<=8; SHIFTED<<=8;
SHIFTED>>=8; SHIFTED>>=8;
//SHIFTED&=0x00ffffff; //SHIFTED&=0x00FFFFFF;
//if(SHIFTED&0x00800000) //if(SHIFTED&0x00800000)
// SHIFTED|=0xff000000; // SHIFTED|=0xFF000000;
} }
else if(SHIFT==3) else if(SHIFT==3)
{ {
SHIFTED=ACC; SHIFTED=ACC;
SHIFTED<<=8; SHIFTED<<=8;
SHIFTED>>=8; SHIFTED>>=8;
//SHIFTED&=0x00ffffff; //SHIFTED&=0x00FFFFFF;
//if(SHIFTED&0x00800000) //if(SHIFTED&0x00800000)
// SHIFTED|=0xff000000; // SHIFTED|=0xFF000000;
} }
//ACCUM //ACCUM
Y<<=19; Y<<=19;
Y>>=19; Y>>=19;
//if(Y&0x1000) //if(Y&0x1000)
// Y|=0xfffff000; // Y|=0xFFFFF000;
v=(((int64_t) X*(int64_t) Y)>>12); v=(((int64_t) X*(int64_t) Y)>>12);
ACC=(int) v+B; ACC=(int) v+B;
if(TWT) if(TWT)
TEMP[(TWA+DEC)&0x7f]=SHIFTED; TEMP[(TWA+DEC)&0x7F]=SHIFTED;
if(FRCL) if(FRCL)
{ {
if(SHIFT==3) if(SHIFT==3)
FRC_REG=SHIFTED&0x0fff; FRC_REG=SHIFTED&0x0FFF;
else else
FRC_REG=(SHIFTED>>11)&0x1fff; FRC_REG=(SHIFTED>>11)&0x1FFF;
} }
if(MRD || MWT) if(MRD || MWT)
@ -283,13 +283,13 @@ void AICADSP::step()
if(!TABLE) if(!TABLE)
ADDR+=DEC; ADDR+=DEC;
if(ADREB) if(ADREB)
ADDR+=ADRS_REG&0x0fff; ADDR+=ADRS_REG&0x0FFF;
if(NXADR) if(NXADR)
ADDR++; ADDR++;
if(!TABLE) if(!TABLE)
ADDR&=RBL-1; ADDR&=RBL-1;
else else
ADDR&=0xffff; ADDR&=0xFFFF;
//ADDR<<=1; //ADDR<<=1;
//ADDR+=RBP<<13; //ADDR+=RBP<<13;
//MEMVAL=AICARAM[ADDR>>1]; //MEMVAL=AICARAM[ADDR>>1];
@ -313,7 +313,7 @@ void AICADSP::step()
if(ADRL) if(ADRL)
{ {
if(SHIFT==3) if(SHIFT==3)
ADRS_REG=(SHIFTED>>12)&0xfff; ADRS_REG=(SHIFTED>>12)&0xFFF;
else else
ADRS_REG=(INPUTS>>16); ADRS_REG=(INPUTS>>16);
} }

27
src/mame/drivers/dccons.cpp
View File

@ -5,9 +5,9 @@
by R. Belmont & Angelo Salese by R. Belmont & Angelo Salese
SH-4 @ 200 MHz SH-4 @ 200 MHz
ARM7DI @ 2.8223 MHz (no T or M extensions)
PowerVR 3D video PowerVR 3D video
AICA audio AICA audio
ARM7DI @ 2.8223 MHz (no T or M extensions)
GD-ROM drive (modified ATAPI interface) GD-ROM drive (modified ATAPI interface)
NTSC/N NTSC/I PAL/N PAL/I VGA NTSC/N NTSC/I PAL/N PAL/I VGA
@ -377,9 +377,9 @@ void dc_cons_state::dc_map(address_map &map)
map(0x005f7c00, 0x005f7cff).m(m_powervr2, FUNC(powervr2_device::pd_dma_map)); map(0x005f7c00, 0x005f7cff).m(m_powervr2, FUNC(powervr2_device::pd_dma_map));
map(0x005f8000, 0x005f9fff).m(m_powervr2, FUNC(powervr2_device::ta_map)); map(0x005f8000, 0x005f9fff).m(m_powervr2, FUNC(powervr2_device::ta_map));
map(0x00600000, 0x006007ff).rw(this, FUNC(dc_cons_state::dc_modem_r), FUNC(dc_cons_state::dc_modem_w)); map(0x00600000, 0x006007ff).rw(this, FUNC(dc_cons_state::dc_modem_r), FUNC(dc_cons_state::dc_modem_w));
map(0x00700000, 0x00707fff).rw(m_aica, FUNC(aica_device::host_aica_reg_r), FUNC(aica_device::host_aica_reg_w)); map(0x00700000, 0x00707fff).rw(this, FUNC(dc_cons_state::dc_aica_reg_r), FUNC(dc_cons_state::dc_aica_reg_w));
map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff); map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff);
map(0x00800000, 0x009fffff).rw(m_aica, FUNC(aica_device::ram_host_r), FUNC(aica_device::ram_w)); map(0x00800000, 0x009fffff).rw(this, FUNC(dc_cons_state::sh4_soundram_r), FUNC(dc_cons_state::sh4_soundram_w));
// AM_RANGE(0x01000000, 0x01ffffff) G2 Ext Device #1 // AM_RANGE(0x01000000, 0x01ffffff) G2 Ext Device #1
// AM_RANGE(0x02700000, 0x02707fff) AICA reg mirror // AM_RANGE(0x02700000, 0x02707fff) AICA reg mirror
// AM_RANGE(0x02800000, 0x02ffffff) AICA wave mem mirror // AM_RANGE(0x02800000, 0x02ffffff) AICA wave mem mirror
@ -417,6 +417,13 @@ void dc_cons_state::dc_port(address_map &map)
map(0x00000000, 0x00000007).rw(this, FUNC(dc_cons_state::dc_pdtra_r), FUNC(dc_cons_state::dc_pdtra_w)); map(0x00000000, 0x00000007).rw(this, FUNC(dc_cons_state::dc_pdtra_r), FUNC(dc_cons_state::dc_pdtra_w));
} }
void dc_cons_state::dc_audio_map(address_map &map)
{
map.unmap_value_high();
map(0x00000000, 0x001fffff).ram().share("dc_sound_ram"); /* shared with SH-4 */
map(0x00800000, 0x00807fff).rw(this, FUNC(dc_cons_state::dc_arm_aica_r), FUNC(dc_cons_state::dc_arm_aica_w));
}
static INPUT_PORTS_START( dc ) static INPUT_PORTS_START( dc )
PORT_START("P1:0") PORT_START("P1:0")
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("P1 RIGHT") PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("P1 RIGHT")
@ -591,6 +598,9 @@ MACHINE_CONFIG_START(dc_cons_state::dc)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1)
MCFG_CPU_ADD("soundcpu", ARM7, ((XTAL(33'868'800)*2)/3)/8) // AICA bus clock is 2/3rds * 33.8688. ARM7 gets 1 bus cycle out of each 8.
MCFG_CPU_PROGRAM_MAP(dc_audio_map)
MCFG_MACHINE_RESET_OVERRIDE(dc_cons_state,dc_console ) MCFG_MACHINE_RESET_OVERRIDE(dc_cons_state,dc_console )
// MCFG_MACRONIX_29LV160TMC_ADD("dcflash") // MCFG_MACRONIX_29LV160TMC_ADD("dcflash")
@ -609,13 +619,12 @@ MACHINE_CONFIG_START(dc_cons_state::dc)
MCFG_POWERVR2_ADD("powervr2", WRITE8(dc_state, pvr_irq)) MCFG_POWERVR2_ADD("powervr2", WRITE8(dc_state, pvr_irq))
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SOUND_ADD("aica", AICA, XTAL(33'868'800)) MCFG_SOUND_ADD("aica", AICA, 0)
MCFG_AICA_MASTER
MCFG_AICA_IRQ_CB(WRITELINE(dc_state, aica_irq))
MCFG_AICA_MAIN_IRQ_CB(WRITELINE(dc_state, sh4_aica_irq)) MCFG_AICA_MAIN_IRQ_CB(WRITELINE(dc_state, sh4_aica_irq))
MCFG_SOUND_ROUTE(0, "lspeaker", 2.0) MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
MCFG_SOUND_ROUTE(1, "rspeaker", 2.0) MCFG_SOUND_ROUTE(0, "rspeaker", 1.0)
MCFG_RAM_MODIFY("aica:ram")
MCFG_RAM_DEFAULT_SIZE("2M")
MCFG_AICARTC_ADD("aicartc", XTAL(32'768)) MCFG_AICARTC_ADD("aicartc", XTAL(32'768))

15
src/mame/drivers/hikaru.cpp
View File

@ -526,20 +526,9 @@ MACHINE_CONFIG_START(hikaru_state::hikaru)
// MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") // MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
// MCFG_SOUND_ADD("aica", AICA, XTAL(33'868'800)) // MCFG_SOUND_ADD("aica", AICA, 0)
// MCFG_SOUND_ROUTE(0, "lspeaker", 2.0) // MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
// MCFG_SOUND_ROUTE(1, "rspeaker", 2.0) // MCFG_SOUND_ROUTE(0, "rspeaker", 2.0)
//
// MCFG_RAM_MODIFY("aica:ram")
// MCFG_RAM_DEFAULT_SIZE("8M")
//
// Second AICA with External Sound Board is Enable
// MCFG_SOUND_ADD("aica_2", AICA, XTAL(33'868'800))
// MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
// MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
//
// MCFG_RAM_MODIFY("aica:ram")
// MCFG_RAM_DEFAULT_SIZE("8M")
MACHINE_CONFIG_END MACHINE_CONFIG_END

132
src/mame/drivers/naomi.cpp
View File

@ -1701,9 +1701,9 @@ void naomi_state::naomi_map(address_map &map)
map(0x005f7c00, 0x005f7cff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::pd_dma_map)); map(0x005f7c00, 0x005f7cff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::pd_dma_map));
map(0x005f8000, 0x005f9fff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::ta_map)); map(0x005f8000, 0x005f9fff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::ta_map));
map(0x00600000, 0x006007ff).mirror(0x02000000).rw(this, FUNC(naomi_state::dc_modem_r), FUNC(naomi_state::dc_modem_w)); map(0x00600000, 0x006007ff).mirror(0x02000000).rw(this, FUNC(naomi_state::dc_modem_r), FUNC(naomi_state::dc_modem_w));
map(0x00700000, 0x00707fff).mirror(0x02000000).rw(m_aica, FUNC(aica_device::host_aica_reg_r), FUNC(aica_device::host_aica_reg_w)); map(0x00700000, 0x00707fff).mirror(0x02000000).rw(this, FUNC(naomi_state::dc_aica_reg_r), FUNC(naomi_state::dc_aica_reg_w));
map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff); map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff);
map(0x00800000, 0x00ffffff).mirror(0x02000000).rw(m_aica, FUNC(aica_device::ram_host_r), FUNC(aica_device::ram_w)); // sound RAM (8 MB) map(0x00800000, 0x00ffffff).mirror(0x02000000).rw(this, FUNC(naomi_state::sh4_soundram_r), FUNC(naomi_state::sh4_soundram_w)); // sound RAM (8 MB)
/* External Device */ /* External Device */
map(0x01000000, 0x01ffffff).mirror(0x02000000).r(this, FUNC(naomi_state::naomi_g2bus_r)); map(0x01000000, 0x01ffffff).mirror(0x02000000).r(this, FUNC(naomi_state::naomi_g2bus_r));
@ -1760,9 +1760,9 @@ void naomi2_state::naomi2_map(address_map &map)
map(0x005f7c00, 0x005f7cff).m(m_powervr2, FUNC(powervr2_device::pd_dma_map)); map(0x005f7c00, 0x005f7cff).m(m_powervr2, FUNC(powervr2_device::pd_dma_map));
map(0x005f8000, 0x005f9fff).m(m_powervr2, FUNC(powervr2_device::ta_map)); map(0x005f8000, 0x005f9fff).m(m_powervr2, FUNC(powervr2_device::ta_map));
map(0x00600000, 0x006007ff).mirror(0x02000000).rw(this, FUNC(naomi2_state::dc_modem_r), FUNC(naomi2_state::dc_modem_w)); map(0x00600000, 0x006007ff).mirror(0x02000000).rw(this, FUNC(naomi2_state::dc_modem_r), FUNC(naomi2_state::dc_modem_w));
map(0x00700000, 0x00707fff).mirror(0x02000000).rw(m_aica, FUNC(aica_device::host_aica_reg_r), FUNC(aica_device::host_aica_reg_w)); map(0x00700000, 0x00707fff).mirror(0x02000000).rw(this, FUNC(naomi2_state::dc_aica_reg_r), FUNC(naomi2_state::dc_aica_reg_w));
map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff); map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff);
map(0x00800000, 0x00ffffff).mirror(0x02000000).rw(m_aica, FUNC(aica_device::ram_host_r), FUNC(aica_device::ram_w)); // sound RAM (8 MB) map(0x00800000, 0x00ffffff).mirror(0x02000000).rw(this, FUNC(naomi2_state::sh4_soundram_r), FUNC(naomi2_state::sh4_soundram_w)); // sound RAM (8 MB)
/* External Device */ /* External Device */
map(0x01000000, 0x01ffffff).mirror(0x02000000).r(this, FUNC(naomi2_state::naomi_g2bus_r)); map(0x01000000, 0x01ffffff).mirror(0x02000000).r(this, FUNC(naomi2_state::naomi_g2bus_r));
@ -1816,6 +1816,31 @@ void naomi_state::naomi_port(address_map &map)
* Atomiswave address map, almost identical to Dreamcast * Atomiswave address map, almost identical to Dreamcast
*/ */
READ64_MEMBER(atomiswave_state::aw_flash_r )
{
return (uint64_t)m_awflash->read(offset*8) | (uint64_t)m_awflash->read((offset*8)+1)<<8 | (uint64_t)m_awflash->read((offset*8)+2)<<16 | (uint64_t)m_awflash->read((offset*8)+3)<<24 |
(uint64_t)m_awflash->read((offset*8)+4)<<32 | (uint64_t)m_awflash->read((offset*8)+5)<<40 | (uint64_t)m_awflash->read((offset*8)+6)<<48 | (uint64_t)m_awflash->read((offset*8)+7)<<56;
}
WRITE64_MEMBER(atomiswave_state::aw_flash_w )
{
int i;
uint32_t addr = offset * 8;
for (i = 0; i < 8; i++)
{
if (mem_mask & ((uint64_t)0xff)<< (i*8))
{
addr += i;
break;
}
}
data >>= (i*8);
m_awflash->write(addr, data);
}
// TODO: don't we have a common function for this? // TODO: don't we have a common function for this?
inline int atomiswave_state::decode_reg32_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift) inline int atomiswave_state::decode_reg32_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift)
{ {
@ -1855,7 +1880,7 @@ READ64_MEMBER(atomiswave_state::aw_modem_r )
(ab == 0) -> BIOS skip RAM test (ab == 0) -> BIOS skip RAM test
*/ */
return 0xffffffff00000000U | (ioport("COINS")->read() & 0x0f); return 0xffffffff00000000U | (ioport("COINS")->read() & 0x0F);
} else } else
if (reg == 0x284/4) if (reg == 0x284/4)
return 0xffffffff00000000U | aw_ctrl_type; return 0xffffffff00000000U | aw_ctrl_type;
@ -1875,7 +1900,7 @@ WRITE64_MEMBER(atomiswave_state::aw_modem_w )
dat = (uint32_t)(data >> shift); dat = (uint32_t)(data >> shift);
if (reg == 0x284/4) if (reg == 0x284/4)
{ {
aw_ctrl_type = dat & 0xf0; aw_ctrl_type = dat & 0xF0;
} }
/* /*
0x00600284 rw ddcc0000 0x00600284 rw ddcc0000
@ -1900,8 +1925,8 @@ WRITE64_MEMBER(atomiswave_state::aw_modem_w )
void atomiswave_state::aw_map(address_map &map) void atomiswave_state::aw_map(address_map &map)
{ {
/* Area 0 */ /* Area 0 */
map(0x00000000, 0x0001ffff).rw(m_awflash, FUNC(macronix_29l001mc_device::read), FUNC(macronix_29l001mc_device::write)).region("awflash", 0); map(0x00000000, 0x0001ffff).rw(this, FUNC(atomiswave_state::aw_flash_r), FUNC(atomiswave_state::aw_flash_w)).region("awflash", 0);
map(0xa0000000, 0xa001ffff).rw(m_awflash, FUNC(macronix_29l001mc_device::read), FUNC(macronix_29l001mc_device::write)).region("awflash", 0); map(0xa0000000, 0xa001ffff).rw(this, FUNC(atomiswave_state::aw_flash_r), FUNC(atomiswave_state::aw_flash_w)).region("awflash", 0);
map(0x00200000, 0x0021ffff).ram().share("sram"); // battery backed up RAM map(0x00200000, 0x0021ffff).ram().share("sram"); // battery backed up RAM
map(0x005f6800, 0x005f69ff).rw(this, FUNC(atomiswave_state::dc_sysctrl_r), FUNC(atomiswave_state::dc_sysctrl_w)); map(0x005f6800, 0x005f69ff).rw(this, FUNC(atomiswave_state::dc_sysctrl_r), FUNC(atomiswave_state::dc_sysctrl_w));
@ -1912,9 +1937,9 @@ void atomiswave_state::aw_map(address_map &map)
map(0x005f7c00, 0x005f7cff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::pd_dma_map)); map(0x005f7c00, 0x005f7cff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::pd_dma_map));
map(0x005f8000, 0x005f9fff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::ta_map)); map(0x005f8000, 0x005f9fff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::ta_map));
map(0x00600000, 0x006007ff).rw(this, FUNC(atomiswave_state::aw_modem_r), FUNC(atomiswave_state::aw_modem_w)); map(0x00600000, 0x006007ff).rw(this, FUNC(atomiswave_state::aw_modem_r), FUNC(atomiswave_state::aw_modem_w));
map(0x00700000, 0x00707fff).rw(m_aica, FUNC(aica_device::host_aica_reg_r), FUNC(aica_device::host_aica_reg_w)); map(0x00700000, 0x00707fff).rw(this, FUNC(atomiswave_state::dc_aica_reg_r), FUNC(atomiswave_state::dc_aica_reg_w));
map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff); map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff);
map(0x00800000, 0x00ffffff).rw(m_aica, FUNC(aica_device::ram_host_r), FUNC(aica_device::ram_w)); // Atomiswave has only 2MB of sound RAM, but Games are accessing full 8MB area? map(0x00800000, 0x00ffffff).rw(this, FUNC(atomiswave_state::sh4_soundram_r), FUNC(atomiswave_state::sh4_soundram_w)); // sound RAM (8 MB)
/* Area 1 - half the texture memory, like dreamcast, not naomi */ /* Area 1 - half the texture memory, like dreamcast, not naomi */
map(0x04000000, 0x047fffff).ram().mirror(0x00800000).share("dc_texture_ram"); // texture memory 64 bit access map(0x04000000, 0x047fffff).ram().mirror(0x00800000).share("dc_texture_ram"); // texture memory 64 bit access
@ -1955,6 +1980,13 @@ void atomiswave_state::aw_port(address_map &map)
// ??? // ???
} }
void dc_state::dc_audio_map(address_map &map)
{
map.unmap_value_high();
map(0x00000000, 0x007fffff).ram().share("dc_sound_ram"); /* shared with SH-4 */
map(0x00800000, 0x00807fff).rw(this, FUNC(dc_state::dc_arm_aica_r), FUNC(dc_state::dc_arm_aica_w));
}
/* /*
* Input ports * Input ports
*/ */
@ -2633,6 +2665,7 @@ INPUT_PORTS_END
MACHINE_RESET_MEMBER(naomi_state,naomi) MACHINE_RESET_MEMBER(naomi_state,naomi)
{ {
naomi_state::machine_reset(); naomi_state::machine_reset();
m_aica->set_ram_base(dc_sound_ram, 8*1024*1024);
} }
/* /*
@ -2656,6 +2689,9 @@ MACHINE_CONFIG_START(dc_state::naomi_aw_base)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1)
MCFG_CPU_ADD("soundcpu", ARM7, ((XTAL(33'868'800)*2)/3)/8) // AICA bus clock is 2/3rds * 33.8688. ARM7 gets 1 bus cycle out of each 8.
MCFG_CPU_PROGRAM_MAP(dc_audio_map)
MCFG_MAPLE_DC_ADD( "maple_dc", "maincpu", dc_maple_irq ) MCFG_MAPLE_DC_ADD( "maple_dc", "maincpu", dc_maple_irq )
/* video hardware */ /* video hardware */
@ -2666,14 +2702,14 @@ MACHINE_CONFIG_START(dc_state::naomi_aw_base)
MCFG_POWERVR2_ADD("powervr2", WRITE8(dc_state, pvr_irq)) MCFG_POWERVR2_ADD("powervr2", WRITE8(dc_state, pvr_irq))
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SOUND_ADD("aica", AICA, XTAL(33'868'800)) MCFG_SOUND_ADD("aica", AICA, 0)
MCFG_AICA_MASTER
MCFG_AICA_IRQ_CB(WRITELINE(dc_state, aica_irq))
MCFG_AICA_MAIN_IRQ_CB(WRITELINE(dc_state, sh4_aica_irq)) MCFG_AICA_MAIN_IRQ_CB(WRITELINE(dc_state, sh4_aica_irq))
MCFG_SOUND_ROUTE(0, "lspeaker", 2.0) MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
MCFG_SOUND_ROUTE(1, "rspeaker", 2.0) MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
MCFG_RAM_MODIFY("aica:ram")
MCFG_RAM_DEFAULT_SIZE("8M")
MCFG_AICARTC_ADD("aicartc", XTAL(32'768) ) MCFG_AICARTC_ADD("aicartc", XTAL(32'768) )
MACHINE_CONFIG_END MACHINE_CONFIG_END
@ -10494,37 +10530,37 @@ ROM_END
/* Atomiswave */ /* Atomiswave */
GAME( 2001, awbios, 0, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Atomiswave Bios", GAME_FLAGS|MACHINE_IS_BIOS_ROOT ) GAME( 2001, awbios, 0, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Atomiswave Bios", GAME_FLAGS|MACHINE_IS_BIOS_ROOT )
// game "exe" build timestamps, shown in SYSTEM MENU -> TEST MODE // game "exe" build timestamps, shown in SYSTEM MENU -> TEST MODE
GAME( 2003, ggx15, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Arc System Works / Sammy", "Guilty Gear X ver. 1.5", GAME_FLAGS) // none GAME( 2003, ggx15, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Arc System Works / Sammy", "Guilty Gear X ver. 1.5", GAME_FLAGS) // none
GAME( 2003, sprtshot, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy USA", "Sports Shooting USA", GAME_FLAGS ) // May 02 2003 09:40:31 GAME( 2003, sprtshot, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy USA", "Sports Shooting USA", GAME_FLAGS ) // May 02 2003 09:40:31
GAME( 2003, sushibar, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Sushi Bar / Tore Tore! Sushi", MACHINE_IMPERFECT_GRAPHICS|MACHINE_IMPERFECT_SOUND )// May 23 2003 14:40:15 GAME( 2003, sushibar, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Sushi Bar", MACHINE_IMPERFECT_GRAPHICS|MACHINE_IMPERFECT_SOUND )// May 23 2003 14:40:15
GAME( 2003, demofist, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Polygon Magic / Dimps", "Demolish Fist", GAME_FLAGS ) // Jun 02 2003 16:45:35 GAME( 2003, demofist, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Polygon Magic / Dimps", "Demolish Fist", GAME_FLAGS ) // Jun 02 2003 16:45:35
GAME( 2003, maxspeed, awbios, aw1c, aw1w, atomiswave_state, atomiswave, ROT0, "SIMS / Sammy", "Maximum Speed", GAME_FLAGS ) // Jun 09 2003 10:20:37 GAME( 2003, maxspeed, awbios, aw1c, aw1w, atomiswave_state, atomiswave, ROT0, "SIMS / Sammy", "Maximum Speed", GAME_FLAGS ) // Jun 09 2003 10:20:37
GAME( 2003, dolphin, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Dolphin Blue", GAME_FLAGS) // Jun 27 2003 09:00:03 GAME( 2003, dolphin, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Dolphin Blue", GAME_FLAGS) // Jun 27 2003 09:00:03
GAME( 2003, kov7sprt, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "IGS / Sammy", "Knights of Valour - The Seven Spirits", GAME_FLAGS) // Nov 24 2003 16:56:01 GAME( 2003, kov7sprt, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "IGS / Sammy", "Knights of Valour - The Seven Spirits", GAME_FLAGS) // Nov 24 2003 16:56:01
GAME( 2004, ggisuka, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Arc System Works / Sammy", "Guilty Gear Isuka", GAME_FLAGS) // Jan 14 2004 10:04:24 GAME( 2004, ggisuka, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Arc System Works / Sammy", "Guilty Gear Isuka", GAME_FLAGS) // Jan 14 2004 10:04:24
GAME( 2004, rumblefp, rumblef, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / Dimps", "The Rumble Fish (prototype)", GAME_FLAGS) // Feb 20 2004 09:15:34 GAME( 2004, rumblefp, rumblef, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / Dimps", "The Rumble Fish (prototype)", GAME_FLAGS) // Feb 20 2004 09:15:34
GAME( 2004, rangrmsn, awbios, aw2c, aw1w, atomiswave_state, atomiswave, ROT0, "RIZ Inc./ Sammy", "Ranger Mission", GAME_FLAGS ) // Mar 01 2004 19:08:15 GAME( 2004, rangrmsn, awbios, aw2c, aw1w, atomiswave_state, atomiswave, ROT0, "RIZ Inc./ Sammy", "Ranger Mission", GAME_FLAGS ) // Mar 01 2004 19:08:15
GAME( 2004, rumblef, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / Dimps", "The Rumble Fish", GAME_FLAGS) // Mar 10 2004 19:07:43 GAME( 2004, rumblef, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / Dimps", "The Rumble Fish", GAME_FLAGS) // Mar 10 2004 19:07:43
GAME( 2004, salmankt, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Yuki Enterprise / Sammy", "Net Select: Salaryman Kintaro", GAME_FLAGS ) // Jun 14 2004 22:50:03 GAME( 2004, salmankt, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Yuki Enterprise / Sammy", "Net Select: Salaryman Kintaro", GAME_FLAGS ) // Jun 14 2004 22:50:03
GAME( 2004, kofnw, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "The King of Fighters Neowave", GAME_FLAGS ) // Jul 09 2004 15:05:53 GAME( 2004, kofnw, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "The King of Fighters Neowave", GAME_FLAGS ) // Jul 09 2004 15:05:53
GAME( 2004, kofnwj, kofnw, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "The King of Fighters Neowave (Japan)", GAME_FLAGS ) // Jul 09 2004 15:05:53 GAME( 2004, kofnwj, kofnw, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "The King of Fighters Neowave (Japan)", GAME_FLAGS ) // Jul 09 2004 15:05:53
GAME( 2004, ftspeed, awbios, aw1c, aw1w, atomiswave_state, atomiswave, ROT0, "Sammy", "Faster Than Speed", GAME_FLAGS ) // Aug 24 2004 18:40:24 GAME( 2004, ftspeed, awbios, aw1c, aw1w, atomiswave_state, atomiswave, ROT0, "Sammy", "Faster Than Speed", GAME_FLAGS ) // Aug 24 2004 18:40:24
GAME( 2004, xtrmhunt, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Extreme Hunting", GAME_FLAGS ) // Nov 23 2004 10:14:14 GAME( 2004, xtrmhunt, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Extreme Hunting", GAME_FLAGS ) // Nov 23 2004 10:14:14
GAME( 2004, blokpong, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT270, "MOSS / Sammy", "Block Pong-Pong", GAME_FLAGS ) // Dec 22 2004 12:32:52 GAME( 2004, blokpong, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT270, "MOSS / Sammy", "Block Pong-Pong", GAME_FLAGS ) // Dec 22 2004 12:32:52
GAME( 2005, rumblf2p, rumblef2, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / Dimps", "The Rumble Fish 2 (prototype)", GAME_FLAGS ) // Jan 11 2005 14:31:05 GAME( 2005, rumblf2p, rumblef2, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / Dimps", "The Rumble Fish 2 (prototype)", GAME_FLAGS ) // Jan 11 2005 14:31:05
GAME( 2005, anmlbskta, anmlbskt, aw2c, aw2c, atomiswave_state, atomiswave, ROT270, "MOSS / Sammy", "Animal Basket (19 Jan 2005)", GAME_FLAGS ) // Jan 19 2005 13:09:07 GAME( 2005, anmlbskta, anmlbskt, aw2c, aw2c, atomiswave_state, atomiswave, ROT270, "MOSS / Sammy", "Animal Basket (19 Jan 2005)", GAME_FLAGS ) // Jan 19 2005 13:09:07
GAME( 2005, anmlbskt, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT270, "MOSS / Sammy", "Animal Basket (24 Jan 2005)", GAME_FLAGS ) // Jan 24 2005 14:12:29 GAME( 2005, anmlbskt, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT270, "MOSS / Sammy", "Animal Basket (24 Jan 2005)", GAME_FLAGS ) // Jan 24 2005 14:12:29
GAME( 2005, waidrive, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT270, "MOSS / Sammy", "WaiWai Drive", GAME_FLAGS ) // Jan 27 2005 16:21:21 GAME( 2005, waidrive, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT270, "MOSS / Sammy", "WaiWai Drive", GAME_FLAGS ) // Jan 27 2005 16:21:21
GAME( 2005, vfurlong, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Progress / Sammy", "Net Select Horse Racing: Victory Furlong", GAME_FLAGS ) // Mar 02 2005 22:10:33 GAME( 2005, vfurlong, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Progress / Sammy", "Net Select Horse Racing: Victory Furlong", GAME_FLAGS ) // Mar 02 2005 22:10:33
GAME( 2005, rumblef2, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / Dimps", "The Rumble Fish 2", GAME_FLAGS ) // Mar 04 2005 19:26:32 GAME( 2005, rumblef2, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / Dimps", "The Rumble Fish 2", GAME_FLAGS ) // Mar 04 2005 19:26:32
GAME( 2005, ngbc, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "NeoGeo Battle Coliseum", GAME_FLAGS ) // Jun 25 2005 17:00:38 GAME( 2005, ngbc, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "NeoGeo Battle Coliseum", GAME_FLAGS ) // Jun 25 2005 17:00:38
GAME( 2005, ngbcj, ngbc, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "NeoGeo Battle Coliseum (Japan)", GAME_FLAGS ) // Jun 25 2005 17:00:38 GAME( 2005, ngbcj, ngbc, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "NeoGeo Battle Coliseum (Japan)", GAME_FLAGS ) // Jun 25 2005 17:00:38
GAME( 2005, samsptk, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "Samurai Spirits Tenkaichi Kenkakuden", GAME_FLAGS ) // Aug 05 2005 16:43:48 GAME( 2005, samsptk, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "Samurai Spirits Tenkaichi Kenkakuden", GAME_FLAGS ) // Aug 05 2005 16:43:48
GAME( 2005, kofxi, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "The King of Fighters XI", GAME_FLAGS ) // Aug 07 2005 18:11:25 GAME( 2005, kofxi, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy / SNK Playmore", "The King of Fighters XI", GAME_FLAGS ) // Aug 07 2005 18:11:25
GAME( 2005, fotns, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Arc System Works / Sega", "Fist Of The North Star", GAME_FLAGS ) // Nov 28 2005 21:04:40 GAME( 2005, fotns, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Arc System Works / Sega", "Fist Of The North Star", GAME_FLAGS ) // Nov 28 2005 21:04:40
GAME( 2006, mslug6, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sega / SNK Playmore", "Metal Slug 6", GAME_FLAGS) // Jan 13 2006 00:49:12 GAME( 2006, mslug6, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sega / SNK Playmore", "Metal Slug 6", GAME_FLAGS) // Jan 13 2006 00:49:12
GAME( 2006, xtrmhnt2, awbios, aw2c, aw2c, atomiswave_state, xtrmhnt2, ROT0, "Sega", "Extreme Hunting 2", GAME_FLAGS ) // May 26 2006 14:03:22 GAME( 2006, xtrmhnt2, awbios, aw2c, aw2c, atomiswave_state, xtrmhnt2, ROT0, "Sega", "Extreme Hunting 2", GAME_FLAGS ) // May 26 2006 14:03:22
GAME( 2006, dirtypig, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Dirty Pigskin Football", GAME_FLAGS) // Sep 10 2006 20:24:14 GAME( 2006, dirtypig, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sammy", "Dirty Pigskin Football", GAME_FLAGS) // Sep 10 2006 20:24:14
GAME( 2008, claychal, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sega", "Sega Clay Challenge", GAME_FLAGS ) // Oct 15 2008 16:08:20 GAME( 2008, claychal, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sega", "Sega Clay Challenge", GAME_FLAGS ) // Oct 15 2008 16:08:20
GAME( 2009, basschalo, basschal, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sega", "Sega Bass Fishing Challenge", GAME_FLAGS ) // Feb 08 2009 22:35:34 GAME( 2009, basschalo, basschal, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sega", "Sega Bass Fishing Challenge", GAME_FLAGS ) // Feb 08 2009 22:35:34
GAME( 2009, basschal, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sega", "Sega Bass Fishing Challenge Version A", GAME_FLAGS ) // Jul 25 2009 16:27:40 GAME( 2009, basschal, awbios, aw2c, aw2c, atomiswave_state, atomiswave, ROT0, "Sega", "Sega Bass Fishing Challenge Version A", GAME_FLAGS ) // Jul 25 2009 16:27:40

4
src/mame/drivers/segasp.cpp
View File

@ -191,10 +191,10 @@ void segasp_state::segasp_map(address_map &map)
map(0x005f7c00, 0x005f7cff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::pd_dma_map)); map(0x005f7c00, 0x005f7cff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::pd_dma_map));
map(0x005f8000, 0x005f9fff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::ta_map)); map(0x005f8000, 0x005f9fff).mirror(0x02000000).m(m_powervr2, FUNC(powervr2_device::ta_map));
map(0x00600000, 0x006007ff).mirror(0x02000000).rw(this, FUNC(segasp_state::dc_modem_r), FUNC(segasp_state::dc_modem_w)); map(0x00600000, 0x006007ff).mirror(0x02000000).rw(this, FUNC(segasp_state::dc_modem_r), FUNC(segasp_state::dc_modem_w));
map(0x00700000, 0x00707fff).mirror(0x02000000).rw(m_aica, FUNC(aica_device::host_aica_reg_r), FUNC(aica_device::host_aica_reg_w)); map(0x00700000, 0x00707fff).mirror(0x02000000).rw(this, FUNC(segasp_state::dc_aica_reg_r), FUNC(segasp_state::dc_aica_reg_w));
map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff); map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff);
map(0x00800000, 0x00ffffff).mirror(0x02000000).rw(m_aica, FUNC(aica_device::ram_host_r), FUNC(aica_device::ram_w)); // sound RAM (8 MB) map(0x00800000, 0x00ffffff).mirror(0x02000000).rw(this, FUNC(segasp_state::sh4_soundram_r), FUNC(segasp_state::sh4_soundram_w)); // sound RAM (8 MB)
/* External Device */ /* External Device */
map(0x01000000, 0x0100ffff).ram(); // banked access to ROM/NET board address space, mainly backup SRAM and ATA map(0x01000000, 0x0100ffff).ram(); // banked access to ROM/NET board address space, mainly backup SRAM and ATA

35
src/mame/includes/dc.h
View File

@ -18,22 +18,24 @@
class dc_state : public driver_device class dc_state : public driver_device
{ {
public: public:
dc_state(const machine_config &mconfig, device_type type, const char *tag) dc_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag) : driver_device(mconfig, type, tag),
, dc_framebuffer_ram(*this, "frameram") dc_framebuffer_ram(*this, "frameram"),
, dc_texture_ram(*this, "dc_texture_ram") dc_texture_ram(*this, "dc_texture_ram"),
, dc_ram(*this, "dc_ram") dc_sound_ram(*this, "dc_sound_ram"),
, m_maincpu(*this, "maincpu") dc_ram(*this, "dc_ram"),
, m_powervr2(*this, "powervr2") m_maincpu(*this, "maincpu"),
, m_maple(*this, "maple_dc") m_soundcpu(*this, "soundcpu"),
, m_naomig1(*this, "rom_board") m_powervr2(*this, "powervr2"),
, m_aica(*this, "aica") m_maple(*this, "maple_dc"),
{ } m_naomig1(*this, "rom_board"),
m_aica(*this, "aica") { }
required_shared_ptr<uint64_t> dc_framebuffer_ram; // '32-bit access area' required_shared_ptr<uint64_t> dc_framebuffer_ram; // '32-bit access area'
required_shared_ptr<uint64_t> dc_texture_ram; // '64-bit access area' required_shared_ptr<uint64_t> dc_texture_ram; // '64-bit access area'
required_shared_ptr<uint32_t> dc_sound_ram;
required_shared_ptr<uint64_t> dc_ram; required_shared_ptr<uint64_t> dc_ram;
/* machine related */ /* machine related */
@ -57,6 +59,10 @@ public:
virtual void machine_reset() override; virtual void machine_reset() override;
TIMER_CALLBACK_MEMBER(g2_dma_irq); TIMER_CALLBACK_MEMBER(g2_dma_irq);
TIMER_CALLBACK_MEMBER(ch2_dma_irq); TIMER_CALLBACK_MEMBER(ch2_dma_irq);
DECLARE_READ32_MEMBER(dc_aica_reg_r);
DECLARE_WRITE32_MEMBER(dc_aica_reg_w);
DECLARE_READ32_MEMBER(dc_arm_aica_r);
DECLARE_WRITE32_MEMBER(dc_arm_aica_w);
void g2_dma_execute(address_space &space, int channel); void g2_dma_execute(address_space &space, int channel);
inline int decode_reg32_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift); inline int decode_reg32_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift);
inline int decode_reg3216_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift); inline int decode_reg3216_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift);
@ -73,10 +79,14 @@ public:
DECLARE_WRITE64_MEMBER( dc_modem_w ); DECLARE_WRITE64_MEMBER( dc_modem_w );
DECLARE_WRITE8_MEMBER( g1_irq ); DECLARE_WRITE8_MEMBER( g1_irq );
DECLARE_WRITE8_MEMBER( pvr_irq ); DECLARE_WRITE8_MEMBER( pvr_irq );
DECLARE_READ64_MEMBER( sh4_soundram_r );
DECLARE_WRITE64_MEMBER( sh4_soundram_w );
DECLARE_WRITE_LINE_MEMBER(aica_irq);
DECLARE_WRITE_LINE_MEMBER(sh4_aica_irq); DECLARE_WRITE_LINE_MEMBER(sh4_aica_irq);
required_device<sh4_base_device> m_maincpu; required_device<sh4_base_device> m_maincpu;
required_device<cpu_device> m_soundcpu;
required_device<powervr2_device> m_powervr2; required_device<powervr2_device> m_powervr2;
required_device<maple_dc_device> m_maple; required_device<maple_dc_device> m_maple;
optional_device<naomi_g1_device> m_naomig1; optional_device<naomi_g1_device> m_naomig1;
@ -87,6 +97,7 @@ public:
DECLARE_MACHINE_RESET(dc_console); DECLARE_MACHINE_RESET(dc_console);
void naomi_aw_base(machine_config &config); void naomi_aw_base(machine_config &config);
void dc_audio_map(address_map &map);
}; };
/*--------- Ch2-DMA Control Registers ----------*/ /*--------- Ch2-DMA Control Registers ----------*/

1
src/mame/includes/dccons.h
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@ -49,6 +49,7 @@ public:
static void gdrom_config(device_t *device); static void gdrom_config(device_t *device);
void dc(machine_config &config); void dc(machine_config &config);
void dc_audio_map(address_map &map);
void dc_map(address_map &map); void dc_map(address_map &map);
void dc_port(address_map &map); void dc_port(address_map &map);
private: private:

31
src/mame/includes/naomi.h
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@ -39,12 +39,12 @@ enum {
class naomi_state : public dc_state class naomi_state : public dc_state
{ {
public: public:
naomi_state(const machine_config &mconfig, device_type type, const char *tag) naomi_state(const machine_config &mconfig, device_type type, const char *tag)
: dc_state(mconfig, type, tag) : dc_state(mconfig, type, tag),
, m_eeprom(*this, "main_eeprom") m_eeprom(*this, "main_eeprom"),
, m_rombase(*this, "rombase") m_rombase(*this, "rombase")
{ } { }
required_device<eeprom_serial_93cxx_device> m_eeprom; required_device<eeprom_serial_93cxx_device> m_eeprom;
optional_shared_ptr<uint64_t> m_rombase; optional_shared_ptr<uint64_t> m_rombase;
@ -95,12 +95,11 @@ class naomi2_state : public naomi_state
{ {
public: public:
naomi2_state(const machine_config &mconfig, device_type type, const char *tag) naomi2_state(const machine_config &mconfig, device_type type, const char *tag)
: naomi_state(mconfig, type, tag) : naomi_state(mconfig, type, tag),
, m_pvr2_texture_ram(*this, "textureram2") m_pvr2_texture_ram(*this, "textureram2"),
, m_pvr2_framebuffer_ram(*this, "frameram2") m_pvr2_framebuffer_ram(*this, "frameram2"),
, m_elan_ram(*this, "elan_ram") m_elan_ram(*this, "elan_ram"),
, m_powervr2_slave(*this, "powervr2_slave") m_powervr2_slave(*this, "powervr2_slave") { }
{ }
required_shared_ptr<uint64_t> m_pvr2_texture_ram; required_shared_ptr<uint64_t> m_pvr2_texture_ram;
required_shared_ptr<uint64_t> m_pvr2_framebuffer_ram; required_shared_ptr<uint64_t> m_pvr2_framebuffer_ram;
@ -120,12 +119,14 @@ class atomiswave_state : public dc_state
{ {
public: public:
atomiswave_state(const machine_config &mconfig, device_type type, const char *tag) atomiswave_state(const machine_config &mconfig, device_type type, const char *tag)
: dc_state(mconfig, type, tag) : dc_state(mconfig, type, tag),
, m_awflash(*this, "awflash") m_awflash(*this, "awflash")
{ } { }
required_device<macronix_29l001mc_device> m_awflash; required_device<macronix_29l001mc_device> m_awflash;
DECLARE_READ64_MEMBER( aw_flash_r );
DECLARE_WRITE64_MEMBER( aw_flash_w );
DECLARE_READ64_MEMBER( aw_modem_r ); DECLARE_READ64_MEMBER( aw_modem_r );
DECLARE_WRITE64_MEMBER( aw_modem_w ); DECLARE_WRITE64_MEMBER( aw_modem_w );

6
src/mame/includes/segasp.h
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@ -12,9 +12,9 @@ class segasp_state : public naomi_state
{ {
public: public:
segasp_state(const machine_config &mconfig, device_type type, const char *tag) segasp_state(const machine_config &mconfig, device_type type, const char *tag)
: naomi_state(mconfig, type, tag) : naomi_state(mconfig, type, tag),
, m_sp_eeprom(*this, "sp_eeprom") m_sp_eeprom(*this, "sp_eeprom")
{ } { }
required_device<eeprom_serial_93cxx_device> m_sp_eeprom; required_device<eeprom_serial_93cxx_device> m_sp_eeprom;
DECLARE_DRIVER_INIT(segasp); DECLARE_DRIVER_INIT(segasp);

67
src/mame/machine/dc.cpp
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@ -658,6 +658,7 @@ void dc_state::machine_start()
// save states // save states
save_pointer(NAME(dc_sysctrl_regs), 0x200/4); save_pointer(NAME(dc_sysctrl_regs), 0x200/4);
save_pointer(NAME(g2bus_regs), 0x100/4); save_pointer(NAME(g2bus_regs), 0x100/4);
save_pointer(NAME(dc_sound_ram.target()),dc_sound_ram.bytes()/4);
SAVE_G2DMA(0) SAVE_G2DMA(0)
SAVE_G2DMA(1) SAVE_G2DMA(1)
SAVE_G2DMA(2) SAVE_G2DMA(2)
@ -666,11 +667,76 @@ void dc_state::machine_start()
void dc_state::machine_reset() void dc_state::machine_reset()
{ {
/* halt the ARM7 */
m_armrst = 1;
m_soundcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
memset(dc_sysctrl_regs, 0, sizeof(dc_sysctrl_regs)); memset(dc_sysctrl_regs, 0, sizeof(dc_sysctrl_regs));
dc_sysctrl_regs[SB_SBREV] = 0x0b; dc_sysctrl_regs[SB_SBREV] = 0x0b;
} }
READ32_MEMBER(dc_state::dc_aica_reg_r)
{
// osd_printf_verbose("%s",string_format("AICA REG: [%08x] read %x, mask %x\n", 0x700000+reg*4, (uint64_t)offset, mem_mask).c_str());
if(offset == 0x2c00/4)
return m_armrst;
return m_aica->read(space, offset*2, 0xffff);
}
WRITE32_MEMBER(dc_state::dc_aica_reg_w)
{
if (offset == (0x2c00/4))
{
if(ACCESSING_BITS_0_7)
{
m_armrst = data & 1;
if (data & 1)
{
/* halt the ARM7 */
m_soundcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
}
else
{
/* it's alive ! */
m_soundcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
}
}
}
m_aica->write(space, offset*2, data, 0xffff);
// osd_printf_verbose("%s",string_format("AICA REG: [%08x=%x] write %x to %x, mask %x\n", 0x700000+reg*4, data, offset, mem_mask).c_str());
}
READ32_MEMBER(dc_state::dc_arm_aica_r)
{
return m_aica->read(space, offset*2, 0xffff) & 0xffff;
}
WRITE32_MEMBER(dc_state::dc_arm_aica_w)
{
m_aica->write(space, offset*2, data, mem_mask&0xffff);
}
READ64_MEMBER(dc_state::sh4_soundram_r )
{
return *((uint64_t *)dc_sound_ram.target()+offset);
}
WRITE64_MEMBER(dc_state::sh4_soundram_w )
{
COMBINE_DATA((uint64_t *)dc_sound_ram.target() + offset);
}
WRITE_LINE_MEMBER(dc_state::aica_irq)
{
m_soundcpu->set_input_line(ARM7_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
}
WRITE_LINE_MEMBER(dc_state::sh4_aica_irq) WRITE_LINE_MEMBER(dc_state::sh4_aica_irq)
{ {
if(state) if(state)
@ -685,6 +751,7 @@ MACHINE_RESET_MEMBER(dc_state,dc_console)
{ {
dc_state::machine_reset(); dc_state::machine_reset();
m_maincpu->sh2drc_set_options(SH2DRC_STRICT_VERIFY | SH2DRC_STRICT_PCREL); m_maincpu->sh2drc_set_options(SH2DRC_STRICT_VERIFY | SH2DRC_STRICT_PCREL);
m_aica->set_ram_base(dc_sound_ram, 2*1024*1024);
} }
TIMER_DEVICE_CALLBACK_MEMBER(dc_state::dc_scanline) TIMER_DEVICE_CALLBACK_MEMBER(dc_state::dc_scanline)