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cischeat.cpp: reworked interrupt generation, fixed attract mode desyncs in Big Run [Angelo Salese]

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angelosa 2018-06-29 00:11:12 +02:00
parent 5854421008
commit 4b6a420df5
1 changed files with 19 additions and 10 deletions
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29
src/mame/drivers/cischeat.cpp
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@ -227,7 +227,7 @@ void cischeat_state::bigrun_map(address_map &map)
map(0x082308, 0x082309).w(FUNC(cischeat_state::cischeat_comms_w)); map(0x082308, 0x082309).w(FUNC(cischeat_state::cischeat_comms_w));
map(0x082400, 0x082401).w(FUNC(cischeat_state::active_layers_w)); map(0x082400, 0x082401).w(FUNC(cischeat_state::active_layers_w));
/* It's actually 0x840000-0x847ff, divided in four banks and shared with other boards. /* It's actually 0x84000-0x847ff, divided in four banks and shared with other boards.
Each board expects reads from the other boards and writes to own bank. Each board expects reads from the other boards and writes to own bank.
Amusingly, if you run the communication test as ID = X then soft reset -> ID = Y, what was at ID = X gets an OK in the second test Amusingly, if you run the communication test as ID = X then soft reset -> ID = Y, what was at ID = X gets an OK in the second test
so it's likely to be the only thing needed. */ so it's likely to be the only thing needed. */
@ -421,7 +421,7 @@ void wildplt_state::wildplt_map(address_map &map)
map(0x082308, 0x082309).nopr().w(FUNC(cischeat_state::f1gpstar_comms_w)); map(0x082308, 0x082309).nopr().w(FUNC(cischeat_state::f1gpstar_comms_w));
map(0x082400, 0x082401).w(FUNC(cischeat_state::active_layers_w)); map(0x082400, 0x082401).w(FUNC(cischeat_state::active_layers_w));
// AM_RANGE(0x088000, 0x088fff) AM_RAM // Linking with other units // map(0x088000, 0x088fff).ram(); // Linking with other units (not present on this)
map(0x090000, 0x097fff).ram().share("share2"); // Sharedram with sub CPU#2 map(0x090000, 0x097fff).ram().share("share2"); // Sharedram with sub CPU#2
map(0x098000, 0x09ffff).ram().share("share1"); // Sharedram with sub CPU#1 map(0x098000, 0x09ffff).ram().share("share1"); // Sharedram with sub CPU#1
@ -1914,22 +1914,31 @@ GFXDECODE_END
Big Run, Cisco Heat, F1 GrandPrix Star Big Run, Cisco Heat, F1 GrandPrix Star
**************************************************************************/ **************************************************************************/
/* // TODO: irq generation is unknown, as usual with Jaleco/NMK HW
irq 1 is comms related, presumably the bridge chip is capable of sending the irq signal at given times. Wild Pilot of course doesn't need it. // - irq 1 is comms related, presumably the bridge chip is capable of sending the irq signal at given times.
irq 2/4 controls gameplay speed, currently unknown about the timing // Wild Pilot of course doesn't need it.
*/ // - irq 2/4 controls gameplay speed, currently unknown about the timing
// - 2 updates palettes while 4 is vblank?
// - Calling 2 every frame causes attract mode to desync in Big Run.
// - Not calling 1 in Big Run causes service mode to not work at all, so even if the comms doesn't work
// something still triggers it somehow?
TIMER_DEVICE_CALLBACK_MEMBER(cischeat_state::bigrun_scanline) TIMER_DEVICE_CALLBACK_MEMBER(cischeat_state::bigrun_scanline)
{ {
int scanline = param; int scanline = param;
if(m_screen->frame_number() & 1)
{
if(scanline == 240)
m_cpu1->set_input_line(1, HOLD_LINE);
return;
}
if(scanline == 240) // vblank-out irq if(scanline == 240) // vblank-out irq
m_cpu1->set_input_line(m_screen->frame_number() & 1 ? 4 : 1, HOLD_LINE); m_cpu1->set_input_line(4, HOLD_LINE);
if(scanline == 0) if(scanline == 0)
m_cpu1->set_input_line(2, HOLD_LINE); m_cpu1->set_input_line(2, HOLD_LINE);
// if(scanline == 69)
// m_cpu1->set_input_line(1, HOLD_LINE);
} }
WRITE_LINE_MEMBER(cischeat_state::sound_irq) WRITE_LINE_MEMBER(cischeat_state::sound_irq)