mirror of
https://github.com/holub/mame
synced 2025-07-01 08:18:59 +03:00
new device seeq8003
This commit is contained in:
Patrick Mackinlay
parent
e78ac44ab0
commit
4b70016e83
@ -4079,3 +4079,15 @@ if (MACHINES["XC1700E"]~=null) then
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MAME_DIR .. "src/devices/machine/xc1700e.h",
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MAME_DIR .. "src/devices/machine/xc1700e.h",
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}
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}
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end
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end
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---------------------------------------------------
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--
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--@src/devices/machine/edlc.h,MACHINES["EDLC"] = true
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---------------------------------------------------
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if (MACHINES["EDLC"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/edlc.cpp",
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MAME_DIR .. "src/devices/machine/edlc.h",
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}
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end
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@ -710,6 +710,7 @@ MACHINES["AIC6250"] = true
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MACHINES["DC7085"] = true
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MACHINES["DC7085"] = true
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MACHINES["I82357"] = true
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MACHINES["I82357"] = true
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MACHINES["XC1700E"] = true
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MACHINES["XC1700E"] = true
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MACHINES["EDLC"] = true
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--------------------------------------------------
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--------------------------------------------------
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-- specify available bus cores
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-- specify available bus cores
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318
src/devices/machine/edlc.cpp
Normal file
318
src/devices/machine/edlc.cpp
Normal file
@ -0,0 +1,318 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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/*
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* An emulation of the SEEQ 8003 Ethernet Data Link Controller.
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*
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* This implementation uses transmit/receive fifos which hold entire frames,
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* rather than the 16-byte fifos of the real device to simplify logic. Also,
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* the bidirectional RxTxEOF line is split into separate read/write handlers
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* which must be used strictly as follows:
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*
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* - rxeof_r() must be read before fifo_r()
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* - txeof_w() must be written after fifo_w()
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*
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* Sources:
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* - http://www.bitsavers.org/components/seeq/_dataBooks/1985_SEEQ_Data_Book.pdf
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*
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* TODO:
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* - RxDC (discard) and TxRET (retransmit) logic
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* - 80c03 support
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* - testing
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*/
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#include "emu.h"
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#include "edlc.h"
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#include "hashing.h"
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#define LOG_GENERAL (1U << 0)
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#define LOG_FRAMES (1U << 1)
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#define LOG_FILTER (1U << 2)
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//#define VERBOSE (LOG_GENERAL|LOG_FRAMES|LOG_FILTER)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(SEEQ8003, seeq8003_device, "seeq8003", "SEEQ 8003 EDLC")
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static const u8 ETH_BROADCAST[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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seeq8003_device::seeq8003_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
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: device_t(mconfig, SEEQ8003, tag, owner, clock)
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, device_network_interface(mconfig, *this, 10.0f)
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, m_out_int(*this)
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, m_out_rxrdy(*this)
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, m_out_txrdy(*this)
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{
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}
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void seeq8003_device::device_start()
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{
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m_out_int.resolve_safe();
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m_out_rxrdy.resolve_safe();
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m_out_txrdy.resolve_safe();
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save_item(NAME(m_int_state));
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save_item(NAME(m_station_address));
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save_item(NAME(m_rx_status));
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save_item(NAME(m_tx_status));
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save_item(NAME(m_rx_command));
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save_item(NAME(m_tx_command));
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m_tx_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(seeq8003_device::transmit), this));
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m_int_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(seeq8003_device::interrupt), this));
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m_int_state = 0;
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}
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void seeq8003_device::device_reset()
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{
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m_rx_status = RXS_O;
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m_tx_status = TXS_O;
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m_rx_command = 0;
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m_tx_command = 0;
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m_rx_fifo.clear();
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m_tx_fifo.clear();
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m_out_rxrdy(0);
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if (m_dev)
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m_out_txrdy(1);
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interrupt();
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}
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int seeq8003_device::recv_start_cb(u8 *buf, int length)
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{
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// check receiver disabled
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if ((m_rx_command & RXC_M) == RXC_M0)
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return 0;
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if (address_filter(buf))
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{
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LOG("receiving frame length %d\n", length);
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dump_bytes(buf, length);
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return receive(buf, length);
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}
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return 0;
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}
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void seeq8003_device::map(address_map &map)
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{
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map.unmap_value_high();
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map(0, 0).w(FUNC(seeq8003_device::station_address_w<0>));
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map(1, 1).w(FUNC(seeq8003_device::station_address_w<1>));
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map(2, 2).w(FUNC(seeq8003_device::station_address_w<2>));
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map(3, 3).w(FUNC(seeq8003_device::station_address_w<3>));
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map(4, 4).w(FUNC(seeq8003_device::station_address_w<4>));
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map(5, 5).w(FUNC(seeq8003_device::station_address_w<5>));
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map(6, 6).rw(FUNC(seeq8003_device::rx_status_r), FUNC(seeq8003_device::rx_command_w));
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map(7, 7).rw(FUNC(seeq8003_device::tx_status_r), FUNC(seeq8003_device::tx_command_w));
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}
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u8 seeq8003_device::fifo_r()
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{
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if (m_rx_fifo.empty())
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fatalerror("seeq8003_device::fifo_r: fifo empty\n");
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u8 const data = m_rx_fifo.dequeue();
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if (m_rx_fifo.empty())
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{
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// disable rx fifo
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m_out_rxrdy(0);
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// schedule interrupt
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m_int_timer->adjust(attotime::zero);
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}
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return data;
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}
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int seeq8003_device::rxeof_r()
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{
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return m_rx_fifo.queue_length() == 1;
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}
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void seeq8003_device::fifo_w(u8 data)
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{
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if (m_tx_fifo.full())
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fatalerror("seeq8003_device::fifo_w: fifo full\n");
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m_tx_fifo.enqueue(data);
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if (m_tx_fifo.full())
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m_out_txrdy(0);
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}
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void seeq8003_device::txeof_w(int state)
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{
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if (state)
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{
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// disable tx fifo
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m_out_txrdy(0);
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// schedule transmit
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m_tx_timer->adjust(attotime::zero);
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}
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}
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u8 seeq8003_device::rx_status_r()
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{
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u8 const data = m_rx_status;
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// clear interrupt
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m_rx_status |= RXS_O;
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m_int_timer->adjust(attotime::zero);
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return data;
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}
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u8 seeq8003_device::tx_status_r()
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{
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u8 const data = m_tx_status;
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// clear interrupt
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m_tx_status |= TXS_O;
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m_int_timer->adjust(attotime::zero);
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return data;
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}
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void seeq8003_device::transmit(void *ptr, int param)
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{
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if (m_tx_fifo.queue_length())
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{
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u8 buf[MAX_FRAME_SIZE];
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int length = 0;
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// dequeue to buffer
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while (!m_tx_fifo.empty())
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buf[length++] = m_tx_fifo.dequeue();
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// compute and append fcs
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u32 const fcs = util::crc32_creator::simple(buf, length);
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buf[length++] = (fcs >> 0) & 0xff;
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buf[length++] = (fcs >> 8) & 0xff;
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buf[length++] = (fcs >> 16) & 0xff;
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buf[length++] = (fcs >> 24) & 0xff;
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LOG("transmitting frame length %d\n", length);
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dump_bytes(buf, length);
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// transmit the frame
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send(buf, length);
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// TODO: transmit errors/TxRET
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// update status
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m_tx_status = TXS_S;
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}
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else
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m_tx_status = TXS_U;
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// enable tx fifo
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m_out_txrdy(1);
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interrupt();
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}
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int seeq8003_device::receive(u8 *buf, int length)
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{
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// discard if rx status has not been read
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// TODO: RxDC
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if (!(m_rx_status & RXS_O))
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return 0;
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m_rx_status = RXS_E;
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// check for errors
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u32 const fcs = util::crc32_creator::simple(buf, length);
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if (length < 64)
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m_rx_status |= RXS_S;
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else if (~fcs != FCS_RESIDUE)
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m_rx_status |= RXS_C;
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else
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m_rx_status |= RXS_G;
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// enqueue from buffer
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for (unsigned i = 0; i < length - 4; i++)
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m_rx_fifo.enqueue(buf[i]);
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// enable rx fifo
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m_out_rxrdy(1);
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return length;
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}
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void seeq8003_device::interrupt(void *ptr, int param)
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{
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int const state =
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(!(m_tx_status & TXS_O) && (m_tx_status & m_tx_command & TXS_M)) ||
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(!(m_rx_status & RXS_O) && (m_rx_status & m_rx_command & RXS_M));
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// TODO: assert RxDC for masked rx crc or short frame errors
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if (state != m_int_state)
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{
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m_int_state = state;
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m_out_int(state);
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}
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}
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bool seeq8003_device::address_filter(u8 *address)
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{
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LOGMASKED(LOG_FILTER, "address_filter testing destination address %02x:%02x:%02x:%02x:%02x:%02x\n",
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address[0], address[1], address[2], address[3], address[4], address[5]);
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if ((m_rx_command & RXC_M) == RXC_M1)
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{
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LOG("address_filter accepted: promiscuous mode enabled\n");
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return true;
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}
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// ethernet broadcast
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if (!memcmp(address, ETH_BROADCAST, 6))
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{
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LOGMASKED(LOG_FILTER, "address_filter accepted: broadcast\n");
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return true;
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}
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// station address
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if (!memcmp(address, m_station_address, 6))
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{
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LOGMASKED(LOG_FILTER, "address_filter accepted: station address match\n");
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return true;
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}
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// ethernet multicast
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if (((m_rx_command & RXC_M) == RXC_M3) && (address[0] & 0x1))
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{
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LOGMASKED(LOG_FILTER, "address_filter accepted: multicast address match\n");
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return true;
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}
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return false;
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}
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void seeq8003_device::dump_bytes(u8 *buf, int length)
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{
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if (VERBOSE & LOG_FRAMES)
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{
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// pad frame with zeros to 8-byte boundary
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for (int i = 0; i < 8 - (length % 8); i++)
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buf[length + i] = 0;
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// dump length / 8 (rounded up) groups of 8 bytes
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for (int i = 0; i < (length + 7) / 8; i++)
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LOGMASKED(LOG_FRAMES, "%02x %02x %02x %02x %02x %02x %02x %02x\n",
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buf[i * 8 + 0], buf[i * 8 + 1], buf[i * 8 + 2], buf[i * 8 + 3],
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buf[i * 8 + 4], buf[i * 8 + 5], buf[i * 8 + 6], buf[i * 8 + 7]);
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}
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}
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125
src/devices/machine/edlc.h
Normal file
125
src/devices/machine/edlc.h
Normal file
@ -0,0 +1,125 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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#ifndef MAME_MACHINE_EDLC_H
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#define MAME_MACHINE_EDLC_H
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#pragma once
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class seeq8003_device :
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public device_t,
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public device_network_interface
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{
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public:
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// callback configuration
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auto out_int_cb() { return m_out_int.bind(); }
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auto out_rxrdy_cb() { return m_out_rxrdy.bind(); }
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auto out_txrdy_cb() { return m_out_txrdy.bind(); }
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seeq8003_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock = 0);
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// host interface
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void map(address_map &map);
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u8 fifo_r();
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int rxeof_r();
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void fifo_w(u8 data);
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void txeof_w(int state);
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protected:
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// device_t overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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// device_network_interface overrides
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virtual int recv_start_cb(u8 *buf, int length) override;
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// command/status interface
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template <unsigned N> void station_address_w(u8 data) { m_station_address[N] = data; }
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u8 rx_status_r();
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u8 tx_status_r();
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void rx_command_w(u8 data) { m_rx_command = data; }
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||||||
|
void tx_command_w(u8 data) { m_tx_command = data & TXC_M; }
|
||||||
|
|
||||||
|
// helpers
|
||||||
|
void transmit(void *ptr, int param);
|
||||||
|
int receive(u8 *buf, int length);
|
||||||
|
void interrupt(void *ptr = nullptr, int param = 0);
|
||||||
|
bool address_filter(u8 *address);
|
||||||
|
void dump_bytes(u8 *buf, int length);
|
||||||
|
|
||||||
|
// constants and masks
|
||||||
|
static const unsigned MAX_FRAME_SIZE = 1518;
|
||||||
|
static const u32 FCS_RESIDUE = 0xdebb20e3;
|
||||||
|
|
||||||
|
enum rx_status_mask : u8
|
||||||
|
{
|
||||||
|
RXS_V = 0x01, // received frame with overflow error
|
||||||
|
RXS_C = 0x02, // received frame with crc error
|
||||||
|
RXS_D = 0x04, // received frame with dribble error
|
||||||
|
RXS_S = 0x08, // received short frame
|
||||||
|
RXS_E = 0x10, // received end of frame
|
||||||
|
RXS_G = 0x20, // received good frame
|
||||||
|
RXS_O = 0x80, // old/new status
|
||||||
|
|
||||||
|
RXS_M = 0x3f, // mask
|
||||||
|
};
|
||||||
|
enum rx_command_mask : u8
|
||||||
|
{
|
||||||
|
RXC_V = 0x01, // interrupt on receive overflow error
|
||||||
|
RXC_C = 0x02, // interrupt on receive crc error
|
||||||
|
RXC_D = 0x04, // interrupt on receive dribble error
|
||||||
|
RXC_S = 0x08, // interrupt on short frame
|
||||||
|
RXC_E = 0x10, // interrupt on end of frame
|
||||||
|
RXC_G = 0x20, // interrupt on good frame
|
||||||
|
RXC_M = 0xc0, // match mode
|
||||||
|
};
|
||||||
|
enum rx_match_mask : u8
|
||||||
|
{
|
||||||
|
RXC_M0 = 0x00, // receiver disable
|
||||||
|
RXC_M1 = 0x40, // receive all frames
|
||||||
|
RXC_M2 = 0x80, // receive station or broadcast frames
|
||||||
|
RXC_M3 = 0xc0, // receive station, broadcast/multicast frames
|
||||||
|
};
|
||||||
|
enum tx_status_mask : u8
|
||||||
|
{
|
||||||
|
TXS_U = 0x01, // transmit underflow
|
||||||
|
TXS_C = 0x02, // transmit collision
|
||||||
|
TXS_R = 0x04, // 16 transmission attempts
|
||||||
|
TXS_S = 0x08, // transmission successful
|
||||||
|
TXS_O = 0x80, // old/new status
|
||||||
|
|
||||||
|
TXS_M = 0x0f, // mask
|
||||||
|
};
|
||||||
|
enum tx_command_mask : u8
|
||||||
|
{
|
||||||
|
TXC_U = 0x01, // interrupt on transmit underflow
|
||||||
|
TXC_C = 0x02, // interrupt on transmit collision
|
||||||
|
TXC_R = 0x04, // interrupt on 16 transmission attempts
|
||||||
|
TXC_S = 0x08, // interrupt on transmit success
|
||||||
|
|
||||||
|
TXC_M = 0x0f, // write mask
|
||||||
|
};
|
||||||
|
|
||||||
|
private:
|
||||||
|
emu_timer *m_tx_timer;
|
||||||
|
emu_timer *m_int_timer;
|
||||||
|
|
||||||
|
// device state
|
||||||
|
devcb_write_line m_out_int;
|
||||||
|
devcb_write_line m_out_rxrdy;
|
||||||
|
devcb_write_line m_out_txrdy;
|
||||||
|
|
||||||
|
int m_int_state;
|
||||||
|
u8 m_station_address[6];
|
||||||
|
u8 m_rx_status;
|
||||||
|
u8 m_tx_status;
|
||||||
|
u8 m_rx_command;
|
||||||
|
u8 m_tx_command;
|
||||||
|
|
||||||
|
util::fifo<u8, MAX_FRAME_SIZE> m_rx_fifo;
|
||||||
|
util::fifo<u8, MAX_FRAME_SIZE> m_tx_fifo;
|
||||||
|
};
|
||||||
|
|
||||||
|
DECLARE_DEVICE_TYPE(SEEQ8003, seeq8003_device)
|
||||||
|
|
||||||
|
#endif // MAME_MACHINE_EDLC_H
|
||||||
Loading…
Reference in New Issue
Block a user