Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-21 16:01:56 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

netlist: remove duplicate device definitions.

Browse Source
This commit is contained in:
couriersud 2020-08-22 21:30:51 +02:00
parent ba8c8e79cf
commit 4b7eaf67e3
13 changed files with 114 additions and 409 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/lib/netlist/devices/net_lib.cpp
View File

@ -248,9 +248,7 @@ namespace devices
LIB_ENTRY(9310)
LIB_ENTRY(9314)
LIB_ENTRY(9316)
LIB_ENTRY(9321_GATE)
LIB_ENTRY(9321)
LIB_ENTRY(9322_GATE)
LIB_ENTRY(9322)
LIB_ENTRY(9334)
LIB_ENTRY(AM2847)
@ -259,7 +257,6 @@ namespace devices
LIB_ENTRY(CD4013)
LIB_ENTRY(CD4017)
LIB_ENTRY(CD4022)
LIB_ENTRY(CD4020_WI)
LIB_ENTRY(CD4020)
LIB_ENTRY(CD4024)
LIB_ENTRY(CD4053_GATE)

3
src/lib/netlist/devices/nld_4020.cpp
View File

@ -167,8 +167,7 @@ namespace netlist
NETLIB_DEVICE_IMPL(CD4020, "CD4020", "")
NETLIB_DEVICE_IMPL_ALIAS(CD4020_WI, CD4020, "CD4020_WI", "+IP,+RESET,+VDD,+VSS")
NETLIB_DEVICE_IMPL(CD4020, "CD4020", "+IP,+RESET,+VDD,+VSS")
NETLIB_DEVICE_IMPL(CD4024, "CD4024", "")

18
src/lib/netlist/devices/nld_4020.h
View File

@ -6,18 +6,12 @@
#include "netlist/nl_setup.h"
/* FIXME: only used in mario.c */
#define CD4020_WI(name, cIP, cRESET, cVDD, cVSS) \
NET_REGISTER_DEV(CD4020_WI, name) \
NET_CONNECT(name, IP, cIP) \
NET_CONNECT(name, RESET, cRESET) \
NET_CONNECT(name, VDD, cVDD) \
NET_CONNECT(name, VSS, cVSS)
// usage : CD4020(name)
#define CD4020(...) \
NET_REGISTER_DEVEXT(CD4020, __VA_ARGS__)
#define CD4020(name) \
NET_REGISTER_DEV(CD4020, name)
#define CD4024(name) \
NET_REGISTER_DEV(CD4024, name)
// usage : CD4024(name)
#define CD4024(...) \
NET_REGISTER_DEVEXT(CD4024, __VA_ARGS__)
#endif /* NLD_4020_H_ */

1
src/lib/netlist/devices/nld_74174.cpp
View File

@ -162,7 +162,6 @@ namespace devices
NETLIB_SUB(74174_GATE) F;
};
NETLIB_DEVICE_IMPL(74174_GATE, "TTL_74174_GATE", "")
NETLIB_DEVICE_IMPL(74174, "TTL_74174", "+CLK,+D1,+D2,+D3,+D4,+D5,+D6,+CLRQ,@VCC,@GND")
} //namespace devices

4
src/lib/netlist/devices/nld_74174.h
View File

@ -6,10 +6,6 @@
#include "netlist/nl_setup.h"
// usage: TTL_74174_GATE(name)
#define TTL_74174_GATE(...) \
NET_REGISTER_DEVEXT(TTL_74174_GATE, __VA_ARGS__)
// usage: TTL_74174(name, cCLK, cD1, cD2, cD3, cD4, cD5, cD6, cCLRQ)
#define TTL_74174(...) \
NET_REGISTER_DEVEXT(TTL_74174, __VA_ARGS__)

44
src/lib/netlist/devices/nld_9321.cpp
View File

@ -25,11 +25,12 @@ namespace netlist
{
namespace devices
{
class NETLIB_NAME(9321);
NETLIB_OBJECT(9321_GATE)
// FIXME: m_E should activate deactivate m_A
NETLIB_OBJECT(9321)
{
NETLIB_CONSTRUCTOR(9321_GATE)
NETLIB_CONSTRUCTOR(9321)
, m_enable(*this, "m_enable", true)
, m_o(*this, "m_o", 0)
, m_A(*this, 0, "A{}", NETLIB_DELEGATE(in))
@ -64,42 +65,7 @@ namespace netlist
nld_power_pins m_power_pins;
};
NETLIB_OBJECT(9321)
{
NETLIB_CONSTRUCTOR(9321)
, m_A(*this, "A")
, m_B(*this, "B")
{
register_subalias("AE1", m_A.m_E);
register_subalias("BE1", m_B.m_E);
register_subalias("AA0", m_A.m_A[0]);
register_subalias("BA0", m_B.m_A[0]);
register_subalias("AA1", m_A.m_A[1]);
register_subalias("BA1", m_B.m_A[1]);
register_subalias("AD0", m_A.m_D[0]);
register_subalias("BD0", m_B.m_D[0]);
register_subalias("AD1", m_A.m_D[1]);
register_subalias("BD1", m_B.m_D[1]);
register_subalias("AD2", m_A.m_D[2]);
register_subalias("BD2", m_B.m_D[2]);
register_subalias("AD3", m_A.m_D[3]);
register_subalias("BD3", m_B.m_D[3]);
connect("A.VCC", "B.VCC");
connect("A.GND", "B.GND");
register_subalias("GND", "A.GND");
register_subalias("VCC", "B.VCC");
}
friend class NETLIB_NAME(9321_dip);
private:
NETLIB_SUB(9321_GATE) m_A;
NETLIB_SUB(9321_GATE) m_B;
};
NETLIB_DEVICE_IMPL(9321_GATE, "TTL_9321_GATE", "")
NETLIB_DEVICE_IMPL(9321, "TTL_9321", "+SELECT,+A1,+B1,+A2,+B2,+A3,+B3,+A4,+B4,+STROBE,@VCC,@GND")
NETLIB_DEVICE_IMPL(9321, "TTL_9321", "+E,+A0,+A1")
} //namespace devices
} // namespace netlist

3
src/lib/netlist/devices/nld_9321.h
View File

@ -6,9 +6,6 @@
#include "netlist/nl_setup.h"
#define TTL_9321_GATE(...) \
NET_REGISTER_DEVEXT(TTL_9321_GATE, __VA_ARGS__)
// usage: TTL_9321(name, cAE, cA0, cA1, cBE, cB0, cB1)
#define TTL_9321(...) \
NET_REGISTER_DEVEXT(TTL_9321, __VA_ARGS__)

1
src/lib/netlist/devices/nld_9322.cpp
View File

@ -107,7 +107,6 @@ namespace netlist
};
NETLIB_DEVICE_IMPL(9322_GATE, "TTL_9322_GATE", "")
NETLIB_DEVICE_IMPL(9322, "TTL_9322", "+SELECT,+A1,+B1,+A2,+B2,+A3,+B3,+A4,+B4,+STROBE,@VCC,@GND")
} //namespace devices

3
src/lib/netlist/devices/nld_9322.h
View File

@ -6,9 +6,6 @@
#include "netlist/nl_setup.h"
#define TTL_9322_GATE(...) \
NET_REGISTER_DEVEXT(TTL_9322_GATE, __VA_ARGS__)
// usage: TTL_9322(name, cSELECT, cA1, cB1, cA2, cB2, cA3, cB3, cA4, cB4, cSTROBE)
#define TTL_9322(...) \
NET_REGISTER_DEVEXT(TTL_9322, __VA_ARGS__)

258
src/lib/netlist/macro/nlm_ttl74xx_lib.cpp
View File

@ -22,10 +22,10 @@
//- +---+---++---+
//-
static NETLIST_START(TTL_7400_DIP)
TTL_7400_GATE(A)
TTL_7400_GATE(B)
TTL_7400_GATE(C)
TTL_7400_GATE(D)
TTL_7400_NAND(A)
TTL_7400_NAND(B)
TTL_7400_NAND(C)
TTL_7400_NAND(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
@ -61,10 +61,10 @@ NETLIST_END()
//- +---+---++---+
//-
static NETLIST_START(TTL_7402_DIP)
TTL_7402_GATE(A)
TTL_7402_GATE(B)
TTL_7402_GATE(C)
TTL_7402_GATE(D)
TTL_7402_NOR(A)
TTL_7402_NOR(B)
TTL_7402_NOR(C)
TTL_7402_NOR(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
@ -98,12 +98,12 @@ NETLIST_END()
//- +---++---+
//-
static NETLIST_START(TTL_7404_DIP)
TTL_7404_GATE(A)
TTL_7404_GATE(B)
TTL_7404_GATE(C)
TTL_7404_GATE(D)
TTL_7404_GATE(E)
TTL_7404_GATE(F)
TTL_7404_INVERT(A)
TTL_7404_INVERT(B)
TTL_7404_INVERT(C)
TTL_7404_INVERT(D)
TTL_7404_INVERT(E)
TTL_7404_INVERT(F)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
@ -221,10 +221,10 @@ NETLIST_END()
//- +---+---++---+
//-
static NETLIST_START(TTL_7408_DIP)
TTL_7408_GATE(A)
TTL_7408_GATE(B)
TTL_7408_GATE(C)
TTL_7408_GATE(D)
TTL_7408_AND(A)
TTL_7408_AND(B)
TTL_7408_AND(C)
TTL_7408_AND(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
@ -260,9 +260,9 @@ NETLIST_END()
//- +---+---+---++---+
//-
static NETLIST_START(TTL_7410_DIP)
TTL_7410_GATE(A)
TTL_7410_GATE(B)
TTL_7410_GATE(C)
TTL_7410_NAND(A)
TTL_7410_NAND(B)
TTL_7410_NAND(C)
NET_C(A.VCC, B.VCC, C.VCC)
NET_C(A.GND, B.GND, C.GND)
@ -298,9 +298,9 @@ NETLIST_END()
//- +---+---+---++---+
//-
static NETLIST_START(TTL_7411_DIP)
TTL_7411_GATE(A)
TTL_7411_GATE(B)
TTL_7411_GATE(C)
TTL_7411_AND(A)
TTL_7411_AND(B)
TTL_7411_AND(C)
NET_C(A.VCC, B.VCC, C.VCC)
NET_C(A.GND, B.GND, C.GND)
@ -457,8 +457,8 @@ NETLIST_END()
//- +---+---+---+---++---+
//-
static NETLIST_START(TTL_7420_DIP)
TTL_7420_GATE(A)
TTL_7420_GATE(B)
TTL_7420_NAND(A)
TTL_7420_NAND(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
@ -496,8 +496,8 @@ NETLIST_END()
//- +---+---+---+---++---+
//-
static NETLIST_START(TTL_7421_DIP)
TTL_7421_GATE(A)
TTL_7421_GATE(B)
TTL_7421_AND(A)
TTL_7421_AND(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
@ -538,8 +538,8 @@ NETLIST_END()
//- +---+---+---+---+---++---+
//-
static NETLIST_START(TTL_7425_DIP)
TTL_7425_GATE(A)
TTL_7425_GATE(B)
TTL_7425_NOR(A)
TTL_7425_NOR(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
@ -577,9 +577,9 @@ NETLIST_END()
//- +---+---+---++---+
//-
static NETLIST_START(TTL_7427_DIP)
TTL_7427_GATE(A)
TTL_7427_GATE(B)
TTL_7427_GATE(C)
TTL_7427_NOR(A)
TTL_7427_NOR(B)
TTL_7427_NOR(C)
NET_C(A.VCC, B.VCC, C.VCC)
NET_C(A.GND, B.GND, C.GND)
@ -619,7 +619,7 @@ NETLIST_END()
//- +---+---+---+---+---+---+---+---++---+
//-
static NETLIST_START(TTL_7430_DIP)
TTL_7430_GATE(A)
TTL_7430_NAND(A)
NC_PIN(NC)
DIPPINS( /* +--------------+ */
@ -653,10 +653,10 @@ NETLIST_END()
//- +---+---++---+
//-
static NETLIST_START(TTL_7432_DIP)
TTL_7432_GATE(A)
TTL_7432_GATE(B)
TTL_7432_GATE(C)
TTL_7432_GATE(D)
TTL_7432_OR(A)
TTL_7432_OR(B)
TTL_7432_OR(C)
TTL_7432_OR(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
@ -693,10 +693,10 @@ NETLIST_END()
//- +---+---++---+
//-
static NETLIST_START(TTL_7437_DIP)
TTL_7437_GATE(A)
TTL_7437_GATE(B)
TTL_7437_GATE(C)
TTL_7437_GATE(D)
TTL_7437_NAND(A)
TTL_7437_NAND(B)
TTL_7437_NAND(C)
TTL_7437_NAND(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
@ -1202,10 +1202,10 @@ NETLIST_END()
//- +---+---++---+
//-
static NETLIST_START(TTL_7486_DIP)
TTL_7486_GATE(A)
TTL_7486_GATE(B)
TTL_7486_GATE(C)
TTL_7486_GATE(D)
TTL_7486_XOR(A)
TTL_7486_XOR(B)
TTL_7486_XOR(C)
TTL_7486_XOR(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
@ -2316,12 +2316,12 @@ NETLIST_END()
//- +------+-----+---++---+
//-
static NETLIST_START(TTL_74174_DIP)
TTL_74174_GATE(A)
TTL_74174_GATE(B)
TTL_74174_GATE(C)
TTL_74174_GATE(D)
TTL_74174_GATE(E)
TTL_74174_GATE(F)
TTL_74174(A)
TTL_74174(B)
TTL_74174(C)
TTL_74174(D)
TTL_74174(E)
TTL_74174(F)
DIPPINS( /* +--------------+ */
A.CLRQ, /* CLRQ |1 ++ 16| VCC */ A.VCC,
@ -2357,8 +2357,8 @@ NETLIST_END()
//- +---+---+---+---+---++---+
//-
static NETLIST_START(TTL_74260_DIP)
TTL_74260_GATE(A)
TTL_74260_GATE(B)
TTL_74260_NOR(A)
TTL_74260_NOR(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
@ -2846,25 +2846,17 @@ NETLIST_END()
//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006606.PDF
//-
static NETLIST_START(TTL_9322_DIP)
TTL_9322_GATE(A)
TTL_9322_GATE(B)
TTL_9322_GATE(C)
TTL_9322_GATE(D)
NET_C(A.SELECT, B.SELECT, C.SELECT, D.SELECT)
NET_C(A.STROBE, B.STROBE, C.STROBE, D.STROBE)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
TTL_9322(A)
DIPPINS( /* +--------------+ */
A.SELECT, /* SELECT |1 ++ 16| VCC */ A.VCC,
A.A, /* A1 |2 15| STROBE */ A.STROBE,
A.B, /* B1 |3 14| A4 */ D.A,
A.Y, /* Y1 |4 9322 13| B4 */ D.B,
B.A, /* A2 |5 12| Y4 */ D.Y,
B.B, /* B2 |6 11| A3 */ C.A,
B.Y, /* Y2 |7 10| B3 */ C.B,
A.GND, /* GND |8 9| Y3 */ C.Y
A.SELECT, /* SELECT |1 ++ 16| VCC */ A.VCC,
A.A1, /* A1 |2 15| STROBE */ A.STROBE,
A.B1, /* B1 |3 14| A4 */ A.A4,
A.Y1, /* Y1 |4 9322 13| B4 */ A.B4,
A.A2, /* A2 |5 12| Y4 */ A.Y4,
A.B2, /* B2 |6 11| A3 */ A.A3,
A.Y2, /* Y2 |7 10| B3 */ A.B3,
A.GND, /* GND |8 9| Y3 */ A.Y3
/* +--------------+ */
)
NETLIST_END()
@ -2876,8 +2868,8 @@ NETLIST_END()
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
//-
static NETLIST_START(TTL_9321_DIP)
TTL_9321_GATE(A)
TTL_9321_GATE(B)
TTL_9321(A)
TTL_9321(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
@ -2952,14 +2944,6 @@ NETLIST_START(ttl74xx_lib)
//NET_MODEL("DM7414 FAMILY(IVL=0.16 IVH=0.4 OVL=0.1 OVH=0.05 ORL=10.0 ORH=1.0e8)")
TRUTHTABLE_START(TTL_7400_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|1|22")
TT_LINE("X,0|1|22")
TT_LINE("1,1|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7400_NAND, 2, 1, "+A,+B,@VCC,@GND")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|1|22")
@ -2968,14 +2952,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7402_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|1|22")
TT_LINE("X,1|0|15")
TT_LINE("1,X|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7402_NOR, 2, 1, "+A,+B,@VCC,@GND")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|1|22")
@ -2984,13 +2960,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7404_GATE, 1, 1, "")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |22")
TT_LINE(" 1 | 0 |15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7404_INVERT, 1, 1, "+A,@VCC,@GND")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |22")
@ -3074,16 +3043,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XXOC")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7420_GATE, 4, 1, "")
TT_HEAD("A,B,C,D|Q ")
TT_LINE("0,X,X,X|1|22")
TT_LINE("X,0,X,X|1|22")
TT_LINE("X,X,0,X|1|22")
TT_LINE("X,X,X,0|1|22")
TT_LINE("1,1,1,1|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7420_NAND, 4, 1, "+A,+B,+C,+D,@VCC,@GND")
TT_HEAD("A,B,C,D|Q ")
TT_LINE("0,X,X,X|1|22")
@ -3094,16 +3053,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7421_GATE, 4, 1, "")
TT_HEAD("A,B,C,D|Q ")
TT_LINE("0,X,X,X|0|22")
TT_LINE("X,0,X,X|0|22")
TT_LINE("X,X,0,X|0|22")
TT_LINE("X,X,X,0|0|22")
TT_LINE("1,1,1,1|1|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7421_AND, 4, 1, "+A,+B,+C,+D,@VCC,@GND")
TT_HEAD("A,B,C,D|Q ")
TT_LINE("0,X,X,X|0|22")
@ -3114,16 +3063,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7425_GATE, 4, 1, "")
TT_HEAD("A,B,C,D|Q ")
TT_LINE("1,X,X,X|0|15")
TT_LINE("X,1,X,X|0|15")
TT_LINE("X,X,1,X|0|15")
TT_LINE("X,X,X,1|0|15")
TT_LINE("0,0,0,0|1|22")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7425_NOR, 4, 1, "+A,+B,+C,+D,@VCC,@GND")
TT_HEAD("A,B,C,D|Q ")
TT_LINE("1,X,X,X|0|15")
@ -3134,15 +3073,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7427_GATE, 3, 1, "")
TT_HEAD("A,B,C|Q ")
TT_LINE("1,X,X|0|15")
TT_LINE("X,1,X|0|15")
TT_LINE("X,X,1|0|15")
TT_LINE("0,0,0|1|22")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7427_NOR, 3, 1, "+A,+B,+C,@VCC,@GND")
TT_HEAD("A,B,C|Q ")
TT_LINE("1,X,X|0|15")
@ -3152,20 +3082,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7430_GATE, 8, 1, "")
TT_HEAD("A,B,C,D,E,F,G,H|Q ")
TT_LINE("0,X,X,X,X,X,X,X|1|22")
TT_LINE("X,0,X,X,X,X,X,X|1|22")
TT_LINE("X,X,0,X,X,X,X,X|1|22")
TT_LINE("X,X,X,0,X,X,X,X|1|22")
TT_LINE("X,X,X,X,0,X,X,X|1|22")
TT_LINE("X,X,X,X,X,0,X,X|1|22")
TT_LINE("X,X,X,X,X,X,0,X|1|22")
TT_LINE("X,X,X,X,X,X,X,0|1|22")
TT_LINE("1,1,1,1,1,1,1,1|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7430_NAND, 8, 1, "+A,+B,+C,+D,+E,+F,+G,+H,@VCC,@GND")
TT_HEAD("A,B,C,D,E,F,G,H|Q ")
TT_LINE("0,X,X,X,X,X,X,X|1|22")
@ -3180,14 +3096,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7432_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("1,X|1|22")
TT_LINE("X,1|1|22")
TT_LINE("0,0|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7432_OR, 2, 1, "+A,+B,@VCC,@GND")
TT_HEAD("A,B|Q ")
TT_LINE("1,X|1|22")
@ -3196,18 +3104,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
/* FIXME: Same as 7400, but drains higher output currents.
* Netlist currently does not model over currents (should it ever?)
*/
TRUTHTABLE_START(TTL_7437_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|1|22")
TT_LINE("X,0|1|22")
TT_LINE("1,1|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7442, 4, 10, "")
TT_HEAD("D,C,B,A|0,1,2,3,4,5,6,7,8,9")
TT_LINE("0,0,0,0|0,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
@ -3224,6 +3120,10 @@ NETLIST_START(ttl74xx_lib)
TT_LINE("1,1,X,X|1,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TRUTHTABLE_END()
/* FIXME: Same as 7400, but drains higher output currents.
* Netlist currently does not model over currents (should it ever?)
*/
TRUTHTABLE_START(TTL_7437_NAND, 2, 1, "+A,+B")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|1|22")
@ -3232,15 +3132,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7486_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|0|15")
TT_LINE("0,1|1|22")
TT_LINE("1,0|1|22")
TT_LINE("1,1|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7486_XOR, 2, 1, "+A,+B,@VCC,@GND")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|0|15")
@ -3315,17 +3206,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_74260_GATE, 5, 1, "")
TT_HEAD("A,B,C,D,E|Q ")
TT_LINE("0,0,0,0,0|1|10")
TT_LINE("X,X,X,X,1|0|12")
TT_LINE("X,X,X,1,X|0|12")
TT_LINE("X,X,1,X,X|0|12")
TT_LINE("X,1,X,X,X|0|12")
TT_LINE("1,X,X,X,X|0|12")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_74260_NOR, 5, 1, "+A,+B,+C,+D,+E,@VCC,@GND")
TT_HEAD("A,B,C,D,E|Q")
TT_LINE("0,0,0,0,0|1|10")

181
src/lib/netlist/macro/nlm_ttl74xx_lib.h
View File

@ -18,41 +18,21 @@
#if !NL_AUTO_DEVICES
#define TTL_7400_GATE(name) \
NET_REGISTER_DEV(TTL_7400_GATE, name)
#define TTL_7400_NAND(name, cA, cB) \
NET_REGISTER_DEV(TTL_7400_NAND, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB)
#define TTL_7400_NAND(...) \
NET_REGISTER_DEVEXT(TTL_7400_NAND, __VA_ARGS__)
#define TTL_7400_DIP(name) \
NET_REGISTER_DEV(TTL_7400_DIP, name)
#define TTL_7402_GATE(name) \
NET_REGISTER_DEV(TTL_7402_GATE, name)
#define TTL_7402_NOR(name, cI1, cI2) \
NET_REGISTER_DEV(TTL_7402_NOR, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2)
#define TTL_7402_NOR(...) \
NET_REGISTER_DEVEXT(TTL_7402_NOR, __VA_ARGS__)
#define TTL_7402_DIP(name) \
NET_REGISTER_DEV(TTL_7402_DIP, name)
#define TTL_7404_GATE(name) \
NET_REGISTER_DEV(TTL_7404_GATE, name)
#define TTL_7404_INVERT(name, cA) \
NET_REGISTER_DEV(TTL_7404_INVERT, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cA)
#define TTL_7404_INVERT(...) \
NET_REGISTER_DEVEXT(TTL_7404_INVERT, __VA_ARGS__)
#define TTL_7404_DIP(name) \
NET_REGISTER_DEV(TTL_7404_DIP, name)
@ -72,48 +52,27 @@
NET_REGISTER_DEV(TTL_7407_DIP, name)
#define TTL_7408_GATE(name) \
NET_REGISTER_DEV(TTL_7408_GATE, name)
#define TTL_7408_AND(name, cA, cB) \
NET_REGISTER_DEV(TTL_7408_AND, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB)
#define TTL_7408_AND(...) \
NET_REGISTER_DEVEXT(TTL_7408_AND, __VA_ARGS__)
#define TTL_7408_DIP(name) \
NET_REGISTER_DEV(TTL_7408_DIP, name)
#define TTL_7410_GATE(name) \
NET_REGISTER_DEV(TTL_7410_GATE, name)
#define TTL_7410_NAND(name, cI1, cI2, cI3) \
NET_REGISTER_DEV(TTL_7410_NAND, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3)
#define TTL_7410_NAND(...) \
NET_REGISTER_DEVEXT(TTL_7410_NAND, __VA_ARGS__)
#define TTL_7410_DIP(name) \
NET_REGISTER_DEV(TTL_7410_DIP, name)
#define TTL_7411_GATE(name) \
NET_REGISTER_DEV(TTL_7411_GATE, name)
#define TTL_7411_AND(name, cI1, cI2, cI3) \
NET_REGISTER_DEV(TTL_7411_AND, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3)
#define TTL_7411_AND(...) \
NET_REGISTER_DEVEXT(TTL_7411_AND, __VA_ARGS__)
#define TTL_7411_DIP(name) \
NET_REGISTER_DEV(TTL_7411_DIP, name)
#define TTL_7414_GATE(name) \
NET_REGISTER_DEV(TTL_7414_GATE, name)
@ -135,111 +94,50 @@
NET_REGISTER_DEV(TTL_7416_DIP, name)
#define TTL_7420_GATE(name) \
NET_REGISTER_DEV(TTL_7420_GATE, name)
#define TTL_7420_NAND(name, cI1, cI2, cI3, cI4) \
NET_REGISTER_DEV(TTL_7420_NAND, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4)
#define TTL_7420_NAND(...) \
NET_REGISTER_DEVEXT(TTL_7420_NAND, __VA_ARGS__)
#define TTL_7420_DIP(name) \
NET_REGISTER_DEV(TTL_7420_DIP, name)
#define TTL_7421_GATE(name) \
NET_REGISTER_DEV(TTL_7421_GATE, name)
#define TTL_7421_AND(name, cI1, cI2, cI3, cI4) \
NET_REGISTER_DEV(TTL_7421_AND, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4)
#define TTL_7421_AND(...) \
NET_REGISTER_DEVEXT(TTL_7421_AND, __VA_ARGS__)
#define TTL_7421_DIP(name) \
NET_REGISTER_DEV(TTL_7421_DIP, name)
#define TTL_7425_GATE(name) \
NET_REGISTER_DEV(TTL_7425_GATE, name)
#define TTL_7425_NOR(name, cI1, cI2, cI3, cI4) \
NET_REGISTER_DEV(TTL_7425_NOR, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4)
#define TTL_7425_NOR(...) \
NET_REGISTER_DEVEXT(TTL_7425_NOR, __VA_ARGS__)
#define TTL_7425_DIP(name) \
NET_REGISTER_DEV(TTL_7425_DIP, name)
#define TTL_7427_GATE(name) \
NET_REGISTER_DEV(TTL_7427_GATE, name)
#define TTL_7427_NOR(name, cI1, cI2, cI3) \
NET_REGISTER_DEV(TTL_7427_NOR, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3)
#define TTL_7427_NOR(...) \
NET_REGISTER_DEVEXT(TTL_7427_NOR, __VA_ARGS__)
#define TTL_7427_DIP(name) \
NET_REGISTER_DEV(TTL_7427_DIP, name)
#define TTL_7430_GATE(name) \
NET_REGISTER_DEV(TTL_7430_GATE, name)
#define TTL_7430_NAND(name, cI1, cI2, cI3, cI4, cI5, cI6, cI7, cI8)\
NET_REGISTER_DEV(TTL_7430_NAND, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4) \
NET_CONNECT(name, E, cI5) \
NET_CONNECT(name, F, cI6) \
NET_CONNECT(name, G, cI7) \
NET_CONNECT(name, H, cI8)
#define TTL_7430_NAND(...) \
NET_REGISTER_DEVEXT(TTL_7430_NAND, __VA_ARGS__)
#define TTL_7430_DIP(name) \
NET_REGISTER_DEV(TTL_7430_DIP, name)
#define TTL_7432_GATE(name) \
NET_REGISTER_DEV(TTL_7432_OR, name)
#define TTL_7432_OR(name, cI1, cI2) \
NET_REGISTER_DEV(TTL_7432_OR, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2)
#define TTL_7432_OR(...) \
NET_REGISTER_DEVEXT(TTL_7432_OR, __VA_ARGS__)
#define TTL_7432_DIP(name) \
NET_REGISTER_DEV(TTL_7432_DIP, name)
#define TTL_7437_GATE(name) \
NET_REGISTER_DEV(TTL_7437_GATE, name)
#define TTL_7437_NAND(name, cA, cB) \
NET_REGISTER_DEV(TTL_7437_NAND, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB)
#define TTL_7437_NAND(...) \
NET_REGISTER_DEVEXT(TTL_7437_NAND, __VA_ARGS__)
#define TTL_7437_DIP(name) \
NET_REGISTER_DEV(TTL_7437_DIP, name)
@ -275,15 +173,8 @@
#define TTL_7485_DIP(name) \
NET_REGISTER_DEV(TTL_7485_DIP, name)
#define TTL_7486_GATE(name) \
NET_REGISTER_DEV(TTL_7486_GATE, name)
#define TTL_7486_XOR(name, cA, cB) \
NET_REGISTER_DEV(TTL_7486_XOR, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB)
#define TTL_7486_XOR(...) \
NET_REGISTER_DEVEXT(TTL_7486_XOR, __VA_ARGS__)
#define TTL_7486_DIP(name) \
NET_REGISTER_DEV(TTL_7486_DIP, name)
@ -357,18 +248,8 @@
#define TTL_74174_DIP(name) \
NET_REGISTER_DEV(TTL_74174_DIP, name)
#define TTL_74260_GATE(name) \
NET_REGISTER_DEV(TTL_74260_GATE, name)
#define TTL_74260_NOR(name, cA, cB, cC, cD, cE) \
NET_REGISTER_DEV(TTL_74260_NOR, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, E, cE)
#define TTL_74260_NOR(...) \
NET_REGISTER_DEVEXT(TTL_74260_NOR, __VA_ARGS__)
#define TTL_74260_DIP(name) \
NET_REGISTER_DEV(TTL_74260_DIP, name)

2
src/mame/audio/nl_mario.cpp
View File

@ -149,7 +149,7 @@ static NETLIST_START(nl_mario_snd7)
NET_C(R65.2, 4K_A.FC, C44.1)
NET_C(C44.2, GND)
CD4020_WI(3H, 4K_B.Y, ttllow, V5, GND)
CD4020(3H, 4K_B.Y, ttllow, V5, GND)
TTL_7404_INVERT(4J_B, 3H.Q12)
RES(R64, RES_K(20))

2
src/mame/audio/nl_starcrus.cpp
View File

@ -151,7 +151,7 @@ NETLIST_START(starcrus)
NET_C(LAUNCH_1, H6.1, H6.2)
NET_C(LAUNCH_2, H6.12, H6.13)
TTL_7404_GATE(F8)
TTL_7404_INVERT(F8)
NET_C(F8.GND, GND)
NET_C(F8.VCC, V5)
NET_C(H6.6, F8.A)