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tispellb.c mrchalgr expects reads to be valid after setting indirect address

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hap 2015-12-23 03:48:57 +01:00
parent ac89a938e1
commit 4b93d14cab
1 changed files with 2 additions and 2 deletions
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4
src/devices/machine/tms6100.cpp
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@ -206,8 +206,7 @@ WRITE_LINE_MEMBER(tms6100_device::romclock_w)
if (m_4bit_read) if (m_4bit_read)
{ {
// high nibble 1st? m_data = word >> (m_address & 4) & 0xf;
m_data = word >> (~m_address & 4) & 0xf;
m_address += 4; m_address += 4;
} }
else else
@ -237,6 +236,7 @@ WRITE_LINE_MEMBER(tms6100_device::romclock_w)
// READ AND BRANCH // READ AND BRANCH
if (m_state & TMS6100_NEXT_READ_IS_DUMMY) if (m_state & TMS6100_NEXT_READ_IS_DUMMY)
{ {
m_state |= TMS6100_READ_PENDING;
m_state &= ~TMS6100_NEXT_READ_IS_DUMMY; // clear - no dummy read according to datasheet m_state &= ~TMS6100_NEXT_READ_IS_DUMMY; // clear - no dummy read according to datasheet
m_address = m_rom[m_address_latch] | (m_rom[m_address_latch+1] << 8); m_address = m_rom[m_address_latch] | (m_rom[m_address_latch+1] << 8);
m_address &= 0x3fff; // 14 bits m_address &= 0x3fff; // 14 bits