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z80sio: more corner cases (nw)
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91bc5e3bc9
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4beede1983
@ -1027,18 +1027,14 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data)
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case WR0_ERROR_RESET:
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// error reset
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LOGCMD("%s %s Ch:%c : Error Reset\n", FUNCNAME, tag(), 'A' + m_index);
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if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR))
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if ((WR1_RX_INT_FIRST == (m_wr1 & WR1_RX_INT_MODE_MASK)) && (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR)))
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{
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// clearing framing and overrun errors advances the FIFO
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m_rr1 &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR);
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advance_rx_fifo();
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}
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else
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{
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if (m_rx_fifo_depth && (WR1_RX_INT_FIRST == (m_wr1 & WR1_RX_INT_MODE_MASK)))
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{
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// shift the FIFO
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m_rx_data_fifo >>= 8;
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m_rx_error_fifo >>= 8;
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// no more characters available in the FIFO?
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if (!--m_rx_fifo_depth)
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m_rr0 &= ~RR0_RX_CHAR_AVAILABLE;
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}
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m_rr1 &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR);
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}
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break;
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@ -1185,19 +1181,9 @@ uint8_t z80sio_channel::data_read()
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{
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uint8_t const data = uint8_t(m_rx_data_fifo & 0x000000ffU);
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if (m_rx_fifo_depth && ((WR1_RX_INT_FIRST != (m_wr1 & WR1_RX_INT_MODE_MASK)) || !(m_rx_error_fifo & 0x000000ffU)))
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{
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// load error status from the FIFO
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m_rr1 = (m_rr1 & ~RR1_CRC_FRAMING_ERROR) | uint8_t(m_rx_error_fifo & 0x000000ffU);
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// shift the FIFO
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m_rx_data_fifo >>= 8;
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m_rx_error_fifo >>= 8;
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// no more characters available in the FIFO?
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if (!--m_rx_fifo_depth)
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m_rr0 &= ~RR0_RX_CHAR_AVAILABLE;
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}
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// framing and overrun errors need to be cleared to advance the FIFO in interrupt-on-first mode
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if ((WR1_RX_INT_FIRST != (m_wr1 & WR1_RX_INT_MODE_MASK)) || !(m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR)))
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advance_rx_fifo();
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LOG("Z80SIO \"%s\" Channel %c : Data Register Read '%02x'\n", owner()->tag(), 'A' + m_index, data);
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@ -1243,6 +1229,32 @@ void z80sio_channel::receive_reset()
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m_rx_bit = 0;
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}
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//-------------------------------------------------
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// advance_rx_fifo - move to next received byte
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//-------------------------------------------------
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void z80sio_channel::advance_rx_fifo()
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{
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if (m_rx_fifo_depth)
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{
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if (--m_rx_fifo_depth)
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{
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// shift the FIFO
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m_rx_data_fifo >>= 8;
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m_rx_error_fifo >>= 8;
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// load error status from the FIFO
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m_rr1 = (m_rr1 & ~RR1_CRC_FRAMING_ERROR) | uint8_t(m_rx_error_fifo & 0x000000ffU);
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}
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else
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{
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// no more characters available in the FIFO
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m_rr0 &= ~RR0_RX_CHAR_AVAILABLE;
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}
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}
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}
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//-------------------------------------------------
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// receive_data - receive data word
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//-------------------------------------------------
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@ -1285,6 +1297,8 @@ void z80sio_channel::receive_data()
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}
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m_rr0 |= RR0_RX_CHAR_AVAILABLE;
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if (!m_rx_fifo_depth)
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m_rr1 |= uint8_t(rx_error);
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// receive interrupt
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switch (m_wr1 & WR1_RX_INT_MODE_MASK)
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@ -161,6 +161,7 @@ public:
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void receive_reset();
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void receive_data();
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void advance_rx_fifo();
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DECLARE_WRITE_LINE_MEMBER( write_rx ) { m_rxd = state; }
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DECLARE_WRITE_LINE_MEMBER( cts_w );
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