Also fixes some missing tilemap displays [David Haywood]

-----Messaggio originale-----
Da: David Haywood [mailto:neohaze@nildram.co.uk]
Inviato: lunedì 9 novembre 2009 20.56
Cc: Angelo Salese
Oggetto: Re: Further improvements

This un-breaks the palette, bad pointers and casts, fake ram areasand writing the same data to multiple places are bad mmmmk ?



David Haywood wrote:
> note, eyes may hurt, but it proves the roz / sprites work.
>
> check in please.
>
This commit is contained in:
Angelo Salese 2009-11-09 20:47:06 +00:00
parent c4ad0d37e3
commit 4c00d7f29f
2 changed files with 25 additions and 17 deletions

View File

@ -708,7 +708,11 @@ static INTERRUPT_GEN(konamigx_vbinterrupt_type4)
// IRQ 1 is the main 60hz vblank interrupt
// the gx_syncen & 0x20 test doesn't work on type 3 or 4 ROM boards, likely because the ROM board
// generates the timing in those cases. With this change, rushing heroes and rng2 boot :)
if (1) // gx_syncen & 0x20)
// maybe this interupt should only be every 30fps, or maybe there are flags to prevent the game running too fast
// the real hardware should output the display for each screen on alternate frames
if(video_screen_get_frame_number(device->machine->primary_screen) & 1)
// if (1) // gx_syncen & 0x20)
{
gx_syncen &= ~0x20;
@ -1207,8 +1211,8 @@ static ADDRESS_MAP_START( gx_type3_map, ADDRESS_SPACE_PROGRAM, 32 )
//AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP
AM_RANGE(0xe40000, 0xe40003) AM_WRITE(konamigx_type3_psac2_bank_w) AM_BASE(&konamigx_type3_psac2_bank)
AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE((UINT32**)&K053936_0_linectrl)
AM_RANGE(0xe80000, 0xe87fff) AM_RAM_WRITE(konamigx_555_palette_w) AM_BASE(&paletteram32) // main monitor palette (twice as large as reality)
AM_RANGE(0xea0000, 0xea3fff) AM_RAM_WRITE(konamigx_555_palette2_w) AM_BASE(&gx_subpaletteram32) // sub monitor palette
AM_RANGE(0xe80000, 0xe83fff) AM_RAM_WRITE(konamigx_555_palette_w) AM_BASE(&paletteram32) // main monitor palette
AM_RANGE(0xea0000, 0xea3fff) AM_RAM_WRITE(konamigx_555_palette2_w) AM_BASE(&gx_subpaletteram32)
AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r)
//AM_RANGE(0xf00000, 0xf07fff) AM_RAM
AM_IMPORT_FROM(gx_base_memmap)
@ -1221,7 +1225,7 @@ static ADDRESS_MAP_START( gx_type4_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP
AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP
AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE((UINT32**)&K053936_1_linectrl) // 29C & 29G (PSAC2 line control)
AM_RANGE(0xe80000, 0xe8ffff) AM_RAM_WRITE(konamigx_palette_w) AM_BASE(&paletteram32) // 11G/13G/15G (main screen palette RAM) (twice as large as reality)
AM_RANGE(0xe80000, 0xe87fff) AM_RAM_WRITE(konamigx_palette_w) AM_BASE(&paletteram32) // 11G/13G/15G (main screen palette RAM)
AM_RANGE(0xea0000, 0xea7fff) AM_RAM_WRITE(konamigx_palette2_w) AM_BASE(&gx_subpaletteram32) // 5G/7G/9G (sub screen palette RAM)
AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r) // type 4 polls this too
AM_RANGE(0xf00000, 0xf07fff) AM_RAM_WRITE(konamigx_t4_psacmap_w) AM_BASE(&gx_psacram) // PSAC2 tilemap

View File

@ -332,7 +332,7 @@ VIDEO_START(konamigx_type3)
int width = video_screen_get_width(machine->primary_screen);
int height = video_screen_get_height(machine->primary_screen);
K056832_vh_start(machine, "gfx1", K056832_BPP_6, 1, NULL, konamigx_type2_tile_callback, 0);
K056832_vh_start(machine, "gfx1", K056832_BPP_6, 0, NULL, konamigx_type2_tile_callback, 1);
K055673_vh_start(machine, "gfx2", K055673_LAYOUT_GX6, -132, -24, konamigx_type2_sprite_callback);
_gxcommoninitnosprites(machine);
@ -638,30 +638,34 @@ WRITE32_HANDLER( konamigx_palette2_w )
palette_set_color(space->machine,offset,MAKE_RGB(r,g,b));
}
INLINE void set_color_555(running_machine *machine, pen_t color, int rshift, int gshift, int bshift, UINT16 data)
{
palette_set_color_rgb(machine, color, pal5bit(data >> rshift), pal5bit(data >> gshift), pal5bit(data >> bshift));
}
// main monitor for type 3
WRITE32_HANDLER( konamigx_555_palette_w )
{
UINT32 coldat;
COMBINE_DATA(&paletteram32[offset]);
paletteram16 = (UINT16 *)paletteram32;
if ((ACCESSING_BITS_16_23) && (ACCESSING_BITS_24_31))
paletteram16_xBBBBBGGGGGRRRRR_word_w(space, offset*2, data >> 16, mem_mask >> 16);
if ((ACCESSING_BITS_0_7) && (ACCESSING_BITS_8_15))
paletteram16_xBBBBBGGGGGRRRRR_word_w(space, offset*2+1, data, mem_mask);
coldat = paletteram32[offset];
set_color_555(space->machine, offset*2, 0, 5, 10,coldat >> 16);
set_color_555(space->machine, offset*2+1, 0, 5, 10,coldat & 0xffff);
}
// sub monitor for type 3
WRITE32_HANDLER( konamigx_555_palette2_w )
{
UINT32 coldat;
COMBINE_DATA(&gx_subpaletteram32[offset]);
offset += (0x4000/4);
COMBINE_DATA(&paletteram32[offset]);
paletteram16 = (UINT16 *)paletteram32;
coldat = gx_subpaletteram32[offset];
if ((ACCESSING_BITS_16_23) && (ACCESSING_BITS_24_31))
paletteram16_xBBBBBGGGGGRRRRR_word_w(space, offset*2, data >> 16, mem_mask >> 16);
if ((ACCESSING_BITS_0_7) && (ACCESSING_BITS_8_15))
paletteram16_xBBBBBGGGGGRRRRR_word_w(space, offset*2+1, data, mem_mask);
offset += (0x4000/4);
set_color_555(space->machine, offset*2, 0, 5, 10,coldat >> 16);
set_color_555(space->machine, offset*2+1, 0, 5, 10,coldat & 0xffff);
}
WRITE32_HANDLER( konamigx_tilebank_w )