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680x0: Improve disassembly for various FMOVE forms [R. Belmont]

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This commit is contained in:
R. Belmont 2010-03-11 05:23:24 +00:00
parent dfff696a55
commit 4c0a6f40e7
1 changed files with 78 additions and 7 deletions
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85
src/emu/cpu/m68000/m68kdasm.c
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@ -1697,6 +1697,10 @@ static void d68040_fpu(void)
{
".l", ".s", ".x", ".p", ".w", ".d", ".b", ".?"
};
const char *spec_reg[8] =
{
"?", "FPIAR", "FPSR", "?", "FPCR", "?", "?", "?"
};
char mnemonic[40];
UINT32 w2, src, dst_reg;
@ -1783,21 +1787,88 @@ static void d68040_fpu(void)
case 0x3:
{
sprintf(g_dasm_str, "fmove /todo");
sprintf(g_dasm_str, "fmove FP%d, %s", dst_reg, get_ea_mode_str_32(g_cpu_ir));
break;
}
case 0x4:
case 0x5:
case 0x4: // ea to control
{
sprintf(g_dasm_str, "fmove /todo");
sprintf(g_dasm_str, "fmove.l %s, %s", get_ea_mode_str_32(g_cpu_ir), spec_reg[(w2>>10)&7]);
break;
}
case 0x6:
case 0x7:
case 0x5: // control to ea
{
sprintf(g_dasm_str, "fmovem /todo");
sprintf(g_dasm_str, "fmove.l %s, %s", spec_reg[(w2>>10)&7], get_ea_mode_str_32(g_cpu_ir));
break;
}
case 0x6: // memory to FPU, list
{
char temp[32];
if ((w2>>11) & 1) // dynamic register list
{
sprintf(g_dasm_str, "fmovem.x %s, D%d", get_ea_mode_str_32(g_cpu_ir), (w2>>4)&7);
}
else // static register list
{
int i;
sprintf(g_dasm_str, "fmovem.x %s, ", get_ea_mode_str_32(g_cpu_ir));
for (i = 0; i < 8; i++)
{
if (w2 & (1<<i))
{
if ((w2>>12) & 1) // postincrement or control
{
sprintf(temp, "FP%d ", 7-i);
}
else // predecrement
{
sprintf(temp, "FP%d ", i);
}
strcat(g_dasm_str, temp);
}
}
}
break;
}
case 0x7: // FPU to memory, list
{
char temp[32];
if ((w2>>11) & 1) // dynamic register list
{
sprintf(g_dasm_str, "fmovem.x D%d, %s", (w2>>4)&7, get_ea_mode_str_32(g_cpu_ir));
}
else // static register list
{
int i;
sprintf(g_dasm_str, "fmovem.x ");
for (i = 0; i < 8; i++)
{
if (w2 & (1<<i))
{
if ((w2>>12) & 1) // postincrement or control
{
sprintf(temp, "FP%d ", 7-i);
}
else // predecrement
{
sprintf(temp, "FP%d ", i);
}
strcat(g_dasm_str, temp);
}
}
strcat(g_dasm_str, ", ");
strcat(g_dasm_str, get_ea_mode_str_32(g_cpu_ir));
}
break;
}