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n68681: Only clear input state on start, not reset. (nw)

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R. Belmont 2014-03-10 12:29:48 +00:00
parent 8042e28af9
commit 4cb81aa897
1 changed files with 2 additions and 1 deletions
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src/emu/machine/n68681.c
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@ -106,6 +106,8 @@ void duartn68681_device::device_start()
duart_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(duartn68681_device::duart_timer_callback),this), NULL); duart_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(duartn68681_device::duart_timer_callback),this), NULL);
IP_last_state = 0;
save_item(NAME(ACR)); save_item(NAME(ACR));
save_item(NAME(IMR)); save_item(NAME(IMR));
save_item(NAME(ISR)); save_item(NAME(ISR));
@ -129,7 +131,6 @@ void duartn68681_device::device_reset()
OPCR = 0; /* Output Port Conf. Register */ OPCR = 0; /* Output Port Conf. Register */
OPR = 0; /* Output Port Register */ OPR = 0; /* Output Port Register */
CTR.d = 0; /* Counter/Timer Preset Value */ CTR.d = 0; /* Counter/Timer Preset Value */
IP_last_state = 0; /* last state of IP bits */
m_read_vector = false; m_read_vector = false;
// "reset clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR) puts OP0-7 in the high state, stops the counter/timer, and puts channels a/b in the inactive state" // "reset clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR) puts OP0-7 in the high state, stops the counter/timer, and puts channels a/b in the inactive state"