From 4cef27ecc96d604bee68b9ab4f0dfa4e150e42e2 Mon Sep 17 00:00:00 2001 From: Ryan Holtz Date: Mon, 16 Nov 2009 00:04:37 +0000 Subject: [PATCH] - Fixed Context usage and TLB exception vectors in the MIPS core [Harmony] --- src/emu/cpu/mips/mips3drc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c index 9544e42952d..36032d1f2ef 100644 --- a/src/emu/cpu/mips/mips3drc.c +++ b/src/emu/cpu/mips/mips3drc.c @@ -1157,9 +1157,10 @@ static void static_generate_exception(mips3_state *mips3, UINT8 exception, int r if (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE) { + offset = 0x000; /* set the upper bits of EntryHi and the lower bits of Context to the fault page */ UML_ROLINS(block, CPR032(COP0_EntryHi), IREG(0), IMM(0), IMM(0xffffe000)); // rolins [EntryHi],i0,0,0xffffe000 - UML_ROLINS(block, CPR032(COP0_Context), IREG(0), IMM(32-9), IMM(0x7fffff)); // rolins [Context],i0,32-9,0x7fffff + UML_ROLINS(block, CPR032(COP0_Context), IREG(0), IMM(32-9), IMM(0x7ffff0)); // rolins [Context],i0,32-9,0x7fffff } /* set the EPC and Cause registers */