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Merge pull request #379 from JoakimLarsson/z80scc_m166_3

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Z80scc m166 3
This commit is contained in:
R. Belmont 2015-10-13 16:33:22 -04:00
commit 4d9ab25ec8
4 changed files with 1780 additions and 1583 deletions
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1705
src/devices/machine/z80scc.c
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633
src/devices/machine/z80scc.h
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@ -2,31 +2,31 @@
// copyright-holders:Joakim Larsson Edstrom
/***************************************************************************
Z80-SCC Serial Communications Controller emulation
Z80-SCC Serial Communications Controller emulation
****************************************************************************
_____ _____ _____ _____
AD1 1|* \_/ |40 AD0 D1 1|* \_/ |40 D0
AD3 2| |39 AD2 D3 2| |39 D2
AD5 3| |38 AD4 D5 3| |38 D4
AD7 4| |37 AD6 D7 4| |37 D6
_INT 5| |36 _DS _INT 5| |36 _RD
IEO 6| |35 _AS IEO 6| |35 _WR
IEI 7| |34 R/_W IEI 7| |34 B/_A
_INTACK 8| |33 _CS0 _INTACK 8| |33 _CE
VCC 9| |32 CS1 VCC 9| |32 C/_D
_W//REQA 10| |31 GND _W//REQA 10| |31 GND
_SYNCA 11| Z8030 |30 _W/_REQ _SYNCA 11| Z8530 |30 _W/_REQB
_RTxCA 12| Z80C30 |29 _SYNCB _RTxCA 12| Z85C30 |29 _SYNCB
RxDA 13| Z80230 |28 _RTxCB RxDA 13| Z85230 |28 _RTxCB
_TRxCA 14| |27 RxDB _TRxCA 14| |27 RxDB
TxDA 15| |26 _TRxCB TxDA 15| |26 _TRxCB
_DTR//REQA 16| |25 TxDB _DTR//REQA 16| |25 TxDB
_RTSA 17| |24 _DTR/_REQB _RTSA 17| |24 _DTR/_REQB
_CTSA 18| |23 _RTSB _CTSA 18| |23 _RTSB
_DCDA 19| |22 _CTSB _DCDA 19| |22 _CTSB
PCLK 20|_____________|21 _DCDB PCLK 20|_____________|21 _DCDB
ZBUS Universal Bus
_____ _____ _____ _____
AD1 1|* \_/ |40 AD0 D1 1|* \_/ |40 D0
AD3 2| |39 AD2 D3 2| |39 D2
AD5 3| |38 AD4 D5 3| |38 D4
AD7 4| |37 AD6 D7 4| |37 D6
_INT 5| |36 _DS _INT 5| |36 _RD
IEO 6| |35 _AS IEO 6| |35 _WR
IEI 7| |34 R/_W IEI 7| |34 B/_A
_INTACK 8| |33 _CS0 _INTACK 8| |33 _CE
VCC 9| |32 CS1 VCC 9| |32 C/_D
_W//REQA 10| |31 GND _W//REQA 10| |31 GND
_SYNCA 11| Z8030 |30 _W/_REQ _SYNCA 11| Z8530 |30 _W/_REQB
_RTxCA 12| Z80C30 |29 _SYNCB _RTxCA 12| Z85C30 |29 _SYNCB
RxDA 13| Z80230 |28 _RTxCB RxDA 13| Z85230 |28 _RTxCB
_TRxCA 14| |27 RxDB _TRxCA 14| |27 RxDB
TxDA 15| |26 _TRxCB TxDA 15| |26 _TRxCB
_DTR//REQA 16| |25 TxDB _DTR//REQA 16| |25 TxDB
_RTSA 17| |24 _DTR/_REQB _RTSA 17| |24 _DTR/_REQB
_CTSA 18| |23 _RTSB _CTSA 18| |23 _RTSB
_DCDA 19| |22 _CTSB _DCDA 19| |22 _CTSB
PCLK 20|_____________|21 _DCDB PCLK 20|_____________|21 _DCDB
ZBUS Universal Bus
***************************************************************************/
@ -38,7 +38,7 @@
#include "cpu/z80/z80daisy.h"
//**************************************************************************
// DEVICE CONFIGURATION MACROS
// DEVICE CONFIGURATION MACROS
//**************************************************************************
#define MCFG_Z80SCC_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
@ -101,14 +101,16 @@
//**************************************************************************
// TYPE DEFINITIONS
// TYPE DEFINITIONS
//**************************************************************************
// ======================> z80scc_channel
class z80scc_device;
class z80scc_channel : public z80sio_channel
//class z80scc_channel : public z80sio_channel
class z80scc_channel : public device_t,
public device_serial_interface
{
friend class z80scc_device;
@ -126,41 +128,42 @@ public:
virtual void rcv_callback();
virtual void rcv_complete();
// read register handlers
UINT8 do_sccreg_rr0();
UINT8 do_sccreg_rr1();
UINT8 do_sccreg_rr2();
UINT8 do_sccreg_rr3();
UINT8 do_sccreg_rr4();
UINT8 do_sccreg_rr5();
UINT8 do_sccreg_rr6();
UINT8 do_sccreg_rr7();
UINT8 do_sccreg_rr8();
UINT8 do_sccreg_rr9();
UINT8 do_sccreg_rr10();
UINT8 do_sccreg_rr11();
UINT8 do_sccreg_rr12();
UINT8 do_sccreg_rr13();
UINT8 do_sccreg_rr14();
UINT8 do_sccreg_rr15();
// read register handlers
UINT8 do_sccreg_rr0();
UINT8 do_sccreg_rr1();
UINT8 do_sccreg_rr2();
UINT8 do_sccreg_rr3();
UINT8 do_sccreg_rr4();
UINT8 do_sccreg_rr5();
UINT8 do_sccreg_rr6();
UINT8 do_sccreg_rr7();
UINT8 do_sccreg_rr8();
UINT8 do_sccreg_rr9();
UINT8 do_sccreg_rr10();
UINT8 do_sccreg_rr11();
UINT8 do_sccreg_rr12();
UINT8 do_sccreg_rr13();
UINT8 do_sccreg_rr14();
UINT8 do_sccreg_rr15();
// write register handlers
void do_sccreg_wr0(UINT8 data);
void do_sccreg_wr1(UINT8 data);
void do_sccreg_wr2(UINT8 data);
void do_sccreg_wr3(UINT8 data);
void do_sccreg_wr4(UINT8 data);
void do_sccreg_wr5(UINT8 data);
void do_sccreg_wr6(UINT8 data);
void do_sccreg_wr7(UINT8 data);
void do_sccreg_wr8(UINT8 data);
void do_sccreg_wr9(UINT8 data);
void do_sccreg_wr10(UINT8 data);
void do_sccreg_wr11(UINT8 data);
void do_sccreg_wr12(UINT8 data);
void do_sccreg_wr13(UINT8 data);
void do_sccreg_wr14(UINT8 data);
void do_sccreg_wr15(UINT8 data);
// write register handlers
void do_sccreg_wr0(UINT8 data);
void do_sccreg_wr0_resets(UINT8 data);
void do_sccreg_wr1(UINT8 data);
void do_sccreg_wr2(UINT8 data);
void do_sccreg_wr3(UINT8 data);
void do_sccreg_wr4(UINT8 data);
void do_sccreg_wr5(UINT8 data);
void do_sccreg_wr6(UINT8 data);
void do_sccreg_wr7(UINT8 data);
void do_sccreg_wr8(UINT8 data);
void do_sccreg_wr9(UINT8 data);
void do_sccreg_wr10(UINT8 data);
void do_sccreg_wr11(UINT8 data);
void do_sccreg_wr12(UINT8 data);
void do_sccreg_wr13(UINT8 data);
void do_sccreg_wr14(UINT8 data);
void do_sccreg_wr15(UINT8 data);
UINT8 control_read();
void control_write(UINT8 data);
@ -170,7 +173,7 @@ public:
void receive_data(UINT8 data);
void m_rx_fifo_rp_step();
UINT8 m_rx_fifo_rp_data();
UINT8 m_rx_fifo_rp_data();
DECLARE_WRITE_LINE_MEMBER( write_rx );
DECLARE_WRITE_LINE_MEMBER( cts_w );
@ -184,19 +187,17 @@ public:
int m_txc;
// Register state
// read registers enum
#if 0 //defined by z80sio.h
// read registers enum
UINT8 m_rr0; // REG_RR0_STATUS
UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND
UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT
#endif
UINT8 m_rr3; // REG_RR3_INTERUPPT_PEND
UINT8 m_rr4; // REG_RR4_WR4_OR_RR0
UINT8 m_rr5; // REG_RR5_WR5_OR_RR0
UINT8 m_rr6; // REG_RR6_LSB_OR_RR2
UINT8 m_rr7; // REG_RR7_MSB_OR_RR3
UINT8 m_rr8; // REG_RR8_RECEIVE_DATA
UINT8 m_rr9; // REG_RR9_WR3_OR_RR13
UINT8 m_rr9; // REG_RR9_WR3_OR_RR13
UINT8 m_rr10; // REG_RR10_MISC_STATUS
UINT8 m_rr11; // REG_RR11_WR10_OR_RR15
UINT8 m_rr12; // REG_RR12_LO_TIME_CONST
@ -204,8 +205,7 @@ public:
UINT8 m_rr14; // REG_RR14_WR7_OR_R10
UINT8 m_rr15; // REG_RR15_WR15_EXT_STAT
// write registers enum
#if 0 //defined by z80sio.h
// write registers enum
UINT8 m_wr0; // REG_WR0_COMMAND_REGPT
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
UINT8 m_wr2; // REG_WR2_INT_VECTOR
@ -214,7 +214,6 @@ public:
UINT8 m_wr5; // REG_WR5_TX_CONTROL
UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
#endif
UINT8 m_wr8; // REG_WR8_TRANSMIT_DATA
UINT8 m_wr9; // REG_WR9_MASTER_INT_CTRL
UINT8 m_wr10; // REG_WR10_MSC_RX_TX_CTRL
@ -230,288 +229,288 @@ protected:
{
INT_TRANSMIT = 0,
INT_EXTERNAL = 1,
INT_RECEIVE = 2,
INT_SPECIAL = 3
INT_RECEIVE = 2,
INT_SPECIAL = 3
};
// Read registers
enum
{
REG_RR0_STATUS = 0, // SIO
REG_RR1_SPEC_RCV_COND = 1, // SIO
REG_RR2_INTERRUPT_VECT = 2, // SIO
REG_RR3_INTERUPPT_PEND = 3,
REG_RR4_WR4_OR_RR0 = 4,
REG_RR5_WR5_OR_RR0 = 5,
REG_RR6_LSB_OR_RR2 = 6,
REG_RR7_MSB_OR_RR3 = 7,
REG_RR8_RECEIVE_DATA = 8,
REG_RR9_WR3_OR_RR13 = 9,
REG_RR10_MISC_STATUS = 10,
REG_RR11_WR10_OR_RR15 = 11,
REG_RR12_LO_TIME_CONST = 12,
REG_RR13_HI_TIME_CONST = 13,
REG_RR14_WR7_OR_R10 = 14,
REG_RR15_WR15_EXT_STAT = 15
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0, // SIO
REG_WR1_INT_DMA_ENABLE = 1, // SIO
REG_WR2_INT_VECTOR = 2, // SIO
REG_WR3_RX_CONTROL = 3, // SIO
REG_WR4_RX_TX_MODES = 4, // SIO
REG_WR5_TX_CONTROL = 5, // SIO
REG_WR6_SYNC_OR_SDLC_A = 6, // SIO
REG_WR7_SYNC_OR_SDLC_F = 7, // SIO
REG_WR8_TRANSMIT_DATA = 8,
REG_WR9_MASTER_INT_CTRL = 9,
REG_WR10_MSC_RX_TX_CTRL = 10,
REG_WR11_CLOCK_MODES = 11,
REG_WR12_LO_BAUD_GEN = 12,
REG_WR13_HI_BAUD_GEN = 13,
REG_WR14_MISC_CTRL = 14,
REG_WR15_EXT_ST_INT_CTRL= 15
};
// Read registers
enum
{
RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit
RR0_ZC = 0x02, // SCC bit
RR0_TX_BUFFER_EMPTY = 0x04, // SIO
RR0_DCD = 0x08, // SIO
RR0_RI = 0x10, // DART bit? TODO: investigate function and remove
RR0_SYNC_HUNT = 0x10, // SIO bit, not supported
RR0_CTS = 0x20, // SIO bit
RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported
RR0_BREAK_ABORT = 0x80 // SIO bit, not supported
REG_RR0_STATUS = 0, // SIO
REG_RR1_SPEC_RCV_COND = 1, // SIO
REG_RR2_INTERRUPT_VECT = 2, // SIO
REG_RR3_INTERUPPT_PEND = 3,
REG_RR4_WR4_OR_RR0 = 4,
REG_RR5_WR5_OR_RR0 = 5,
REG_RR6_LSB_OR_RR2 = 6,
REG_RR7_MSB_OR_RR3 = 7,
REG_RR8_RECEIVE_DATA = 8,
REG_RR9_WR3_OR_RR13 = 9,
REG_RR10_MISC_STATUS = 10,
REG_RR11_WR10_OR_RR15 = 11,
REG_RR12_LO_TIME_CONST = 12,
REG_RR13_HI_TIME_CONST = 13,
REG_RR14_WR7_OR_R10 = 14,
REG_RR15_WR15_EXT_STAT = 15
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0, // SIO
REG_WR1_INT_DMA_ENABLE = 1, // SIO
REG_WR2_INT_VECTOR = 2, // SIO
REG_WR3_RX_CONTROL = 3, // SIO
REG_WR4_RX_TX_MODES = 4, // SIO
REG_WR5_TX_CONTROL = 5, // SIO
REG_WR6_SYNC_OR_SDLC_A = 6, // SIO
REG_WR7_SYNC_OR_SDLC_F = 7, // SIO
REG_WR8_TRANSMIT_DATA = 8,
REG_WR9_MASTER_INT_CTRL = 9,
REG_WR10_MSC_RX_TX_CTRL = 10,
REG_WR11_CLOCK_MODES = 11,
REG_WR12_LO_BAUD_GEN = 12,
REG_WR13_HI_BAUD_GEN = 13,
REG_WR14_MISC_CTRL = 14,
REG_WR15_EXT_ST_INT_CTRL= 15
};
enum
{
RR1_ALL_SENT = 0x01, // SIO/SCC bit
RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported
RR1_PARITY_ERROR = 0x10, // SIO/SCC bits
RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits
RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits
RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported
RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit
RR0_ZC = 0x02, // SCC bit
RR0_TX_BUFFER_EMPTY = 0x04, // SIO
RR0_DCD = 0x08, // SIO
RR0_RI = 0x10, // DART bit? TODO: investigate function and remove
RR0_SYNC_HUNT = 0x10, // SIO bit, not supported
RR0_CTS = 0x20, // SIO bit
RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported
RR0_BREAK_ABORT = 0x80 // SIO bit, not supported
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{
RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
RR3_CHANB_RX_IP = 0x04, // channel B return all zero
RR3_CHANA_EXT_IP = 0x08,
RR3_CHANA_TX_IP = 0x10,
RR3_CHANA_RX_IP = 0x20
};
enum
{
RR1_ALL_SENT = 0x01, // SIO/SCC bit
RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported
RR1_PARITY_ERROR = 0x10, // SIO/SCC bits
RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits
RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits
RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{
RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
RR3_CHANB_RX_IP = 0x04, // channel B return all zero
RR3_CHANA_EXT_IP = 0x08,
RR3_CHANA_TX_IP = 0x10,
RR3_CHANA_RX_IP = 0x20
};
enum // Universal Bus WR0 commands for 85X30
{
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38, // COMMANDS
WR0_NULL = 0x00, // 0 0 0
WR0_POINT_HIGH = 0x08, // 0 0 1
WR0_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_SEND_ABORT = 0x18, // 0 1 1
WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
WR0_RESET_TX_INT = 0x28, // 1 0 1
WR0_ERROR_RESET = 0x30, // 1 1 0
WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1
WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET
WR0_CRC_RESET_NULL = 0x00, // 0 0
WR0_CRC_RESET_RX = 0x40, // 0 1
WR0_CRC_RESET_TX = 0x80, // 1 0
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38, // COMMANDS
WR0_NULL = 0x00, // 0 0 0
WR0_POINT_HIGH = 0x08, // 0 0 1
WR0_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_SEND_ABORT = 0x18, // 0 1 1
WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
WR0_RESET_TX_INT = 0x28, // 1 0 1
WR0_ERROR_RESET = 0x30, // 1 1 0
WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1
WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET
WR0_CRC_RESET_NULL = 0x00, // 0 0
WR0_CRC_RESET_RX = 0x40, // 0 1
WR0_CRC_RESET_TX = 0x80, // 1 0
WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // 1 1
};
enum // ZBUS WR0 commands or 80X30
{
WR0_Z_COMMAND_MASK = 0x38, // COMMANDS
WR0_Z_NULL_1 = 0x00, // 0 0 0
WR0_Z_NULL_2 = 0x08, // 0 0 1
WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_Z_SEND_ABORT = 0x18, // 0 1 1
WR0_Z_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
WR0_Z_RESET_TX_INT = 0x28, // 1 0 1
WR0_Z_ERROR_RESET = 0x30, // 1 1 0
WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1
WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B
WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0
WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
};
enum
{
WR1_EXT_INT_ENABLE = 0x01,
WR1_TX_INT_ENABLE = 0x02,
WR1_PARITY_IS_SPEC_COND = 0x04,
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
WR0_Z_COMMAND_MASK = 0x38, // COMMANDS
WR0_Z_NULL_1 = 0x00, // 0 0 0
WR0_Z_NULL_2 = 0x08, // 0 0 1
WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_Z_SEND_ABORT = 0x18, // 0 1 1
WR0_Z_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
WR0_Z_RESET_TX_INT = 0x28, // 1 0 1
WR0_Z_ERROR_RESET = 0x30, // 1 1 0
WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1
WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B
WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0
WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
};
enum
{
WR3_RX_ENABLE = 0x01,
WR1_EXT_INT_ENABLE = 0x01,
WR1_TX_INT_ENABLE = 0x02,
WR1_PARITY_IS_SPEC_COND = 0x04,
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
};
enum
{
WR3_RX_ENABLE = 0x01,
WR3_SYNC_CHAR_LOAD_INHIBIT= 0x02, // not supported
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
WR3_RX_WORD_LENGTH_6 = 0x80,
WR3_RX_WORD_LENGTH_8 = 0xc0
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
WR3_RX_WORD_LENGTH_6 = 0x80,
WR3_RX_WORD_LENGTH_8 = 0xc0
};
enum
{
WR4_PARITY_ENABLE = 0x01,
WR4_PARITY_EVEN = 0x02,
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
WR4_CLOCK_RATE_X32 = 0x80,
WR4_CLOCK_RATE_X64 = 0xc0
WR4_PARITY_ENABLE = 0x01,
WR4_PARITY_EVEN = 0x02,
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
WR4_CLOCK_RATE_X32 = 0x80,
WR4_CLOCK_RATE_X64 = 0xc0
};
enum
{
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
WR5_TX_WORD_LENGTH_7 = 0x20,
WR5_TX_WORD_LENGTH_8 = 0x60,
WR5_DTR = 0x80
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
WR5_TX_WORD_LENGTH_7 = 0x20,
WR5_TX_WORD_LENGTH_8 = 0x60,
WR5_DTR = 0x80
};
/* SCC specifics */
enum
{
WR9_CMD_MASK = 0xC0,
WR9_CMD_NORESET = 0x00,
WR9_CMD_CHNB_RESET = 0x40,
WR9_CMD_CHNA_RESET = 0x80,
WR9_CMD_HW_RESET = 0xC0,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_SHSL = 0x10,
WR9_BIT_IACK = 0x20
};
/* SCC specifics */
enum
{
WR9_CMD_MASK = 0xC0,
WR9_CMD_NORESET = 0x00,
WR9_CMD_CHNB_RESET = 0x40,
WR9_CMD_CHNA_RESET = 0x80,
WR9_CMD_HW_RESET = 0xC0,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_SHSL = 0x10,
WR9_BIT_IACK = 0x20
};
enum
{
WR11_RCVCLK_TYPE = 0x80,
WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0
WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1
WR11_RCVCLK_SRC_BR = 0x40, // 1 0
WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1
WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK
WR11_TRACLK_SRC_RTXC = 0x00, // 0 0
WR11_TRACLK_SRC_TRXC = 0x08, // 0 1
WR11_TRACLK_SRC_BR = 0x10, // 1 0
WR11_TRACLK_SRC_DPLL = 0x18, // 1 1
WR11_TRXC_DIRECTION = 0x04,
WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK
WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0
WR11_TRXSRC_SRC_TRA = 0x01, // 0 1
WR11_TRXSRC_SRC_BR = 0x02, // 1 0
WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1
};
enum
{
WR11_RCVCLK_TYPE = 0x80,
WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0
WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1
WR11_RCVCLK_SRC_BR = 0x40, // 1 0
WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1
WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK
WR11_TRACLK_SRC_RTXC = 0x00, // 0 0
WR11_TRACLK_SRC_TRXC = 0x08, // 0 1
WR11_TRACLK_SRC_BR = 0x10, // 1 0
WR11_TRACLK_SRC_DPLL = 0x18, // 1 1
WR11_TRXC_DIRECTION = 0x04,
WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK
WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0
WR11_TRXSRC_SRC_TRA = 0x01, // 0 1
WR11_TRXSRC_SRC_BR = 0x02, // 1 0
WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1
};
enum
{
WR14_DPLL_CMD_MASK = 0xe0, // Command
WR14_CMD_NULL = 0x00, // 0 0 0
WR14_CMD_ESM = 0x20, // 0 0 1
WR14_CMD_RMC = 0x40, // 0 1 0
WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1
WR14_CMD_SS_BGR = 0x80, // 1 0 0
WR14_CMD_SS_RTXC = 0xa0, // 1 0 1
WR14_CMD_SET_FM = 0xc0, // 1 1 0
WR14_CMD_SET_NRZI = 0xe0 // 1 1 1
};
enum
{
WR14_DPLL_CMD_MASK = 0xe0, // Command
WR14_CMD_NULL = 0x00, // 0 0 0
WR14_CMD_ESM = 0x20, // 0 0 1
WR14_CMD_RMC = 0x40, // 0 1 0
WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1
WR14_CMD_SS_BGR = 0x80, // 1 0 0
WR14_CMD_SS_RTXC = 0xa0, // 1 0 1
WR14_CMD_SET_FM = 0xc0, // 1 1 0
WR14_CMD_SET_NRZI = 0xe0 // 1 1 1
};
void update_serial();
void set_dtr(int state);
void set_rts(int state);
int get_clock_mode();
void update_rts();
void update_rts();
stop_bits_t get_stop_bits();
int get_rx_word_length();
int get_tx_word_length();
// receiver state
UINT8 m_rx_data_fifo[8]; // receive data FIFO
UINT8 m_rx_error_fifo[8]; // receive error FIFO
UINT8 m_rx_error; // current receive error
//int m_rx_fifo // receive FIFO pointer
int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_wp; // receive FIFO write pointer
int m_rx_fifo_sz; // receive FIFO size
UINT8 m_rx_data_fifo[8]; // receive data FIFO
UINT8 m_rx_error_fifo[8]; // receive error FIFO
UINT8 m_rx_error; // current receive error
//int m_rx_fifo // receive FIFO pointer
int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_wp; // receive FIFO write pointer
int m_rx_fifo_sz; // receive FIFO size
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd;
int m_ri; // ring indicator latch
int m_cts; // clear to send latch
int m_dcd; // data carrier detect latch
int m_ri; // ring indicator latch
int m_cts; // clear to send latch
int m_dcd; // data carrier detect latch
// transmitter state
UINT8 m_tx_data; // transmit data register
int m_tx_clock; // transmit clock pulse count
UINT8 m_tx_data; // transmit data register
int m_tx_clock; // transmit clock pulse count
int m_dtr; // data terminal ready
int m_rts; // request to send
int m_dtr; // data terminal ready
int m_rts; // request to send
// synchronous state
UINT16 m_sync; // sync character
UINT16 m_sync; // sync character
// int m_index;
int m_index;
z80scc_device *m_uart;
// SCC specifics
int m_ph; // Point high command to access regs 08-0f
UINT8 m_zc;
int m_ph; // Point high command to access regs 08-0f
UINT8 m_zc;
};
@ -557,10 +556,11 @@ public:
DECLARE_READ8_MEMBER( ba_cd_r );
DECLARE_WRITE8_MEMBER( ba_cd_w );
DECLARE_READ8_MEMBER( da_r ) { return m_chanA->data_read(); }
DECLARE_WRITE8_MEMBER( da_w ) { m_chanA->data_write(data); }
DECLARE_READ8_MEMBER( db_r ) { return m_chanB->data_read(); }
DECLARE_WRITE8_MEMBER( db_w ) { m_chanB->data_write(data); }
/* Definitions moved to z80scc.c for enhencements */
DECLARE_READ8_MEMBER( da_r ); // { return m_chanA->data_read(); }
DECLARE_WRITE8_MEMBER( da_w ); // { m_chanA->data_write(data); }
DECLARE_READ8_MEMBER( db_r ); // { return m_chanB->data_read(); }
DECLARE_WRITE8_MEMBER( db_w ); // { m_chanB->data_write(data); }
DECLARE_READ8_MEMBER( ca_r ) { return m_chanA->control_read(); }
DECLARE_WRITE8_MEMBER( ca_w ) { m_chanA->control_write(data); }
@ -607,7 +607,7 @@ protected:
// Variants in the SCC family
enum
{
TYPE_Z80SCC = 0x001,
TYPE_Z80SCC = 0x001,
TYPE_SCC8030 = 0x002,
TYPE_SCC80C30 = 0x004,
TYPE_SCC80230 = 0x008,
@ -615,16 +615,16 @@ protected:
TYPE_SCC85C30 = 0x020,
TYPE_SCC85230 = 0x040,
TYPE_SCC85233 = 0x080,
TYPE_SCC8523L = 0x100
TYPE_SCC8523L = 0x100
};
#define SET_NMOS ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC8530 )
#define SET_CMOS ( z80scc_device::TYPE_SCC80C30 | z80scc_device::TYPE_SCC85C30 )
#define SET_ESCC ( z80scc_device::TYPE_SCC80230 | z80scc_device::TYPE_SCC85230 | z80scc_device::TYPE_SCC8523L )
#define SET_EMSCC z80scc_device::TYPE_SCC85233
#define SET_EMSCC z80scc_device::TYPE_SCC85233
#define SET_Z80X30 ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC80C30 | z80scc_device::TYPE_SCC80230 )
#define SET_Z85X3X ( z80scc_device::TYPE_SCC8530 | z80scc_device::TYPE_SCC85C30 | z80scc_device::TYPE_SCC85230 \
| z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 )
| z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 )
enum
{
@ -641,27 +641,28 @@ protected:
int m_rxcb;
int m_txcb;
devcb_write_line m_out_txda_cb;
devcb_write_line m_out_dtra_cb;
devcb_write_line m_out_rtsa_cb;
devcb_write_line m_out_wrdya_cb;
devcb_write_line m_out_synca_cb;
devcb_write_line m_out_txda_cb;
devcb_write_line m_out_dtra_cb;
devcb_write_line m_out_rtsa_cb;
devcb_write_line m_out_wrdya_cb;
devcb_write_line m_out_synca_cb;
devcb_write_line m_out_txdb_cb;
devcb_write_line m_out_dtrb_cb;
devcb_write_line m_out_rtsb_cb;
devcb_write_line m_out_wrdyb_cb;
devcb_write_line m_out_syncb_cb;
devcb_write_line m_out_txdb_cb;
devcb_write_line m_out_dtrb_cb;
devcb_write_line m_out_rtsb_cb;
devcb_write_line m_out_wrdyb_cb;
devcb_write_line m_out_syncb_cb;
devcb_write_line m_out_int_cb;
devcb_write_line m_out_rxdrqa_cb;
devcb_write_line m_out_txdrqa_cb;
devcb_write_line m_out_rxdrqb_cb;
devcb_write_line m_out_txdrqb_cb;
devcb_write_line m_out_int_cb;
devcb_write_line m_out_rxdrqa_cb;
devcb_write_line m_out_txdrqa_cb;
devcb_write_line m_out_rxdrqb_cb;
devcb_write_line m_out_txdrqb_cb;
int m_int_state[6]; // interrupt state
int m_int_state[6]; // interrupt state
int m_variant;
UINT8 m_wr0_ptrbits;
};
class scc8030_device : public z80scc_device

678
src/devices/machine/z80sio.c
View File

File diff suppressed because it is too large Load Diff

347
src/devices/machine/z80sio.h
View File

@ -59,7 +59,7 @@
#include "cpu/z80/z80daisy.h"
//**************************************************************************
// DEVICE CONFIGURATION MACROS
// DEVICE CONFIGURATION MACROS
//**************************************************************************
#define MCFG_Z80SIO_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
@ -116,7 +116,7 @@
//**************************************************************************
// TYPE DEFINITIONS
// TYPE DEFINITIONS
//**************************************************************************
// ======================> z80sio_channel
@ -142,22 +142,22 @@ public:
virtual void rcv_callback();
virtual void rcv_complete();
// read register handlers
UINT8 do_sioreg_rr0();
UINT8 do_sioreg_rr1();
UINT8 do_sioreg_rr2();
// write register handlers
void do_sioreg_wr0(UINT8 data);
void do_sioreg_wr0_resets(UINT8 data);
void do_sioreg_wr1(UINT8 data);
void do_sioreg_wr2(UINT8 data);
void do_sioreg_wr3(UINT8 data);
void do_sioreg_wr4(UINT8 data);
void do_sioreg_wr5(UINT8 data);
void do_sioreg_wr6(UINT8 data);
void do_sioreg_wr7(UINT8 data);
// read register handlers
UINT8 do_sioreg_rr0();
UINT8 do_sioreg_rr1();
UINT8 do_sioreg_rr2();
// write register handlers
void do_sioreg_wr0(UINT8 data);
void do_sioreg_wr0_resets(UINT8 data);
void do_sioreg_wr1(UINT8 data);
void do_sioreg_wr2(UINT8 data);
void do_sioreg_wr3(UINT8 data);
void do_sioreg_wr4(UINT8 data);
void do_sioreg_wr5(UINT8 data);
void do_sioreg_wr6(UINT8 data);
void do_sioreg_wr7(UINT8 data);
UINT8 control_read();
void control_write(UINT8 data);
@ -178,11 +178,11 @@ public:
int m_txc;
// Register state
// read registers enum
// read registers enum
UINT8 m_rr0; // REG_RR0_STATUS
UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND
UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT
// write registers enum
// write registers enum
UINT8 m_wr0; // REG_WR0_COMMAND_REGPT
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
UINT8 m_wr2; // REG_WR2_INT_VECTOR
@ -203,160 +203,160 @@ protected:
INT_SPECIAL
};
// Read registers
enum
{
REG_RR0_STATUS = 0,
REG_RR1_SPEC_RCV_COND = 1,
REG_RR2_INTERRUPT_VECT = 2
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0,
REG_WR1_INT_DMA_ENABLE = 1,
REG_WR2_INT_VECTOR = 2,
REG_WR3_RX_CONTROL = 3,
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR6_SYNC_OR_SDLC_A = 6,
REG_WR7_SYNC_OR_SDLC_F = 7
};
// Read registers
enum
{
RR0_RX_CHAR_AVAILABLE = 0x01,
RR0_INTERRUPT_PENDING = 0x02,
RR0_TX_BUFFER_EMPTY = 0x04,
RR0_DCD = 0x08,
RR0_SYNC_HUNT = 0x10,
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40,
RR0_BREAK_ABORT = 0x80
REG_RR0_STATUS = 0,
REG_RR1_SPEC_RCV_COND = 1,
REG_RR2_INTERRUPT_VECT = 2
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0,
REG_WR1_INT_DMA_ENABLE = 1,
REG_WR2_INT_VECTOR = 2,
REG_WR3_RX_CONTROL = 3,
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR6_SYNC_OR_SDLC_A = 6,
REG_WR7_SYNC_OR_SDLC_F = 7
};
enum
{
RR0_RX_CHAR_AVAILABLE = 0x01,
RR0_INTERRUPT_PENDING = 0x02,
RR0_TX_BUFFER_EMPTY = 0x04,
RR0_DCD = 0x08,
RR0_SYNC_HUNT = 0x10,
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40,
RR0_BREAK_ABORT = 0x80
};
enum
{
RR1_ALL_SENT = 0x01,
RR1_RESIDUE_CODE_MASK = 0x0e,
RR1_PARITY_ERROR = 0x10,
RR1_RX_OVERRUN_ERROR = 0x20,
RR1_CRC_FRAMING_ERROR = 0x40,
RR1_END_OF_FRAME = 0x80
RR1_ALL_SENT = 0x01,
RR1_RESIDUE_CODE_MASK = 0x0e,
RR1_PARITY_ERROR = 0x10,
RR1_RX_OVERRUN_ERROR = 0x20,
RR1_CRC_FRAMING_ERROR = 0x40,
RR1_END_OF_FRAME = 0x80
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38,
WR0_NULL = 0x00,
WR0_SEND_ABORT = 0x08, // not supported
WR0_RESET_EXT_STATUS = 0x10,
WR0_CHANNEL_RESET = 0x18,
WR0_ENABLE_INT_NEXT_RX = 0x20,
WR0_RESET_TX_INT = 0x28, // not supported
WR0_ERROR_RESET = 0x30,
WR0_RETURN_FROM_INT = 0x38, // not supported
WR0_CRC_RESET_CODE_MASK = 0xc0, // not supported
WR0_CRC_RESET_NULL = 0x00, // not supported
WR0_CRC_RESET_RX = 0x40, // not supported
WR0_CRC_RESET_TX = 0x80, // not supported
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38,
WR0_NULL = 0x00,
WR0_SEND_ABORT = 0x08, // not supported
WR0_RESET_EXT_STATUS = 0x10,
WR0_CHANNEL_RESET = 0x18,
WR0_ENABLE_INT_NEXT_RX = 0x20,
WR0_RESET_TX_INT = 0x28, // not supported
WR0_ERROR_RESET = 0x30,
WR0_RETURN_FROM_INT = 0x38, // not supported
WR0_CRC_RESET_CODE_MASK = 0xc0, // not supported
WR0_CRC_RESET_NULL = 0x00, // not supported
WR0_CRC_RESET_RX = 0x40, // not supported
WR0_CRC_RESET_TX = 0x80, // not supported
WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // not supported
};
enum
{
WR1_EXT_INT_ENABLE = 0x01,
WR1_TX_INT_ENABLE = 0x02,
WR1_STATUS_VECTOR = 0x04,
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
WR1_EXT_INT_ENABLE = 0x01,
WR1_TX_INT_ENABLE = 0x02,
WR1_STATUS_VECTOR = 0x04,
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
};
enum
{
WR2_DATA_XFER_INT = 0x00, // not supported
WR2_DATA_XFER_DMA_INT = 0x01, // not supported
WR2_DATA_XFER_DMA = 0x02, // not supported
WR2_DATA_XFER_ILLEGAL = 0x03, // not supported
WR2_DATA_XFER_MASK = 0x03, // not supported
WR2_PRIORITY = 0x04, // not supported
WR2_MODE_8085_1 = 0x00, // not supported
WR2_MODE_8085_2 = 0x08, // not supported
WR2_MODE_8086_8088 = 0x10, // not supported
WR2_MODE_ILLEGAL = 0x18, // not supported
WR2_MODE_MASK = 0x18, // not supported
WR2_VECTORED_INT = 0x20, // not supported
WR2_PIN10_SYNDETB_RTSB = 0x80 // not supported
WR2_DATA_XFER_INT = 0x00, // not supported
WR2_DATA_XFER_DMA_INT = 0x01, // not supported
WR2_DATA_XFER_DMA = 0x02, // not supported
WR2_DATA_XFER_ILLEGAL = 0x03, // not supported
WR2_DATA_XFER_MASK = 0x03, // not supported
WR2_PRIORITY = 0x04, // not supported
WR2_MODE_8085_1 = 0x00, // not supported
WR2_MODE_8085_2 = 0x08, // not supported
WR2_MODE_8086_8088 = 0x10, // not supported
WR2_MODE_ILLEGAL = 0x18, // not supported
WR2_MODE_MASK = 0x18, // not supported
WR2_VECTORED_INT = 0x20, // not supported
WR2_PIN10_SYNDETB_RTSB = 0x80 // not supported
};
enum
{
WR3_RX_ENABLE = 0x01,
WR3_RX_ENABLE = 0x01,
WR3_SYNC_CHAR_LOAD_INHIBIT= 0x02, // not supported
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
WR3_RX_WORD_LENGTH_6 = 0x80,
WR3_RX_WORD_LENGTH_8 = 0xc0
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
WR3_RX_WORD_LENGTH_6 = 0x80,
WR3_RX_WORD_LENGTH_8 = 0xc0
};
enum
{
WR4_PARITY_ENABLE = 0x01,
WR4_PARITY_EVEN = 0x02,
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
WR4_CLOCK_RATE_X32 = 0x80,
WR4_CLOCK_RATE_X64 = 0xc0
WR4_PARITY_ENABLE = 0x01,
WR4_PARITY_EVEN = 0x02,
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
WR4_CLOCK_RATE_X32 = 0x80,
WR4_CLOCK_RATE_X64 = 0xc0
};
enum
{
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
WR5_TX_WORD_LENGTH_7 = 0x20,
WR5_TX_WORD_LENGTH_8 = 0x60,
WR5_DTR = 0x80
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
WR5_TX_WORD_LENGTH_7 = 0x20,
WR5_TX_WORD_LENGTH_8 = 0x60,
WR5_DTR = 0x80
};
void update_serial();
void update_rts();
void update_rts();
void set_dtr(int state);
void set_rts(int state);
@ -366,30 +366,30 @@ protected:
int get_tx_word_length();
// receiver state
UINT8 m_rx_data_fifo[3]; // receive data FIFO
UINT8 m_rx_error_fifo[3]; // receive error FIFO
UINT8 m_rx_error; // current receive error
int m_rx_fifo; // receive FIFO pointer
UINT8 m_rx_data_fifo[3]; // receive data FIFO
UINT8 m_rx_error_fifo[3]; // receive error FIFO
UINT8 m_rx_error; // current receive error
int m_rx_fifo; // receive FIFO pointer
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd;
int m_sh; // sync hunt
int m_cts; // clear to send latch
int m_dcd; // data carrier detect latch
int m_sh; // sync hunt
int m_cts; // clear to send latch
int m_dcd; // data carrier detect latch
// transmitter state
UINT8 m_tx_data; // transmit data register
int m_tx_clock; // transmit clock pulse count
UINT8 m_tx_data; // transmit data register
int m_tx_clock; // transmit clock pulse count
int m_dtr; // data terminal ready
int m_rts; // request to send
int m_dtr; // data terminal ready
int m_rts; // request to send
// synchronous state
UINT16 m_sync; // sync character
UINT16 m_sync; // sync character
int m_index;
z80sio_device *m_uart;
@ -403,11 +403,11 @@ class z80sio_device : public device_t,
{
friend class z80sio_channel;
public:
public:
// construction/destruction
z80sio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
z80sio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
template<class _Object> static devcb_base &set_out_txda_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_txda_cb.set_callback(object); }
template<class _Object> static devcb_base &set_out_dtra_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_dtra_cb.set_callback(object); }
template<class _Object> static devcb_base &set_out_rtsa_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_rtsa_cb.set_callback(object); }
@ -504,26 +504,25 @@ protected:
int m_rxcb;
int m_txcb;
devcb_write_line m_out_txda_cb;
devcb_write_line m_out_dtra_cb;
devcb_write_line m_out_rtsa_cb;
devcb_write_line m_out_wrdya_cb;
devcb_write_line m_out_synca_cb;
devcb_write_line m_out_txda_cb;
devcb_write_line m_out_dtra_cb;
devcb_write_line m_out_rtsa_cb;
devcb_write_line m_out_wrdya_cb;
devcb_write_line m_out_synca_cb;
devcb_write_line m_out_txdb_cb;
devcb_write_line m_out_dtrb_cb;
devcb_write_line m_out_rtsb_cb;
devcb_write_line m_out_wrdyb_cb;
devcb_write_line m_out_syncb_cb;
devcb_write_line m_out_txdb_cb;
devcb_write_line m_out_dtrb_cb;
devcb_write_line m_out_rtsb_cb;
devcb_write_line m_out_wrdyb_cb;
devcb_write_line m_out_syncb_cb;
devcb_write_line m_out_int_cb;
devcb_write_line m_out_rxdrqa_cb;
devcb_write_line m_out_txdrqa_cb;
devcb_write_line m_out_rxdrqb_cb;
devcb_write_line m_out_txdrqb_cb;
int m_int_state[8]; // interrupt state
devcb_write_line m_out_int_cb;
devcb_write_line m_out_rxdrqa_cb;
devcb_write_line m_out_txdrqa_cb;
devcb_write_line m_out_rxdrqb_cb;
devcb_write_line m_out_txdrqb_cb;
int m_int_state[8]; // interrupt state
int m_variant;
};